/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_HW_NVRAM_GENERATED_TRACERS_H
#define TRACE_HW_NVRAM_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_ASPEED_OTP_PROG_EVENT;
extern TraceEvent _TRACE_ASPEED_OTP_PROG_CONFLICT_EVENT;
extern TraceEvent _TRACE_ASPEED_OTP_PROG_BIT_EVENT;
extern TraceEvent _TRACE_NVRAM_READ_EVENT;
extern TraceEvent _TRACE_NVRAM_WRITE_EVENT;
extern TraceEvent _TRACE_FW_CFG_SELECT_EVENT;
extern TraceEvent _TRACE_FW_CFG_READ_EVENT;
extern TraceEvent _TRACE_FW_CFG_ADD_BYTES_EVENT;
extern TraceEvent _TRACE_FW_CFG_ADD_FILE_EVENT;
extern TraceEvent _TRACE_FW_CFG_ADD_STRING_EVENT;
extern TraceEvent _TRACE_FW_CFG_ADD_I16_EVENT;
extern TraceEvent _TRACE_FW_CFG_ADD_I32_EVENT;
extern TraceEvent _TRACE_FW_CFG_ADD_I64_EVENT;
extern TraceEvent _TRACE_MACIO_NVRAM_READ_EVENT;
extern TraceEvent _TRACE_MACIO_NVRAM_WRITE_EVENT;
extern uint16_t _TRACE_ASPEED_OTP_PROG_DSTATE;
extern uint16_t _TRACE_ASPEED_OTP_PROG_CONFLICT_DSTATE;
extern uint16_t _TRACE_ASPEED_OTP_PROG_BIT_DSTATE;
extern uint16_t _TRACE_NVRAM_READ_DSTATE;
extern uint16_t _TRACE_NVRAM_WRITE_DSTATE;
extern uint16_t _TRACE_FW_CFG_SELECT_DSTATE;
extern uint16_t _TRACE_FW_CFG_READ_DSTATE;
extern uint16_t _TRACE_FW_CFG_ADD_BYTES_DSTATE;
extern uint16_t _TRACE_FW_CFG_ADD_FILE_DSTATE;
extern uint16_t _TRACE_FW_CFG_ADD_STRING_DSTATE;
extern uint16_t _TRACE_FW_CFG_ADD_I16_DSTATE;
extern uint16_t _TRACE_FW_CFG_ADD_I32_DSTATE;
extern uint16_t _TRACE_FW_CFG_ADD_I64_DSTATE;
extern uint16_t _TRACE_MACIO_NVRAM_READ_DSTATE;
extern uint16_t _TRACE_MACIO_NVRAM_WRITE_DSTATE;
#define TRACE_ASPEED_OTP_PROG_ENABLED 1
#define TRACE_ASPEED_OTP_PROG_CONFLICT_ENABLED 1
#define TRACE_ASPEED_OTP_PROG_BIT_ENABLED 1
#define TRACE_NVRAM_READ_ENABLED 1
#define TRACE_NVRAM_WRITE_ENABLED 1
#define TRACE_FW_CFG_SELECT_ENABLED 1
#define TRACE_FW_CFG_READ_ENABLED 1
#define TRACE_FW_CFG_ADD_BYTES_ENABLED 1
#define TRACE_FW_CFG_ADD_FILE_ENABLED 1
#define TRACE_FW_CFG_ADD_STRING_ENABLED 1
#define TRACE_FW_CFG_ADD_I16_ENABLED 1
#define TRACE_FW_CFG_ADD_I32_ENABLED 1
#define TRACE_FW_CFG_ADD_I64_ENABLED 1
#define TRACE_MACIO_NVRAM_READ_ENABLED 1
#define TRACE_MACIO_NVRAM_WRITE_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_ASPEED_OTP_PROG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_OTP_PROG) || \
    false)

static inline void trace_aspeed_otp_prog(uint32_t addr, uint32_t prog_value, uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_OTP_PROG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 4 "../xemu/hw/nvram/trace-events"
            qemu_log("aspeed_otp_prog " "OTP Memory program: addr 0x%" PRIx32 " prog_value 0x%" PRIx32 " value 0x%" PRIx32 "\n", addr, prog_value, value);
#line 68 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_ASPEED_OTP_PROG_CONFLICT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_OTP_PROG_CONFLICT) || \
    false)

static inline void trace_aspeed_otp_prog_conflict(uint32_t addr, uint32_t bits)
{
    if (trace_event_get_state(TRACE_ASPEED_OTP_PROG_CONFLICT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../xemu/hw/nvram/trace-events"
            qemu_log("aspeed_otp_prog_conflict " "Conflict at addr=0x%x, bits=0x%08x" "\n", addr, bits);
#line 83 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_ASPEED_OTP_PROG_BIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_OTP_PROG_BIT) || \
    false)

static inline void trace_aspeed_otp_prog_bit(int bit)
{
    if (trace_event_get_state(TRACE_ASPEED_OTP_PROG_BIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 6 "../xemu/hw/nvram/trace-events"
            qemu_log("aspeed_otp_prog_bit " "Programmed bit %d" "\n", bit);
#line 98 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_NVRAM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVRAM_READ) || \
    false)

static inline void trace_nvram_read(uint32_t addr, uint32_t ret)
{
    if (trace_event_get_state(TRACE_NVRAM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 9 "../xemu/hw/nvram/trace-events"
            qemu_log("nvram_read " "read addr %d: 0x%02x" "\n", addr, ret);
#line 113 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_NVRAM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVRAM_WRITE) || \
    false)

static inline void trace_nvram_write(uint32_t addr, uint32_t old, uint32_t val)
{
    if (trace_event_get_state(TRACE_NVRAM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 10 "../xemu/hw/nvram/trace-events"
            qemu_log("nvram_write " "write addr %d: 0x%02x -> 0x%02x" "\n", addr, old, val);
#line 128 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_FW_CFG_SELECT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_FW_CFG_SELECT) || \
    false)

static inline void trace_fw_cfg_select(void *s, uint16_t key_value, const char *key_name, int ret)
{
    if (trace_event_get_state(TRACE_FW_CFG_SELECT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 13 "../xemu/hw/nvram/trace-events"
            qemu_log("fw_cfg_select " "%p key 0x%04" PRIx16 " '%s', ret: %d" "\n", s, key_value, key_name, ret);
#line 143 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_FW_CFG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_FW_CFG_READ) || \
    false)

static inline void trace_fw_cfg_read(void *s, uint64_t ret)
{
    if (trace_event_get_state(TRACE_FW_CFG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 14 "../xemu/hw/nvram/trace-events"
            qemu_log("fw_cfg_read " "%p = 0x%"PRIx64 "\n", s, ret);
#line 158 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_FW_CFG_ADD_BYTES_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_FW_CFG_ADD_BYTES) || \
    false)

static inline void trace_fw_cfg_add_bytes(uint16_t key_value, const char *key_name, size_t len)
{
    if (trace_event_get_state(TRACE_FW_CFG_ADD_BYTES)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../xemu/hw/nvram/trace-events"
            qemu_log("fw_cfg_add_bytes " "key 0x%04" PRIx16 " '%s', %zu bytes" "\n", key_value, key_name, len);
#line 173 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_FW_CFG_ADD_FILE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_FW_CFG_ADD_FILE) || \
    false)

static inline void trace_fw_cfg_add_file(void *s, int index, char *name, size_t len)
{
    if (trace_event_get_state(TRACE_FW_CFG_ADD_FILE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 16 "../xemu/hw/nvram/trace-events"
            qemu_log("fw_cfg_add_file " "%p #%d: %s (%zd bytes)" "\n", s, index, name, len);
#line 188 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_FW_CFG_ADD_STRING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_FW_CFG_ADD_STRING) || \
    false)

static inline void trace_fw_cfg_add_string(uint16_t key_value, const char *key_name, const char *value)
{
    if (trace_event_get_state(TRACE_FW_CFG_ADD_STRING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 17 "../xemu/hw/nvram/trace-events"
            qemu_log("fw_cfg_add_string " "key 0x%04" PRIx16 " '%s', value '%s'" "\n", key_value, key_name, value);
#line 203 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_FW_CFG_ADD_I16_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_FW_CFG_ADD_I16) || \
    false)

static inline void trace_fw_cfg_add_i16(uint16_t key_value, const char *key_name, uint16_t value)
{
    if (trace_event_get_state(TRACE_FW_CFG_ADD_I16)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 18 "../xemu/hw/nvram/trace-events"
            qemu_log("fw_cfg_add_i16 " "key 0x%04" PRIx16 " '%s', value 0x%" PRIx16 "\n", key_value, key_name, value);
#line 218 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_FW_CFG_ADD_I32_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_FW_CFG_ADD_I32) || \
    false)

static inline void trace_fw_cfg_add_i32(uint16_t key_value, const char *key_name, uint32_t value)
{
    if (trace_event_get_state(TRACE_FW_CFG_ADD_I32)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 19 "../xemu/hw/nvram/trace-events"
            qemu_log("fw_cfg_add_i32 " "key 0x%04" PRIx16 " '%s', value 0x%" PRIx32 "\n", key_value, key_name, value);
#line 233 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_FW_CFG_ADD_I64_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_FW_CFG_ADD_I64) || \
    false)

static inline void trace_fw_cfg_add_i64(uint16_t key_value, const char *key_name, uint64_t value)
{
    if (trace_event_get_state(TRACE_FW_CFG_ADD_I64)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 20 "../xemu/hw/nvram/trace-events"
            qemu_log("fw_cfg_add_i64 " "key 0x%04" PRIx16 " '%s', value 0x%" PRIx64 "\n", key_value, key_name, value);
#line 248 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_MACIO_NVRAM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MACIO_NVRAM_READ) || \
    false)

static inline void trace_macio_nvram_read(uint32_t addr, uint8_t val)
{
    if (trace_event_get_state(TRACE_MACIO_NVRAM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 23 "../xemu/hw/nvram/trace-events"
            qemu_log("macio_nvram_read " "read addr=0x%04"PRIx32" val=0x%02x" "\n", addr, val);
#line 263 "trace/trace-hw_nvram.h"
        }
    }
}

#define TRACE_MACIO_NVRAM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MACIO_NVRAM_WRITE) || \
    false)

static inline void trace_macio_nvram_write(uint32_t addr, uint8_t val)
{
    if (trace_event_get_state(TRACE_MACIO_NVRAM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 24 "../xemu/hw/nvram/trace-events"
            qemu_log("macio_nvram_write " "write addr=0x%04"PRIx32" val=0x%02x" "\n", addr, val);
#line 278 "trace/trace-hw_nvram.h"
        }
    }
}
#endif /* TRACE_HW_NVRAM_GENERATED_TRACERS_H */
