/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_HW_I2C_GENERATED_TRACERS_H
#define TRACE_HW_I2C_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_BITBANG_I2C_STATE_EVENT;
extern TraceEvent _TRACE_BITBANG_I2C_ADDR_EVENT;
extern TraceEvent _TRACE_BITBANG_I2C_SEND_EVENT;
extern TraceEvent _TRACE_BITBANG_I2C_RECV_EVENT;
extern TraceEvent _TRACE_BITBANG_I2C_DATA_EVENT;
extern TraceEvent _TRACE_I2C_EVENT_EVENT;
extern TraceEvent _TRACE_I2C_SEND_EVENT;
extern TraceEvent _TRACE_I2C_SEND_ASYNC_EVENT;
extern TraceEvent _TRACE_I2C_RECV_EVENT;
extern TraceEvent _TRACE_I2C_ACK_EVENT;
extern TraceEvent _TRACE_SMBUS_IOPORT_READB_EVENT;
extern TraceEvent _TRACE_SMBUS_IOPORT_WRITEB_EVENT;
extern TraceEvent _TRACE_SMBUS_TRANSACTION_EVENT;
extern TraceEvent _TRACE_ALLWINNER_I2C_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_I2C_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_I2C_BUS_CMD_EVENT;
extern TraceEvent _TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT_EVENT;
extern TraceEvent _TRACE_ASPEED_I2C_BUS_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_I2C_BUS_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_I2C_BUS_SEND_EVENT;
extern TraceEvent _TRACE_ASPEED_I2C_BUS_RECV_EVENT;
extern TraceEvent _TRACE_MPC_I2C_READ_EVENT;
extern TraceEvent _TRACE_MPC_I2C_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_READ_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_START_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_SEND_ADDRESS_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_SEND_BYTE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_RECV_BYTE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_STOP_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_NACK_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_RECV_FIFO_EVENT;
extern TraceEvent _TRACE_PCA954X_WRITE_BYTES_EVENT;
extern TraceEvent _TRACE_PCA954X_READ_DATA_EVENT;
extern TraceEvent _TRACE_IMX_I2C_READ_EVENT;
extern TraceEvent _TRACE_IMX_I2C_WRITE_EVENT;
extern uint16_t _TRACE_BITBANG_I2C_STATE_DSTATE;
extern uint16_t _TRACE_BITBANG_I2C_ADDR_DSTATE;
extern uint16_t _TRACE_BITBANG_I2C_SEND_DSTATE;
extern uint16_t _TRACE_BITBANG_I2C_RECV_DSTATE;
extern uint16_t _TRACE_BITBANG_I2C_DATA_DSTATE;
extern uint16_t _TRACE_I2C_EVENT_DSTATE;
extern uint16_t _TRACE_I2C_SEND_DSTATE;
extern uint16_t _TRACE_I2C_SEND_ASYNC_DSTATE;
extern uint16_t _TRACE_I2C_RECV_DSTATE;
extern uint16_t _TRACE_I2C_ACK_DSTATE;
extern uint16_t _TRACE_SMBUS_IOPORT_READB_DSTATE;
extern uint16_t _TRACE_SMBUS_IOPORT_WRITEB_DSTATE;
extern uint16_t _TRACE_SMBUS_TRANSACTION_DSTATE;
extern uint16_t _TRACE_ALLWINNER_I2C_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_I2C_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_I2C_BUS_CMD_DSTATE;
extern uint16_t _TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT_DSTATE;
extern uint16_t _TRACE_ASPEED_I2C_BUS_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_I2C_BUS_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_I2C_BUS_SEND_DSTATE;
extern uint16_t _TRACE_ASPEED_I2C_BUS_RECV_DSTATE;
extern uint16_t _TRACE_MPC_I2C_READ_DSTATE;
extern uint16_t _TRACE_MPC_I2C_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_READ_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_START_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_SEND_ADDRESS_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_SEND_BYTE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_RECV_BYTE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_STOP_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_NACK_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_RECV_FIFO_DSTATE;
extern uint16_t _TRACE_PCA954X_WRITE_BYTES_DSTATE;
extern uint16_t _TRACE_PCA954X_READ_DATA_DSTATE;
extern uint16_t _TRACE_IMX_I2C_READ_DSTATE;
extern uint16_t _TRACE_IMX_I2C_WRITE_DSTATE;
#define TRACE_BITBANG_I2C_STATE_ENABLED 1
#define TRACE_BITBANG_I2C_ADDR_ENABLED 1
#define TRACE_BITBANG_I2C_SEND_ENABLED 1
#define TRACE_BITBANG_I2C_RECV_ENABLED 1
#define TRACE_BITBANG_I2C_DATA_ENABLED 1
#define TRACE_I2C_EVENT_ENABLED 1
#define TRACE_I2C_SEND_ENABLED 1
#define TRACE_I2C_SEND_ASYNC_ENABLED 1
#define TRACE_I2C_RECV_ENABLED 1
#define TRACE_I2C_ACK_ENABLED 1
#define TRACE_SMBUS_IOPORT_READB_ENABLED 1
#define TRACE_SMBUS_IOPORT_WRITEB_ENABLED 1
#define TRACE_SMBUS_TRANSACTION_ENABLED 1
#define TRACE_ALLWINNER_I2C_READ_ENABLED 1
#define TRACE_ALLWINNER_I2C_WRITE_ENABLED 1
#define TRACE_ASPEED_I2C_BUS_CMD_ENABLED 1
#define TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT_ENABLED 1
#define TRACE_ASPEED_I2C_BUS_READ_ENABLED 1
#define TRACE_ASPEED_I2C_BUS_WRITE_ENABLED 1
#define TRACE_ASPEED_I2C_BUS_SEND_ENABLED 1
#define TRACE_ASPEED_I2C_BUS_RECV_ENABLED 1
#define TRACE_MPC_I2C_READ_ENABLED 1
#define TRACE_MPC_I2C_WRITE_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_READ_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_WRITE_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_START_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_SEND_ADDRESS_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_SEND_BYTE_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_RECV_BYTE_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_STOP_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_NACK_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_RECV_FIFO_ENABLED 1
#define TRACE_PCA954X_WRITE_BYTES_ENABLED 1
#define TRACE_PCA954X_READ_DATA_ENABLED 1
#define TRACE_IMX_I2C_READ_ENABLED 1
#define TRACE_IMX_I2C_WRITE_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_BITBANG_I2C_STATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BITBANG_I2C_STATE) || \
    false)

static inline void trace_bitbang_i2c_state(const char *old_state, const char *new_state)
{
    if (trace_event_get_state(TRACE_BITBANG_I2C_STATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 4 "../xemu/hw/i2c/trace-events"
            qemu_log("bitbang_i2c_state " "state %s -> %s" "\n", old_state, new_state);
#line 131 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_BITBANG_I2C_ADDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BITBANG_I2C_ADDR) || \
    false)

static inline void trace_bitbang_i2c_addr(uint8_t addr)
{
    if (trace_event_get_state(TRACE_BITBANG_I2C_ADDR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../xemu/hw/i2c/trace-events"
            qemu_log("bitbang_i2c_addr " "Address 0x%02x" "\n", addr);
#line 146 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_BITBANG_I2C_SEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BITBANG_I2C_SEND) || \
    false)

static inline void trace_bitbang_i2c_send(uint8_t byte)
{
    if (trace_event_get_state(TRACE_BITBANG_I2C_SEND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 6 "../xemu/hw/i2c/trace-events"
            qemu_log("bitbang_i2c_send " "TX byte 0x%02x" "\n", byte);
#line 161 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_BITBANG_I2C_RECV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BITBANG_I2C_RECV) || \
    false)

static inline void trace_bitbang_i2c_recv(uint8_t byte)
{
    if (trace_event_get_state(TRACE_BITBANG_I2C_RECV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 7 "../xemu/hw/i2c/trace-events"
            qemu_log("bitbang_i2c_recv " "RX byte 0x%02x" "\n", byte);
#line 176 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_BITBANG_I2C_DATA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BITBANG_I2C_DATA) || \
    false)

static inline void trace_bitbang_i2c_data(unsigned clk, unsigned dat, unsigned old_out, unsigned new_out)
{
    if (trace_event_get_state(TRACE_BITBANG_I2C_DATA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 8 "../xemu/hw/i2c/trace-events"
            qemu_log("bitbang_i2c_data " "clk %u dat %u out %u -> %u" "\n", clk, dat, old_out, new_out);
#line 191 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_I2C_EVENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_EVENT) || \
    false)

static inline void trace_i2c_event(const char *event, uint8_t address)
{
    if (trace_event_get_state(TRACE_I2C_EVENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 12 "../xemu/hw/i2c/trace-events"
            qemu_log("i2c_event " "%s(addr:0x%02x)" "\n", event, address);
#line 206 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_I2C_SEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_SEND) || \
    false)

static inline void trace_i2c_send(uint8_t address, uint8_t data)
{
    if (trace_event_get_state(TRACE_I2C_SEND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 13 "../xemu/hw/i2c/trace-events"
            qemu_log("i2c_send " "send(addr:0x%02x) data:0x%02x" "\n", address, data);
#line 221 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_I2C_SEND_ASYNC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_SEND_ASYNC) || \
    false)

static inline void trace_i2c_send_async(uint8_t address, uint8_t data)
{
    if (trace_event_get_state(TRACE_I2C_SEND_ASYNC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 14 "../xemu/hw/i2c/trace-events"
            qemu_log("i2c_send_async " "send_async(addr:0x%02x) data:0x%02x" "\n", address, data);
#line 236 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_I2C_RECV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_RECV) || \
    false)

static inline void trace_i2c_recv(uint8_t address, uint8_t data)
{
    if (trace_event_get_state(TRACE_I2C_RECV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../xemu/hw/i2c/trace-events"
            qemu_log("i2c_recv " "recv(addr:0x%02x) data:0x%02x" "\n", address, data);
#line 251 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_I2C_ACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_ACK) || \
    false)

static inline void trace_i2c_ack(void)
{
    if (trace_event_get_state(TRACE_I2C_ACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 16 "../xemu/hw/i2c/trace-events"
            qemu_log("i2c_ack " "" "\n");
#line 266 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_SMBUS_IOPORT_READB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SMBUS_IOPORT_READB) || \
    false)

static inline void trace_smbus_ioport_readb(uint16_t addr, uint8_t data)
{
    if (trace_event_get_state(TRACE_SMBUS_IOPORT_READB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 20 "../xemu/hw/i2c/trace-events"
            qemu_log("smbus_ioport_readb " "[0x%04" PRIx16 "] -> val=0x%02x" "\n", addr, data);
#line 281 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_SMBUS_IOPORT_WRITEB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SMBUS_IOPORT_WRITEB) || \
    false)

static inline void trace_smbus_ioport_writeb(uint16_t addr, uint8_t data)
{
    if (trace_event_get_state(TRACE_SMBUS_IOPORT_WRITEB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 21 "../xemu/hw/i2c/trace-events"
            qemu_log("smbus_ioport_writeb " "[0x%04" PRIx16 "] <- val=0x%02x" "\n", addr, data);
#line 296 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_SMBUS_TRANSACTION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SMBUS_TRANSACTION) || \
    false)

static inline void trace_smbus_transaction(uint8_t addr, uint8_t prot)
{
    if (trace_event_get_state(TRACE_SMBUS_TRANSACTION)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 22 "../xemu/hw/i2c/trace-events"
            qemu_log("smbus_transaction " "addr=0x%02x prot=0x%02x" "\n", addr, prot);
#line 311 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_ALLWINNER_I2C_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_I2C_READ) || \
    false)

static inline void trace_allwinner_i2c_read(const char*reg_name, uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_ALLWINNER_I2C_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 26 "../xemu/hw/i2c/trace-events"
            qemu_log("allwinner_i2c_read " "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64 "\n", reg_name, offset, value);
#line 326 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_ALLWINNER_I2C_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_I2C_WRITE) || \
    false)

static inline void trace_allwinner_i2c_write(const char*reg_name, uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_ALLWINNER_I2C_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 27 "../xemu/hw/i2c/trace-events"
            qemu_log("allwinner_i2c_write " "write %s [0x%" PRIx64 "]: <- 0x%" PRIx64 "\n", reg_name, offset, value);
#line 341 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_ASPEED_I2C_BUS_CMD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I2C_BUS_CMD) || \
    false)

static inline void trace_aspeed_i2c_bus_cmd(uint32_t cmd, const char *cmd_flags, uint32_t count, uint32_t intr_status)
{
    if (trace_event_get_state(TRACE_ASPEED_I2C_BUS_CMD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 31 "../xemu/hw/i2c/trace-events"
            qemu_log("aspeed_i2c_bus_cmd " "handling cmd=0x%x %s count=%d intr=0x%x" "\n", cmd, cmd_flags, count, intr_status);
#line 356 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT) || \
    false)

static inline void trace_aspeed_i2c_bus_raise_interrupt(uint32_t intr_status, const char *s)
{
    if (trace_event_get_state(TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 32 "../xemu/hw/i2c/trace-events"
            qemu_log("aspeed_i2c_bus_raise_interrupt " "handled intr=0x%x %s" "\n", intr_status, s);
#line 371 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_ASPEED_I2C_BUS_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I2C_BUS_READ) || \
    false)

static inline void trace_aspeed_i2c_bus_read(uint32_t busid, uint64_t offset, unsigned size, uint64_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_I2C_BUS_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 33 "../xemu/hw/i2c/trace-events"
            qemu_log("aspeed_i2c_bus_read " "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64 "\n", busid, offset, size, value);
#line 386 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_ASPEED_I2C_BUS_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I2C_BUS_WRITE) || \
    false)

static inline void trace_aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint64_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_I2C_BUS_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 34 "../xemu/hw/i2c/trace-events"
            qemu_log("aspeed_i2c_bus_write " "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64 "\n", busid, offset, size, value);
#line 401 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_ASPEED_I2C_BUS_SEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I2C_BUS_SEND) || \
    false)

static inline void trace_aspeed_i2c_bus_send(const char *mode, int i, int count, uint8_t byte)
{
    if (trace_event_get_state(TRACE_ASPEED_I2C_BUS_SEND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 35 "../xemu/hw/i2c/trace-events"
            qemu_log("aspeed_i2c_bus_send " "%s send %d/%d 0x%02x" "\n", mode, i, count, byte);
#line 416 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_ASPEED_I2C_BUS_RECV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I2C_BUS_RECV) || \
    false)

static inline void trace_aspeed_i2c_bus_recv(const char *mode, int i, int count, uint8_t byte)
{
    if (trace_event_get_state(TRACE_ASPEED_I2C_BUS_RECV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 36 "../xemu/hw/i2c/trace-events"
            qemu_log("aspeed_i2c_bus_recv " "%s recv %d/%d 0x%02x" "\n", mode, i, count, byte);
#line 431 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_MPC_I2C_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MPC_I2C_READ) || \
    false)

static inline void trace_mpc_i2c_read(uint64_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_MPC_I2C_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 40 "../xemu/hw/i2c/trace-events"
            qemu_log("mpc_i2c_read " "[0x%" PRIx64 "] -> 0x%02" PRIx32 "\n", addr, value);
#line 446 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_MPC_I2C_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MPC_I2C_WRITE) || \
    false)

static inline void trace_mpc_i2c_write(uint64_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_MPC_I2C_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 41 "../xemu/hw/i2c/trace-events"
            qemu_log("mpc_i2c_write " "[0x%" PRIx64 "] <- 0x%02" PRIx32 "\n", addr, value);
#line 461 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_NPCM7XX_SMBUS_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_READ) || \
    false)

static inline void trace_npcm7xx_smbus_read(const char *id, uint64_t offset, uint64_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 45 "../xemu/hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_read " "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" "\n", id, offset, value, size);
#line 476 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_NPCM7XX_SMBUS_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_WRITE) || \
    false)

static inline void trace_npcm7xx_smbus_write(const char *id, uint64_t offset, uint64_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 46 "../xemu/hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_write " "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" "\n", id, offset, value, size);
#line 491 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_NPCM7XX_SMBUS_START_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_START) || \
    false)

static inline void trace_npcm7xx_smbus_start(const char *id, int success)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_START)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 47 "../xemu/hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_start " "%s starting, success: %d" "\n", id, success);
#line 506 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_NPCM7XX_SMBUS_SEND_ADDRESS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_SEND_ADDRESS) || \
    false)

static inline void trace_npcm7xx_smbus_send_address(const char *id, uint8_t addr, int recv, int success)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_SEND_ADDRESS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 48 "../xemu/hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_send_address " "%s sending address: 0x%02x, recv: %d, success: %d" "\n", id, addr, recv, success);
#line 521 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_NPCM7XX_SMBUS_SEND_BYTE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_SEND_BYTE) || \
    false)

static inline void trace_npcm7xx_smbus_send_byte(const char *id, uint8_t value, int success)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_SEND_BYTE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 49 "../xemu/hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_send_byte " "%s send byte: 0x%02x, success: %d" "\n", id, value, success);
#line 536 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_NPCM7XX_SMBUS_RECV_BYTE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_RECV_BYTE) || \
    false)

static inline void trace_npcm7xx_smbus_recv_byte(const char *id, uint8_t value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_RECV_BYTE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 50 "../xemu/hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_recv_byte " "%s recv byte: 0x%02x" "\n", id, value);
#line 551 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_NPCM7XX_SMBUS_STOP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_STOP) || \
    false)

static inline void trace_npcm7xx_smbus_stop(const char *id)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_STOP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 51 "../xemu/hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_stop " "%s stopping" "\n", id);
#line 566 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_NPCM7XX_SMBUS_NACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_NACK) || \
    false)

static inline void trace_npcm7xx_smbus_nack(const char *id)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_NACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 52 "../xemu/hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_nack " "%s nacking" "\n", id);
#line 581 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_NPCM7XX_SMBUS_RECV_FIFO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_RECV_FIFO) || \
    false)

static inline void trace_npcm7xx_smbus_recv_fifo(const char *id, uint8_t received, uint8_t expected)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_RECV_FIFO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 53 "../xemu/hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_recv_fifo " "%s recv fifo: received %u, expected %u" "\n", id, received, expected);
#line 596 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_PCA954X_WRITE_BYTES_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCA954X_WRITE_BYTES) || \
    false)

static inline void trace_pca954x_write_bytes(uint8_t value)
{
    if (trace_event_get_state(TRACE_PCA954X_WRITE_BYTES)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 57 "../xemu/hw/i2c/trace-events"
            qemu_log("pca954x_write_bytes " "PCA954X write data: 0x%02x" "\n", value);
#line 611 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_PCA954X_READ_DATA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCA954X_READ_DATA) || \
    false)

static inline void trace_pca954x_read_data(uint8_t value)
{
    if (trace_event_get_state(TRACE_PCA954X_READ_DATA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 58 "../xemu/hw/i2c/trace-events"
            qemu_log("pca954x_read_data " "PCA954X read data: 0x%02x" "\n", value);
#line 626 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_IMX_I2C_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_I2C_READ) || \
    false)

static inline void trace_imx_i2c_read(const char *id, const char *reg, uint64_t ofs, uint64_t value)
{
    if (trace_event_get_state(TRACE_IMX_I2C_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 62 "../xemu/hw/i2c/trace-events"
            qemu_log("imx_i2c_read " "%s:[%s (0x%" PRIx64 ")] -> 0x%02" PRIx64 "\n", id, reg, ofs, value);
#line 641 "trace/trace-hw_i2c.h"
        }
    }
}

#define TRACE_IMX_I2C_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_I2C_WRITE) || \
    false)

static inline void trace_imx_i2c_write(const char *id, const char *reg, uint64_t ofs, uint64_t value)
{
    if (trace_event_get_state(TRACE_IMX_I2C_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 63 "../xemu/hw/i2c/trace-events"
            qemu_log("imx_i2c_write " "%s:[%s (0x%" PRIx64 ")] <- 0x%02" PRIx64 "\n", id, reg, ofs, value);
#line 656 "trace/trace-hw_i2c.h"
        }
    }
}
#endif /* TRACE_HW_I2C_GENERATED_TRACERS_H */
