/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_HW_INTC_GENERATED_TRACERS_H
#define TRACE_HW_INTC_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_PIC_UPDATE_IRQ_EVENT;
extern TraceEvent _TRACE_PIC_SET_IRQ_EVENT;
extern TraceEvent _TRACE_PIC_INTERRUPT_EVENT;
extern TraceEvent _TRACE_PIC_IOPORT_WRITE_EVENT;
extern TraceEvent _TRACE_PIC_IOPORT_READ_EVENT;
extern TraceEvent _TRACE_CPU_SET_APIC_BASE_EVENT;
extern TraceEvent _TRACE_CPU_GET_APIC_BASE_EVENT;
extern TraceEvent _TRACE_APIC_LOCAL_DELIVER_EVENT;
extern TraceEvent _TRACE_APIC_DELIVER_IRQ_EVENT;
extern TraceEvent _TRACE_APIC_REGISTER_READ_EVENT;
extern TraceEvent _TRACE_APIC_REGISTER_WRITE_EVENT;
extern TraceEvent _TRACE_IOAPIC_SET_REMOTE_IRR_EVENT;
extern TraceEvent _TRACE_IOAPIC_CLEAR_REMOTE_IRR_EVENT;
extern TraceEvent _TRACE_IOAPIC_EOI_BROADCAST_EVENT;
extern TraceEvent _TRACE_IOAPIC_EOI_DELAYED_REASSERT_EVENT;
extern TraceEvent _TRACE_IOAPIC_MEM_READ_EVENT;
extern TraceEvent _TRACE_IOAPIC_MEM_WRITE_EVENT;
extern TraceEvent _TRACE_IOAPIC_SET_IRQ_EVENT;
extern TraceEvent _TRACE_KVM_REPORT_IRQ_DELIVERED_EVENT;
extern TraceEvent _TRACE_KVM_RESET_IRQ_DELIVERED_EVENT;
extern TraceEvent _TRACE_KVM_GET_IRQ_DELIVERED_EVENT;
extern TraceEvent _TRACE_SLAVIO_INTCTL_MEM_READL_EVENT;
extern TraceEvent _TRACE_SLAVIO_INTCTL_MEM_WRITEL_EVENT;
extern TraceEvent _TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_EVENT;
extern TraceEvent _TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_EVENT;
extern TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_READL_EVENT;
extern TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_EVENT;
extern TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_EVENT;
extern TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_EVENT;
extern TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_EVENT;
extern TraceEvent _TRACE_SLAVIO_CHECK_INTERRUPTS_EVENT;
extern TraceEvent _TRACE_SLAVIO_SET_IRQ_EVENT;
extern TraceEvent _TRACE_SLAVIO_SET_TIMER_IRQ_CPU_EVENT;
extern TraceEvent _TRACE_GRLIB_IRQMP_CHECK_IRQS_EVENT;
extern TraceEvent _TRACE_GRLIB_IRQMP_ACK_EVENT;
extern TraceEvent _TRACE_GRLIB_IRQMP_SET_IRQ_EVENT;
extern TraceEvent _TRACE_GRLIB_IRQMP_READL_UNKNOWN_EVENT;
extern TraceEvent _TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_EVENT;
extern TraceEvent _TRACE_XICS_ICP_CHECK_IPI_EVENT;
extern TraceEvent _TRACE_XICS_ICP_ACCEPT_EVENT;
extern TraceEvent _TRACE_XICS_ICP_EOI_EVENT;
extern TraceEvent _TRACE_XICS_ICP_IRQ_EVENT;
extern TraceEvent _TRACE_XICS_ICP_RAISE_EVENT;
extern TraceEvent _TRACE_XICS_ICS_SET_IRQ_MSI_EVENT;
extern TraceEvent _TRACE_XICS_MASKED_PENDING_EVENT;
extern TraceEvent _TRACE_XICS_ICS_SET_IRQ_LSI_EVENT;
extern TraceEvent _TRACE_XICS_ICS_WRITE_XIVE_EVENT;
extern TraceEvent _TRACE_XICS_ICS_REJECT_EVENT;
extern TraceEvent _TRACE_XICS_ICS_EOI_EVENT;
extern TraceEvent _TRACE_FLIC_CREATE_DEVICE_EVENT;
extern TraceEvent _TRACE_FLIC_RESET_FAILED_EVENT;
extern TraceEvent _TRACE_QEMU_S390_AIRQ_SUPPRESSED_EVENT;
extern TraceEvent _TRACE_QEMU_S390_SUPPRESS_AIRQ_EVENT;
extern TraceEvent _TRACE_ASPEED_VIC_SET_IRQ_EVENT;
extern TraceEvent _TRACE_ASPEED_VIC_UPDATE_FIQ_EVENT;
extern TraceEvent _TRACE_ASPEED_VIC_UPDATE_IRQ_EVENT;
extern TraceEvent _TRACE_ASPEED_VIC_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_VIC_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_SET_IRQ_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_CLEAR_IRQ_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_UPDATE_IRQ_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_PENDING_IRQ_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_TRIGGER_IRQ_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_ALL_ISR_DONE_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_ENABLE_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_SELECT_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_MASK_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_UNMASK_EVENT;
extern TraceEvent _TRACE_ASPEED_INTC_ALL_ISR_DONE_BIT_EVENT;
extern TraceEvent _TRACE_GIC_ENABLE_IRQ_EVENT;
extern TraceEvent _TRACE_GIC_DISABLE_IRQ_EVENT;
extern TraceEvent _TRACE_GIC_SET_IRQ_EVENT;
extern TraceEvent _TRACE_GIC_UPDATE_BESTIRQ_EVENT;
extern TraceEvent _TRACE_GIC_UPDATE_SET_IRQ_EVENT;
extern TraceEvent _TRACE_GIC_ACKNOWLEDGE_IRQ_EVENT;
extern TraceEvent _TRACE_GIC_CPU_WRITE_EVENT;
extern TraceEvent _TRACE_GIC_CPU_READ_EVENT;
extern TraceEvent _TRACE_GIC_HYP_READ_EVENT;
extern TraceEvent _TRACE_GIC_HYP_WRITE_EVENT;
extern TraceEvent _TRACE_GIC_DIST_READ_EVENT;
extern TraceEvent _TRACE_GIC_DIST_WRITE_EVENT;
extern TraceEvent _TRACE_GIC_LR_ENTRY_EVENT;
extern TraceEvent _TRACE_GIC_UPDATE_MAINTENANCE_IRQ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_PMR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_PMR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_BPR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_BPR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_AP_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_AP_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_IGRPEN_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_IGRPEN_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_IGRPEN1_EL3_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_CTLR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_CTLR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_CTLR_EL3_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_CTLR_EL3_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_CPUIF_UPDATE_EVENT;
extern TraceEvent _TRACE_GICV3_CPUIF_SET_IRQS_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_GENERATE_SGI_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_IAR0_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_IAR1_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_NMIAR1_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_EOIR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_HPPIR0_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_HPPIR1_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_DIR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICC_RPR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_AP_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_AP_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_HCR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_HCR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_VMCR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_VMCR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_LR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_LR32_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_LRC_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_LR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_LR32_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_LRC_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_VTR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_MISR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_EISR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICH_ELRSR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_AP_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_AP_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_BPR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_BPR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_PMR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_PMR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_IGRPEN_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_IGRPEN_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_CTLR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_CTLR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_RPR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_HPPIR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_DIR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_IAR_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_NMIAR1_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ICV_EOIR_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_CPUIF_VIRT_UPDATE_EVENT;
extern TraceEvent _TRACE_GICV3_CPUIF_VIRT_SET_IRQS_EVENT;
extern TraceEvent _TRACE_GICV3_CPUIF_VIRT_SET_MAINT_IRQ_EVENT;
extern TraceEvent _TRACE_GICV3_DIST_READ_EVENT;
extern TraceEvent _TRACE_GICV3_DIST_BADREAD_EVENT;
extern TraceEvent _TRACE_GICV3_DIST_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_DIST_BADWRITE_EVENT;
extern TraceEvent _TRACE_GICV3_DIST_SET_IRQ_EVENT;
extern TraceEvent _TRACE_GICV3_REDIST_READ_EVENT;
extern TraceEvent _TRACE_GICV3_REDIST_BADREAD_EVENT;
extern TraceEvent _TRACE_GICV3_REDIST_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_REDIST_BADWRITE_EVENT;
extern TraceEvent _TRACE_GICV3_REDIST_SET_IRQ_EVENT;
extern TraceEvent _TRACE_GICV3_REDIST_SEND_SGI_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_BADREAD_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_BADWRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_TRANSLATION_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_PROCESS_COMMAND_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_INT_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_CLEAR_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_DISCARD_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_SYNC_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_MAPD_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_MAPC_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_MAPI_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_MAPTI_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_INV_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_INVALL_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_MOVALL_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_MOVI_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_VMAPI_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_VMAPTI_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_VMAPP_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_VMOVP_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_VSYNC_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_VMOVI_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_VINVALL_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CMD_UNKNOWN_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CTE_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CTE_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_CTE_READ_FAULT_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_ITE_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_ITE_READ_FAULT_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_ITE_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_DTE_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_DTE_WRITE_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_DTE_READ_FAULT_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_VTE_READ_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_VTE_READ_FAULT_EVENT;
extern TraceEvent _TRACE_GICV3_ITS_VTE_WRITE_EVENT;
extern TraceEvent _TRACE_NVIC_RECOMPUTE_STATE_EVENT;
extern TraceEvent _TRACE_NVIC_RECOMPUTE_STATE_SECURE_EVENT;
extern TraceEvent _TRACE_NVIC_SET_PRIO_EVENT;
extern TraceEvent _TRACE_NVIC_IRQ_UPDATE_EVENT;
extern TraceEvent _TRACE_NVIC_ESCALATE_PRIO_EVENT;
extern TraceEvent _TRACE_NVIC_ESCALATE_DISABLED_EVENT;
extern TraceEvent _TRACE_NVIC_SET_PENDING_EVENT;
extern TraceEvent _TRACE_NVIC_CLEAR_PENDING_EVENT;
extern TraceEvent _TRACE_NVIC_ACKNOWLEDGE_IRQ_EVENT;
extern TraceEvent _TRACE_NVIC_GET_PENDING_IRQ_INFO_EVENT;
extern TraceEvent _TRACE_NVIC_COMPLETE_IRQ_EVENT;
extern TraceEvent _TRACE_NVIC_SET_IRQ_LEVEL_EVENT;
extern TraceEvent _TRACE_NVIC_SET_NMI_LEVEL_EVENT;
extern TraceEvent _TRACE_NVIC_SYSREG_READ_EVENT;
extern TraceEvent _TRACE_NVIC_SYSREG_WRITE_EVENT;
extern TraceEvent _TRACE_HEATHROW_WRITE_EVENT;
extern TraceEvent _TRACE_HEATHROW_READ_EVENT;
extern TraceEvent _TRACE_HEATHROW_SET_IRQ_EVENT;
extern TraceEvent _TRACE_BCM2835_IC_SET_GPU_IRQ_EVENT;
extern TraceEvent _TRACE_BCM2835_IC_SET_CPU_IRQ_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_CLAIM_IRQ_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_FREE_IRQ_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_SET_IRQ_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_GET_SOURCE_INFO_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_GET_QUEUE_INFO_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_ESB_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_SYNC_EVENT;
extern TraceEvent _TRACE_SPAPR_XIVE_RESET_EVENT;
extern TraceEvent _TRACE_KVM_XIVE_CPU_CONNECT_EVENT;
extern TraceEvent _TRACE_KVM_XIVE_SOURCE_RESET_EVENT;
extern TraceEvent _TRACE_XIVE_TCTX_ACCEPT_EVENT;
extern TraceEvent _TRACE_XIVE_TCTX_NOTIFY_EVENT;
extern TraceEvent _TRACE_XIVE_TCTX_SET_CPPR_EVENT;
extern TraceEvent _TRACE_XIVE_SOURCE_ESB_READ_EVENT;
extern TraceEvent _TRACE_XIVE_SOURCE_ESB_WRITE_EVENT;
extern TraceEvent _TRACE_XIVE_SOURCE_NOTIFY_EVENT;
extern TraceEvent _TRACE_XIVE_SOURCE_BLOCKED_EVENT;
extern TraceEvent _TRACE_XIVE_ROUTER_END_NOTIFY_EVENT;
extern TraceEvent _TRACE_XIVE_ROUTER_END_ESCALATE_EVENT;
extern TraceEvent _TRACE_XIVE_TCTX_TM_WRITE_EVENT;
extern TraceEvent _TRACE_XIVE_TCTX_TM_READ_EVENT;
extern TraceEvent _TRACE_XIVE_PRESENTER_NOTIFY_EVENT;
extern TraceEvent _TRACE_XIVE_END_SOURCE_READ_EVENT;
extern TraceEvent _TRACE_XIVE_NVP_BACKLOG_OP_EVENT;
extern TraceEvent _TRACE_XIVE_NVGC_BACKLOG_OP_EVENT;
extern TraceEvent _TRACE_XIVE_REDISTRIBUTE_EVENT;
extern TraceEvent _TRACE_XIVE_END_ENQUEUE_EVENT;
extern TraceEvent _TRACE_XIVE_ESCALATE_END_EVENT;
extern TraceEvent _TRACE_XIVE_ESCALATE_ESB_EVENT;
extern TraceEvent _TRACE_PNV_XIVE_IC_HW_TRIGGER_EVENT;
extern TraceEvent _TRACE_GOLDFISH_IRQ_REQUEST_EVENT;
extern TraceEvent _TRACE_GOLDFISH_PIC_READ_EVENT;
extern TraceEvent _TRACE_GOLDFISH_PIC_WRITE_EVENT;
extern TraceEvent _TRACE_GOLDFISH_PIC_RESET_EVENT;
extern TraceEvent _TRACE_GOLDFISH_PIC_REALIZE_EVENT;
extern TraceEvent _TRACE_GOLDFISH_PIC_INSTANCE_INIT_EVENT;
extern TraceEvent _TRACE_SH_INTC_SOURCES_EVENT;
extern TraceEvent _TRACE_SH_INTC_PENDING_EVENT;
extern TraceEvent _TRACE_SH_INTC_REGISTER_EVENT;
extern TraceEvent _TRACE_SH_INTC_READ_EVENT;
extern TraceEvent _TRACE_SH_INTC_WRITE_EVENT;
extern TraceEvent _TRACE_SH_INTC_SET_EVENT;
extern TraceEvent _TRACE_LOONGSON_IPI_READ_EVENT;
extern TraceEvent _TRACE_LOONGSON_IPI_WRITE_EVENT;
extern TraceEvent _TRACE_LOONGARCH_PCH_PIC_IRQ_HANDLER_EVENT;
extern TraceEvent _TRACE_LOONGARCH_PCH_PIC_READ_EVENT;
extern TraceEvent _TRACE_LOONGARCH_PCH_PIC_WRITE_EVENT;
extern TraceEvent _TRACE_LOONGARCH_MSI_SET_IRQ_EVENT;
extern TraceEvent _TRACE_LOONGARCH_EXTIOI_SETIRQ_EVENT;
extern TraceEvent _TRACE_LOONGARCH_EXTIOI_READW_EVENT;
extern TraceEvent _TRACE_LOONGARCH_EXTIOI_WRITEW_EVENT;
extern uint16_t _TRACE_PIC_UPDATE_IRQ_DSTATE;
extern uint16_t _TRACE_PIC_SET_IRQ_DSTATE;
extern uint16_t _TRACE_PIC_INTERRUPT_DSTATE;
extern uint16_t _TRACE_PIC_IOPORT_WRITE_DSTATE;
extern uint16_t _TRACE_PIC_IOPORT_READ_DSTATE;
extern uint16_t _TRACE_CPU_SET_APIC_BASE_DSTATE;
extern uint16_t _TRACE_CPU_GET_APIC_BASE_DSTATE;
extern uint16_t _TRACE_APIC_LOCAL_DELIVER_DSTATE;
extern uint16_t _TRACE_APIC_DELIVER_IRQ_DSTATE;
extern uint16_t _TRACE_APIC_REGISTER_READ_DSTATE;
extern uint16_t _TRACE_APIC_REGISTER_WRITE_DSTATE;
extern uint16_t _TRACE_IOAPIC_SET_REMOTE_IRR_DSTATE;
extern uint16_t _TRACE_IOAPIC_CLEAR_REMOTE_IRR_DSTATE;
extern uint16_t _TRACE_IOAPIC_EOI_BROADCAST_DSTATE;
extern uint16_t _TRACE_IOAPIC_EOI_DELAYED_REASSERT_DSTATE;
extern uint16_t _TRACE_IOAPIC_MEM_READ_DSTATE;
extern uint16_t _TRACE_IOAPIC_MEM_WRITE_DSTATE;
extern uint16_t _TRACE_IOAPIC_SET_IRQ_DSTATE;
extern uint16_t _TRACE_KVM_REPORT_IRQ_DELIVERED_DSTATE;
extern uint16_t _TRACE_KVM_RESET_IRQ_DELIVERED_DSTATE;
extern uint16_t _TRACE_KVM_GET_IRQ_DELIVERED_DSTATE;
extern uint16_t _TRACE_SLAVIO_INTCTL_MEM_READL_DSTATE;
extern uint16_t _TRACE_SLAVIO_INTCTL_MEM_WRITEL_DSTATE;
extern uint16_t _TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_DSTATE;
extern uint16_t _TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_DSTATE;
extern uint16_t _TRACE_SLAVIO_INTCTLM_MEM_READL_DSTATE;
extern uint16_t _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DSTATE;
extern uint16_t _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_DSTATE;
extern uint16_t _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_DSTATE;
extern uint16_t _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_DSTATE;
extern uint16_t _TRACE_SLAVIO_CHECK_INTERRUPTS_DSTATE;
extern uint16_t _TRACE_SLAVIO_SET_IRQ_DSTATE;
extern uint16_t _TRACE_SLAVIO_SET_TIMER_IRQ_CPU_DSTATE;
extern uint16_t _TRACE_GRLIB_IRQMP_CHECK_IRQS_DSTATE;
extern uint16_t _TRACE_GRLIB_IRQMP_ACK_DSTATE;
extern uint16_t _TRACE_GRLIB_IRQMP_SET_IRQ_DSTATE;
extern uint16_t _TRACE_GRLIB_IRQMP_READL_UNKNOWN_DSTATE;
extern uint16_t _TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_DSTATE;
extern uint16_t _TRACE_XICS_ICP_CHECK_IPI_DSTATE;
extern uint16_t _TRACE_XICS_ICP_ACCEPT_DSTATE;
extern uint16_t _TRACE_XICS_ICP_EOI_DSTATE;
extern uint16_t _TRACE_XICS_ICP_IRQ_DSTATE;
extern uint16_t _TRACE_XICS_ICP_RAISE_DSTATE;
extern uint16_t _TRACE_XICS_ICS_SET_IRQ_MSI_DSTATE;
extern uint16_t _TRACE_XICS_MASKED_PENDING_DSTATE;
extern uint16_t _TRACE_XICS_ICS_SET_IRQ_LSI_DSTATE;
extern uint16_t _TRACE_XICS_ICS_WRITE_XIVE_DSTATE;
extern uint16_t _TRACE_XICS_ICS_REJECT_DSTATE;
extern uint16_t _TRACE_XICS_ICS_EOI_DSTATE;
extern uint16_t _TRACE_FLIC_CREATE_DEVICE_DSTATE;
extern uint16_t _TRACE_FLIC_RESET_FAILED_DSTATE;
extern uint16_t _TRACE_QEMU_S390_AIRQ_SUPPRESSED_DSTATE;
extern uint16_t _TRACE_QEMU_S390_SUPPRESS_AIRQ_DSTATE;
extern uint16_t _TRACE_ASPEED_VIC_SET_IRQ_DSTATE;
extern uint16_t _TRACE_ASPEED_VIC_UPDATE_FIQ_DSTATE;
extern uint16_t _TRACE_ASPEED_VIC_UPDATE_IRQ_DSTATE;
extern uint16_t _TRACE_ASPEED_VIC_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_VIC_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_SET_IRQ_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_CLEAR_IRQ_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_UPDATE_IRQ_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_PENDING_IRQ_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_TRIGGER_IRQ_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_ALL_ISR_DONE_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_ENABLE_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_SELECT_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_MASK_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_UNMASK_DSTATE;
extern uint16_t _TRACE_ASPEED_INTC_ALL_ISR_DONE_BIT_DSTATE;
extern uint16_t _TRACE_GIC_ENABLE_IRQ_DSTATE;
extern uint16_t _TRACE_GIC_DISABLE_IRQ_DSTATE;
extern uint16_t _TRACE_GIC_SET_IRQ_DSTATE;
extern uint16_t _TRACE_GIC_UPDATE_BESTIRQ_DSTATE;
extern uint16_t _TRACE_GIC_UPDATE_SET_IRQ_DSTATE;
extern uint16_t _TRACE_GIC_ACKNOWLEDGE_IRQ_DSTATE;
extern uint16_t _TRACE_GIC_CPU_WRITE_DSTATE;
extern uint16_t _TRACE_GIC_CPU_READ_DSTATE;
extern uint16_t _TRACE_GIC_HYP_READ_DSTATE;
extern uint16_t _TRACE_GIC_HYP_WRITE_DSTATE;
extern uint16_t _TRACE_GIC_DIST_READ_DSTATE;
extern uint16_t _TRACE_GIC_DIST_WRITE_DSTATE;
extern uint16_t _TRACE_GIC_LR_ENTRY_DSTATE;
extern uint16_t _TRACE_GIC_UPDATE_MAINTENANCE_IRQ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_PMR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_PMR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_BPR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_BPR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_AP_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_AP_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_IGRPEN_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_IGRPEN_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_IGRPEN1_EL3_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_CTLR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_CTLR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_CTLR_EL3_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_CTLR_EL3_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_CPUIF_UPDATE_DSTATE;
extern uint16_t _TRACE_GICV3_CPUIF_SET_IRQS_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_GENERATE_SGI_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_IAR0_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_IAR1_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_NMIAR1_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_EOIR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_HPPIR0_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_HPPIR1_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_DIR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICC_RPR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_AP_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_AP_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_HCR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_HCR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_VMCR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_VMCR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_LR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_LR32_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_LRC_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_LR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_LR32_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_LRC_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_VTR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_MISR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_EISR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICH_ELRSR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_AP_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_AP_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_BPR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_BPR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_PMR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_PMR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_IGRPEN_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_IGRPEN_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_CTLR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_CTLR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_RPR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_HPPIR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_DIR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_IAR_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_NMIAR1_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ICV_EOIR_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_CPUIF_VIRT_UPDATE_DSTATE;
extern uint16_t _TRACE_GICV3_CPUIF_VIRT_SET_IRQS_DSTATE;
extern uint16_t _TRACE_GICV3_CPUIF_VIRT_SET_MAINT_IRQ_DSTATE;
extern uint16_t _TRACE_GICV3_DIST_READ_DSTATE;
extern uint16_t _TRACE_GICV3_DIST_BADREAD_DSTATE;
extern uint16_t _TRACE_GICV3_DIST_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_DIST_BADWRITE_DSTATE;
extern uint16_t _TRACE_GICV3_DIST_SET_IRQ_DSTATE;
extern uint16_t _TRACE_GICV3_REDIST_READ_DSTATE;
extern uint16_t _TRACE_GICV3_REDIST_BADREAD_DSTATE;
extern uint16_t _TRACE_GICV3_REDIST_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_REDIST_BADWRITE_DSTATE;
extern uint16_t _TRACE_GICV3_REDIST_SET_IRQ_DSTATE;
extern uint16_t _TRACE_GICV3_REDIST_SEND_SGI_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_BADREAD_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_BADWRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_TRANSLATION_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_PROCESS_COMMAND_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_INT_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_CLEAR_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_DISCARD_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_SYNC_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_MAPD_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_MAPC_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_MAPI_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_MAPTI_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_INV_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_INVALL_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_MOVALL_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_MOVI_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_VMAPI_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_VMAPTI_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_VMAPP_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_VMOVP_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_VSYNC_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_VMOVI_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_VINVALL_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CMD_UNKNOWN_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CTE_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CTE_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_CTE_READ_FAULT_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_ITE_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_ITE_READ_FAULT_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_ITE_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_DTE_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_DTE_WRITE_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_DTE_READ_FAULT_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_VTE_READ_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_VTE_READ_FAULT_DSTATE;
extern uint16_t _TRACE_GICV3_ITS_VTE_WRITE_DSTATE;
extern uint16_t _TRACE_NVIC_RECOMPUTE_STATE_DSTATE;
extern uint16_t _TRACE_NVIC_RECOMPUTE_STATE_SECURE_DSTATE;
extern uint16_t _TRACE_NVIC_SET_PRIO_DSTATE;
extern uint16_t _TRACE_NVIC_IRQ_UPDATE_DSTATE;
extern uint16_t _TRACE_NVIC_ESCALATE_PRIO_DSTATE;
extern uint16_t _TRACE_NVIC_ESCALATE_DISABLED_DSTATE;
extern uint16_t _TRACE_NVIC_SET_PENDING_DSTATE;
extern uint16_t _TRACE_NVIC_CLEAR_PENDING_DSTATE;
extern uint16_t _TRACE_NVIC_ACKNOWLEDGE_IRQ_DSTATE;
extern uint16_t _TRACE_NVIC_GET_PENDING_IRQ_INFO_DSTATE;
extern uint16_t _TRACE_NVIC_COMPLETE_IRQ_DSTATE;
extern uint16_t _TRACE_NVIC_SET_IRQ_LEVEL_DSTATE;
extern uint16_t _TRACE_NVIC_SET_NMI_LEVEL_DSTATE;
extern uint16_t _TRACE_NVIC_SYSREG_READ_DSTATE;
extern uint16_t _TRACE_NVIC_SYSREG_WRITE_DSTATE;
extern uint16_t _TRACE_HEATHROW_WRITE_DSTATE;
extern uint16_t _TRACE_HEATHROW_READ_DSTATE;
extern uint16_t _TRACE_HEATHROW_SET_IRQ_DSTATE;
extern uint16_t _TRACE_BCM2835_IC_SET_GPU_IRQ_DSTATE;
extern uint16_t _TRACE_BCM2835_IC_SET_CPU_IRQ_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_CLAIM_IRQ_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_FREE_IRQ_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_SET_IRQ_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_GET_SOURCE_INFO_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_GET_QUEUE_INFO_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_ESB_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_SYNC_DSTATE;
extern uint16_t _TRACE_SPAPR_XIVE_RESET_DSTATE;
extern uint16_t _TRACE_KVM_XIVE_CPU_CONNECT_DSTATE;
extern uint16_t _TRACE_KVM_XIVE_SOURCE_RESET_DSTATE;
extern uint16_t _TRACE_XIVE_TCTX_ACCEPT_DSTATE;
extern uint16_t _TRACE_XIVE_TCTX_NOTIFY_DSTATE;
extern uint16_t _TRACE_XIVE_TCTX_SET_CPPR_DSTATE;
extern uint16_t _TRACE_XIVE_SOURCE_ESB_READ_DSTATE;
extern uint16_t _TRACE_XIVE_SOURCE_ESB_WRITE_DSTATE;
extern uint16_t _TRACE_XIVE_SOURCE_NOTIFY_DSTATE;
extern uint16_t _TRACE_XIVE_SOURCE_BLOCKED_DSTATE;
extern uint16_t _TRACE_XIVE_ROUTER_END_NOTIFY_DSTATE;
extern uint16_t _TRACE_XIVE_ROUTER_END_ESCALATE_DSTATE;
extern uint16_t _TRACE_XIVE_TCTX_TM_WRITE_DSTATE;
extern uint16_t _TRACE_XIVE_TCTX_TM_READ_DSTATE;
extern uint16_t _TRACE_XIVE_PRESENTER_NOTIFY_DSTATE;
extern uint16_t _TRACE_XIVE_END_SOURCE_READ_DSTATE;
extern uint16_t _TRACE_XIVE_NVP_BACKLOG_OP_DSTATE;
extern uint16_t _TRACE_XIVE_NVGC_BACKLOG_OP_DSTATE;
extern uint16_t _TRACE_XIVE_REDISTRIBUTE_DSTATE;
extern uint16_t _TRACE_XIVE_END_ENQUEUE_DSTATE;
extern uint16_t _TRACE_XIVE_ESCALATE_END_DSTATE;
extern uint16_t _TRACE_XIVE_ESCALATE_ESB_DSTATE;
extern uint16_t _TRACE_PNV_XIVE_IC_HW_TRIGGER_DSTATE;
extern uint16_t _TRACE_GOLDFISH_IRQ_REQUEST_DSTATE;
extern uint16_t _TRACE_GOLDFISH_PIC_READ_DSTATE;
extern uint16_t _TRACE_GOLDFISH_PIC_WRITE_DSTATE;
extern uint16_t _TRACE_GOLDFISH_PIC_RESET_DSTATE;
extern uint16_t _TRACE_GOLDFISH_PIC_REALIZE_DSTATE;
extern uint16_t _TRACE_GOLDFISH_PIC_INSTANCE_INIT_DSTATE;
extern uint16_t _TRACE_SH_INTC_SOURCES_DSTATE;
extern uint16_t _TRACE_SH_INTC_PENDING_DSTATE;
extern uint16_t _TRACE_SH_INTC_REGISTER_DSTATE;
extern uint16_t _TRACE_SH_INTC_READ_DSTATE;
extern uint16_t _TRACE_SH_INTC_WRITE_DSTATE;
extern uint16_t _TRACE_SH_INTC_SET_DSTATE;
extern uint16_t _TRACE_LOONGSON_IPI_READ_DSTATE;
extern uint16_t _TRACE_LOONGSON_IPI_WRITE_DSTATE;
extern uint16_t _TRACE_LOONGARCH_PCH_PIC_IRQ_HANDLER_DSTATE;
extern uint16_t _TRACE_LOONGARCH_PCH_PIC_READ_DSTATE;
extern uint16_t _TRACE_LOONGARCH_PCH_PIC_WRITE_DSTATE;
extern uint16_t _TRACE_LOONGARCH_MSI_SET_IRQ_DSTATE;
extern uint16_t _TRACE_LOONGARCH_EXTIOI_SETIRQ_DSTATE;
extern uint16_t _TRACE_LOONGARCH_EXTIOI_READW_DSTATE;
extern uint16_t _TRACE_LOONGARCH_EXTIOI_WRITEW_DSTATE;
#define TRACE_PIC_UPDATE_IRQ_ENABLED 1
#define TRACE_PIC_SET_IRQ_ENABLED 1
#define TRACE_PIC_INTERRUPT_ENABLED 1
#define TRACE_PIC_IOPORT_WRITE_ENABLED 1
#define TRACE_PIC_IOPORT_READ_ENABLED 1
#define TRACE_CPU_SET_APIC_BASE_ENABLED 1
#define TRACE_CPU_GET_APIC_BASE_ENABLED 1
#define TRACE_APIC_LOCAL_DELIVER_ENABLED 1
#define TRACE_APIC_DELIVER_IRQ_ENABLED 1
#define TRACE_APIC_REGISTER_READ_ENABLED 1
#define TRACE_APIC_REGISTER_WRITE_ENABLED 1
#define TRACE_IOAPIC_SET_REMOTE_IRR_ENABLED 1
#define TRACE_IOAPIC_CLEAR_REMOTE_IRR_ENABLED 1
#define TRACE_IOAPIC_EOI_BROADCAST_ENABLED 1
#define TRACE_IOAPIC_EOI_DELAYED_REASSERT_ENABLED 1
#define TRACE_IOAPIC_MEM_READ_ENABLED 1
#define TRACE_IOAPIC_MEM_WRITE_ENABLED 1
#define TRACE_IOAPIC_SET_IRQ_ENABLED 1
#define TRACE_KVM_REPORT_IRQ_DELIVERED_ENABLED 1
#define TRACE_KVM_RESET_IRQ_DELIVERED_ENABLED 1
#define TRACE_KVM_GET_IRQ_DELIVERED_ENABLED 1
#define TRACE_SLAVIO_INTCTL_MEM_READL_ENABLED 1
#define TRACE_SLAVIO_INTCTL_MEM_WRITEL_ENABLED 1
#define TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_ENABLED 1
#define TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_ENABLED 1
#define TRACE_SLAVIO_INTCTLM_MEM_READL_ENABLED 1
#define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLED 1
#define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_ENABLED 1
#define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_ENABLED 1
#define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_ENABLED 1
#define TRACE_SLAVIO_CHECK_INTERRUPTS_ENABLED 1
#define TRACE_SLAVIO_SET_IRQ_ENABLED 1
#define TRACE_SLAVIO_SET_TIMER_IRQ_CPU_ENABLED 1
#define TRACE_GRLIB_IRQMP_CHECK_IRQS_ENABLED 1
#define TRACE_GRLIB_IRQMP_ACK_ENABLED 1
#define TRACE_GRLIB_IRQMP_SET_IRQ_ENABLED 1
#define TRACE_GRLIB_IRQMP_READL_UNKNOWN_ENABLED 1
#define TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_ENABLED 1
#define TRACE_XICS_ICP_CHECK_IPI_ENABLED 1
#define TRACE_XICS_ICP_ACCEPT_ENABLED 1
#define TRACE_XICS_ICP_EOI_ENABLED 1
#define TRACE_XICS_ICP_IRQ_ENABLED 1
#define TRACE_XICS_ICP_RAISE_ENABLED 1
#define TRACE_XICS_ICS_SET_IRQ_MSI_ENABLED 1
#define TRACE_XICS_MASKED_PENDING_ENABLED 1
#define TRACE_XICS_ICS_SET_IRQ_LSI_ENABLED 1
#define TRACE_XICS_ICS_WRITE_XIVE_ENABLED 1
#define TRACE_XICS_ICS_REJECT_ENABLED 1
#define TRACE_XICS_ICS_EOI_ENABLED 1
#define TRACE_FLIC_CREATE_DEVICE_ENABLED 1
#define TRACE_FLIC_RESET_FAILED_ENABLED 1
#define TRACE_QEMU_S390_AIRQ_SUPPRESSED_ENABLED 1
#define TRACE_QEMU_S390_SUPPRESS_AIRQ_ENABLED 1
#define TRACE_ASPEED_VIC_SET_IRQ_ENABLED 1
#define TRACE_ASPEED_VIC_UPDATE_FIQ_ENABLED 1
#define TRACE_ASPEED_VIC_UPDATE_IRQ_ENABLED 1
#define TRACE_ASPEED_VIC_READ_ENABLED 1
#define TRACE_ASPEED_VIC_WRITE_ENABLED 1
#define TRACE_ASPEED_INTC_READ_ENABLED 1
#define TRACE_ASPEED_INTC_WRITE_ENABLED 1
#define TRACE_ASPEED_INTC_SET_IRQ_ENABLED 1
#define TRACE_ASPEED_INTC_CLEAR_IRQ_ENABLED 1
#define TRACE_ASPEED_INTC_UPDATE_IRQ_ENABLED 1
#define TRACE_ASPEED_INTC_PENDING_IRQ_ENABLED 1
#define TRACE_ASPEED_INTC_TRIGGER_IRQ_ENABLED 1
#define TRACE_ASPEED_INTC_ALL_ISR_DONE_ENABLED 1
#define TRACE_ASPEED_INTC_ENABLE_ENABLED 1
#define TRACE_ASPEED_INTC_SELECT_ENABLED 1
#define TRACE_ASPEED_INTC_MASK_ENABLED 1
#define TRACE_ASPEED_INTC_UNMASK_ENABLED 1
#define TRACE_ASPEED_INTC_ALL_ISR_DONE_BIT_ENABLED 1
#define TRACE_GIC_ENABLE_IRQ_ENABLED 1
#define TRACE_GIC_DISABLE_IRQ_ENABLED 1
#define TRACE_GIC_SET_IRQ_ENABLED 1
#define TRACE_GIC_UPDATE_BESTIRQ_ENABLED 1
#define TRACE_GIC_UPDATE_SET_IRQ_ENABLED 1
#define TRACE_GIC_ACKNOWLEDGE_IRQ_ENABLED 1
#define TRACE_GIC_CPU_WRITE_ENABLED 1
#define TRACE_GIC_CPU_READ_ENABLED 1
#define TRACE_GIC_HYP_READ_ENABLED 1
#define TRACE_GIC_HYP_WRITE_ENABLED 1
#define TRACE_GIC_DIST_READ_ENABLED 1
#define TRACE_GIC_DIST_WRITE_ENABLED 1
#define TRACE_GIC_LR_ENTRY_ENABLED 1
#define TRACE_GIC_UPDATE_MAINTENANCE_IRQ_ENABLED 1
#define TRACE_GICV3_ICC_PMR_READ_ENABLED 1
#define TRACE_GICV3_ICC_PMR_WRITE_ENABLED 1
#define TRACE_GICV3_ICC_BPR_READ_ENABLED 1
#define TRACE_GICV3_ICC_BPR_WRITE_ENABLED 1
#define TRACE_GICV3_ICC_AP_READ_ENABLED 1
#define TRACE_GICV3_ICC_AP_WRITE_ENABLED 1
#define TRACE_GICV3_ICC_IGRPEN_READ_ENABLED 1
#define TRACE_GICV3_ICC_IGRPEN_WRITE_ENABLED 1
#define TRACE_GICV3_ICC_IGRPEN1_EL3_READ_ENABLED 1
#define TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_ENABLED 1
#define TRACE_GICV3_ICC_CTLR_READ_ENABLED 1
#define TRACE_GICV3_ICC_CTLR_WRITE_ENABLED 1
#define TRACE_GICV3_ICC_CTLR_EL3_READ_ENABLED 1
#define TRACE_GICV3_ICC_CTLR_EL3_WRITE_ENABLED 1
#define TRACE_GICV3_CPUIF_UPDATE_ENABLED 1
#define TRACE_GICV3_CPUIF_SET_IRQS_ENABLED 1
#define TRACE_GICV3_ICC_GENERATE_SGI_ENABLED 1
#define TRACE_GICV3_ICC_IAR0_READ_ENABLED 1
#define TRACE_GICV3_ICC_IAR1_READ_ENABLED 1
#define TRACE_GICV3_ICC_NMIAR1_READ_ENABLED 1
#define TRACE_GICV3_ICC_EOIR_WRITE_ENABLED 1
#define TRACE_GICV3_ICC_HPPIR0_READ_ENABLED 1
#define TRACE_GICV3_ICC_HPPIR1_READ_ENABLED 1
#define TRACE_GICV3_ICC_DIR_WRITE_ENABLED 1
#define TRACE_GICV3_ICC_RPR_READ_ENABLED 1
#define TRACE_GICV3_ICH_AP_READ_ENABLED 1
#define TRACE_GICV3_ICH_AP_WRITE_ENABLED 1
#define TRACE_GICV3_ICH_HCR_READ_ENABLED 1
#define TRACE_GICV3_ICH_HCR_WRITE_ENABLED 1
#define TRACE_GICV3_ICH_VMCR_READ_ENABLED 1
#define TRACE_GICV3_ICH_VMCR_WRITE_ENABLED 1
#define TRACE_GICV3_ICH_LR_READ_ENABLED 1
#define TRACE_GICV3_ICH_LR32_READ_ENABLED 1
#define TRACE_GICV3_ICH_LRC_READ_ENABLED 1
#define TRACE_GICV3_ICH_LR_WRITE_ENABLED 1
#define TRACE_GICV3_ICH_LR32_WRITE_ENABLED 1
#define TRACE_GICV3_ICH_LRC_WRITE_ENABLED 1
#define TRACE_GICV3_ICH_VTR_READ_ENABLED 1
#define TRACE_GICV3_ICH_MISR_READ_ENABLED 1
#define TRACE_GICV3_ICH_EISR_READ_ENABLED 1
#define TRACE_GICV3_ICH_ELRSR_READ_ENABLED 1
#define TRACE_GICV3_ICV_AP_READ_ENABLED 1
#define TRACE_GICV3_ICV_AP_WRITE_ENABLED 1
#define TRACE_GICV3_ICV_BPR_READ_ENABLED 1
#define TRACE_GICV3_ICV_BPR_WRITE_ENABLED 1
#define TRACE_GICV3_ICV_PMR_READ_ENABLED 1
#define TRACE_GICV3_ICV_PMR_WRITE_ENABLED 1
#define TRACE_GICV3_ICV_IGRPEN_READ_ENABLED 1
#define TRACE_GICV3_ICV_IGRPEN_WRITE_ENABLED 1
#define TRACE_GICV3_ICV_CTLR_READ_ENABLED 1
#define TRACE_GICV3_ICV_CTLR_WRITE_ENABLED 1
#define TRACE_GICV3_ICV_RPR_READ_ENABLED 1
#define TRACE_GICV3_ICV_HPPIR_READ_ENABLED 1
#define TRACE_GICV3_ICV_DIR_WRITE_ENABLED 1
#define TRACE_GICV3_ICV_IAR_READ_ENABLED 1
#define TRACE_GICV3_ICV_NMIAR1_READ_ENABLED 1
#define TRACE_GICV3_ICV_EOIR_WRITE_ENABLED 1
#define TRACE_GICV3_CPUIF_VIRT_UPDATE_ENABLED 1
#define TRACE_GICV3_CPUIF_VIRT_SET_IRQS_ENABLED 1
#define TRACE_GICV3_CPUIF_VIRT_SET_MAINT_IRQ_ENABLED 1
#define TRACE_GICV3_DIST_READ_ENABLED 1
#define TRACE_GICV3_DIST_BADREAD_ENABLED 1
#define TRACE_GICV3_DIST_WRITE_ENABLED 1
#define TRACE_GICV3_DIST_BADWRITE_ENABLED 1
#define TRACE_GICV3_DIST_SET_IRQ_ENABLED 1
#define TRACE_GICV3_REDIST_READ_ENABLED 1
#define TRACE_GICV3_REDIST_BADREAD_ENABLED 1
#define TRACE_GICV3_REDIST_WRITE_ENABLED 1
#define TRACE_GICV3_REDIST_BADWRITE_ENABLED 1
#define TRACE_GICV3_REDIST_SET_IRQ_ENABLED 1
#define TRACE_GICV3_REDIST_SEND_SGI_ENABLED 1
#define TRACE_GICV3_ITS_READ_ENABLED 1
#define TRACE_GICV3_ITS_BADREAD_ENABLED 1
#define TRACE_GICV3_ITS_WRITE_ENABLED 1
#define TRACE_GICV3_ITS_BADWRITE_ENABLED 1
#define TRACE_GICV3_ITS_TRANSLATION_WRITE_ENABLED 1
#define TRACE_GICV3_ITS_PROCESS_COMMAND_ENABLED 1
#define TRACE_GICV3_ITS_CMD_INT_ENABLED 1
#define TRACE_GICV3_ITS_CMD_CLEAR_ENABLED 1
#define TRACE_GICV3_ITS_CMD_DISCARD_ENABLED 1
#define TRACE_GICV3_ITS_CMD_SYNC_ENABLED 1
#define TRACE_GICV3_ITS_CMD_MAPD_ENABLED 1
#define TRACE_GICV3_ITS_CMD_MAPC_ENABLED 1
#define TRACE_GICV3_ITS_CMD_MAPI_ENABLED 1
#define TRACE_GICV3_ITS_CMD_MAPTI_ENABLED 1
#define TRACE_GICV3_ITS_CMD_INV_ENABLED 1
#define TRACE_GICV3_ITS_CMD_INVALL_ENABLED 1
#define TRACE_GICV3_ITS_CMD_MOVALL_ENABLED 1
#define TRACE_GICV3_ITS_CMD_MOVI_ENABLED 1
#define TRACE_GICV3_ITS_CMD_VMAPI_ENABLED 1
#define TRACE_GICV3_ITS_CMD_VMAPTI_ENABLED 1
#define TRACE_GICV3_ITS_CMD_VMAPP_ENABLED 1
#define TRACE_GICV3_ITS_CMD_VMOVP_ENABLED 1
#define TRACE_GICV3_ITS_CMD_VSYNC_ENABLED 1
#define TRACE_GICV3_ITS_CMD_VMOVI_ENABLED 1
#define TRACE_GICV3_ITS_CMD_VINVALL_ENABLED 1
#define TRACE_GICV3_ITS_CMD_UNKNOWN_ENABLED 1
#define TRACE_GICV3_ITS_CTE_READ_ENABLED 1
#define TRACE_GICV3_ITS_CTE_WRITE_ENABLED 1
#define TRACE_GICV3_ITS_CTE_READ_FAULT_ENABLED 1
#define TRACE_GICV3_ITS_ITE_READ_ENABLED 1
#define TRACE_GICV3_ITS_ITE_READ_FAULT_ENABLED 1
#define TRACE_GICV3_ITS_ITE_WRITE_ENABLED 1
#define TRACE_GICV3_ITS_DTE_READ_ENABLED 1
#define TRACE_GICV3_ITS_DTE_WRITE_ENABLED 1
#define TRACE_GICV3_ITS_DTE_READ_FAULT_ENABLED 1
#define TRACE_GICV3_ITS_VTE_READ_ENABLED 1
#define TRACE_GICV3_ITS_VTE_READ_FAULT_ENABLED 1
#define TRACE_GICV3_ITS_VTE_WRITE_ENABLED 1
#define TRACE_NVIC_RECOMPUTE_STATE_ENABLED 1
#define TRACE_NVIC_RECOMPUTE_STATE_SECURE_ENABLED 1
#define TRACE_NVIC_SET_PRIO_ENABLED 1
#define TRACE_NVIC_IRQ_UPDATE_ENABLED 1
#define TRACE_NVIC_ESCALATE_PRIO_ENABLED 1
#define TRACE_NVIC_ESCALATE_DISABLED_ENABLED 1
#define TRACE_NVIC_SET_PENDING_ENABLED 1
#define TRACE_NVIC_CLEAR_PENDING_ENABLED 1
#define TRACE_NVIC_ACKNOWLEDGE_IRQ_ENABLED 1
#define TRACE_NVIC_GET_PENDING_IRQ_INFO_ENABLED 1
#define TRACE_NVIC_COMPLETE_IRQ_ENABLED 1
#define TRACE_NVIC_SET_IRQ_LEVEL_ENABLED 1
#define TRACE_NVIC_SET_NMI_LEVEL_ENABLED 1
#define TRACE_NVIC_SYSREG_READ_ENABLED 1
#define TRACE_NVIC_SYSREG_WRITE_ENABLED 1
#define TRACE_HEATHROW_WRITE_ENABLED 1
#define TRACE_HEATHROW_READ_ENABLED 1
#define TRACE_HEATHROW_SET_IRQ_ENABLED 1
#define TRACE_BCM2835_IC_SET_GPU_IRQ_ENABLED 1
#define TRACE_BCM2835_IC_SET_CPU_IRQ_ENABLED 1
#define TRACE_SPAPR_XIVE_CLAIM_IRQ_ENABLED 1
#define TRACE_SPAPR_XIVE_FREE_IRQ_ENABLED 1
#define TRACE_SPAPR_XIVE_SET_IRQ_ENABLED 1
#define TRACE_SPAPR_XIVE_GET_SOURCE_INFO_ENABLED 1
#define TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_ENABLED 1
#define TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_ENABLED 1
#define TRACE_SPAPR_XIVE_GET_QUEUE_INFO_ENABLED 1
#define TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_ENABLED 1
#define TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_ENABLED 1
#define TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_ENABLED 1
#define TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_ENABLED 1
#define TRACE_SPAPR_XIVE_ESB_ENABLED 1
#define TRACE_SPAPR_XIVE_SYNC_ENABLED 1
#define TRACE_SPAPR_XIVE_RESET_ENABLED 1
#define TRACE_KVM_XIVE_CPU_CONNECT_ENABLED 1
#define TRACE_KVM_XIVE_SOURCE_RESET_ENABLED 1
#define TRACE_XIVE_TCTX_ACCEPT_ENABLED 1
#define TRACE_XIVE_TCTX_NOTIFY_ENABLED 1
#define TRACE_XIVE_TCTX_SET_CPPR_ENABLED 1
#define TRACE_XIVE_SOURCE_ESB_READ_ENABLED 1
#define TRACE_XIVE_SOURCE_ESB_WRITE_ENABLED 1
#define TRACE_XIVE_SOURCE_NOTIFY_ENABLED 1
#define TRACE_XIVE_SOURCE_BLOCKED_ENABLED 1
#define TRACE_XIVE_ROUTER_END_NOTIFY_ENABLED 1
#define TRACE_XIVE_ROUTER_END_ESCALATE_ENABLED 1
#define TRACE_XIVE_TCTX_TM_WRITE_ENABLED 1
#define TRACE_XIVE_TCTX_TM_READ_ENABLED 1
#define TRACE_XIVE_PRESENTER_NOTIFY_ENABLED 1
#define TRACE_XIVE_END_SOURCE_READ_ENABLED 1
#define TRACE_XIVE_NVP_BACKLOG_OP_ENABLED 1
#define TRACE_XIVE_NVGC_BACKLOG_OP_ENABLED 1
#define TRACE_XIVE_REDISTRIBUTE_ENABLED 1
#define TRACE_XIVE_END_ENQUEUE_ENABLED 1
#define TRACE_XIVE_ESCALATE_END_ENABLED 1
#define TRACE_XIVE_ESCALATE_ESB_ENABLED 1
#define TRACE_PNV_XIVE_IC_HW_TRIGGER_ENABLED 1
#define TRACE_GOLDFISH_IRQ_REQUEST_ENABLED 1
#define TRACE_GOLDFISH_PIC_READ_ENABLED 1
#define TRACE_GOLDFISH_PIC_WRITE_ENABLED 1
#define TRACE_GOLDFISH_PIC_RESET_ENABLED 1
#define TRACE_GOLDFISH_PIC_REALIZE_ENABLED 1
#define TRACE_GOLDFISH_PIC_INSTANCE_INIT_ENABLED 1
#define TRACE_SH_INTC_SOURCES_ENABLED 1
#define TRACE_SH_INTC_PENDING_ENABLED 1
#define TRACE_SH_INTC_REGISTER_ENABLED 1
#define TRACE_SH_INTC_READ_ENABLED 1
#define TRACE_SH_INTC_WRITE_ENABLED 1
#define TRACE_SH_INTC_SET_ENABLED 1
#define TRACE_LOONGSON_IPI_READ_ENABLED 1
#define TRACE_LOONGSON_IPI_WRITE_ENABLED 1
#define TRACE_LOONGARCH_PCH_PIC_IRQ_HANDLER_ENABLED 1
#define TRACE_LOONGARCH_PCH_PIC_READ_ENABLED 1
#define TRACE_LOONGARCH_PCH_PIC_WRITE_ENABLED 1
#define TRACE_LOONGARCH_MSI_SET_IRQ_ENABLED 1
#define TRACE_LOONGARCH_EXTIOI_SETIRQ_ENABLED 1
#define TRACE_LOONGARCH_EXTIOI_READW_ENABLED 1
#define TRACE_LOONGARCH_EXTIOI_WRITEW_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_PIC_UPDATE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PIC_UPDATE_IRQ) || \
    false)

static inline void trace_pic_update_irq(bool master, uint8_t imr, uint8_t irr, uint8_t padd)
{
    if (trace_event_get_state(TRACE_PIC_UPDATE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 4 "../xemu/hw/intc/trace-events"
            qemu_log("pic_update_irq " "master %d imr %"PRIu8" irr %"PRIu8" padd %"PRIu8 "\n", master, imr, irr, padd);
#line 836 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_PIC_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PIC_SET_IRQ) || \
    false)

static inline void trace_pic_set_irq(bool master, int irq, int level)
{
    if (trace_event_get_state(TRACE_PIC_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../xemu/hw/intc/trace-events"
            qemu_log("pic_set_irq " "master %d irq %d level %d" "\n", master, irq, level);
#line 851 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_PIC_INTERRUPT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PIC_INTERRUPT) || \
    false)

static inline void trace_pic_interrupt(int irq, int intno)
{
    if (trace_event_get_state(TRACE_PIC_INTERRUPT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 6 "../xemu/hw/intc/trace-events"
            qemu_log("pic_interrupt " "irq %d intno %d" "\n", irq, intno);
#line 866 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_PIC_IOPORT_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PIC_IOPORT_WRITE) || \
    false)

static inline void trace_pic_ioport_write(bool master, uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_PIC_IOPORT_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 7 "../xemu/hw/intc/trace-events"
            qemu_log("pic_ioport_write " "master %d addr 0x%"PRIx64" val 0x%"PRIx64 "\n", master, addr, val);
#line 881 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_PIC_IOPORT_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PIC_IOPORT_READ) || \
    false)

static inline void trace_pic_ioport_read(bool master, uint64_t addr, int val)
{
    if (trace_event_get_state(TRACE_PIC_IOPORT_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 8 "../xemu/hw/intc/trace-events"
            qemu_log("pic_ioport_read " "master %d addr 0x%"PRIx64" val 0x%x" "\n", master, addr, val);
#line 896 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_CPU_SET_APIC_BASE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CPU_SET_APIC_BASE) || \
    false)

static inline void trace_cpu_set_apic_base(uint64_t val)
{
    if (trace_event_get_state(TRACE_CPU_SET_APIC_BASE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 11 "../xemu/hw/intc/trace-events"
            qemu_log("cpu_set_apic_base " "0x%016"PRIx64 "\n", val);
#line 911 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_CPU_GET_APIC_BASE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CPU_GET_APIC_BASE) || \
    false)

static inline void trace_cpu_get_apic_base(uint64_t val)
{
    if (trace_event_get_state(TRACE_CPU_GET_APIC_BASE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 12 "../xemu/hw/intc/trace-events"
            qemu_log("cpu_get_apic_base " "0x%016"PRIx64 "\n", val);
#line 926 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_APIC_LOCAL_DELIVER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APIC_LOCAL_DELIVER) || \
    false)

static inline void trace_apic_local_deliver(int vector, uint32_t lvt)
{
    if (trace_event_get_state(TRACE_APIC_LOCAL_DELIVER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../xemu/hw/intc/trace-events"
            qemu_log("apic_local_deliver " "vector %d delivery mode %d" "\n", vector, lvt);
#line 941 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_APIC_DELIVER_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APIC_DELIVER_IRQ) || \
    false)

static inline void trace_apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode)
{
    if (trace_event_get_state(TRACE_APIC_DELIVER_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 16 "../xemu/hw/intc/trace-events"
            qemu_log("apic_deliver_irq " "dest %d dest_mode %d delivery_mode %d vector %d trigger_mode %d" "\n", dest, dest_mode, delivery_mode, vector_num, trigger_mode);
#line 956 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_APIC_REGISTER_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APIC_REGISTER_READ) || \
    false)

static inline void trace_apic_register_read(uint8_t reg, uint64_t val)
{
    if (trace_event_get_state(TRACE_APIC_REGISTER_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 17 "../xemu/hw/intc/trace-events"
            qemu_log("apic_register_read " "register 0x%02x = 0x%"PRIx64 "\n", reg, val);
#line 971 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_APIC_REGISTER_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APIC_REGISTER_WRITE) || \
    false)

static inline void trace_apic_register_write(uint8_t reg, uint64_t val)
{
    if (trace_event_get_state(TRACE_APIC_REGISTER_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 18 "../xemu/hw/intc/trace-events"
            qemu_log("apic_register_write " "register 0x%02x = 0x%"PRIx64 "\n", reg, val);
#line 986 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_IOAPIC_SET_REMOTE_IRR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_SET_REMOTE_IRR) || \
    false)

static inline void trace_ioapic_set_remote_irr(int n)
{
    if (trace_event_get_state(TRACE_IOAPIC_SET_REMOTE_IRR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 21 "../xemu/hw/intc/trace-events"
            qemu_log("ioapic_set_remote_irr " "set remote irr for pin %d" "\n", n);
#line 1001 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_IOAPIC_CLEAR_REMOTE_IRR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_CLEAR_REMOTE_IRR) || \
    false)

static inline void trace_ioapic_clear_remote_irr(int n, int vector)
{
    if (trace_event_get_state(TRACE_IOAPIC_CLEAR_REMOTE_IRR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 22 "../xemu/hw/intc/trace-events"
            qemu_log("ioapic_clear_remote_irr " "clear remote irr for pin %d vector %d" "\n", n, vector);
#line 1016 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_IOAPIC_EOI_BROADCAST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_EOI_BROADCAST) || \
    false)

static inline void trace_ioapic_eoi_broadcast(int vector)
{
    if (trace_event_get_state(TRACE_IOAPIC_EOI_BROADCAST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 23 "../xemu/hw/intc/trace-events"
            qemu_log("ioapic_eoi_broadcast " "EOI broadcast for vector %d" "\n", vector);
#line 1031 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_IOAPIC_EOI_DELAYED_REASSERT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_EOI_DELAYED_REASSERT) || \
    false)

static inline void trace_ioapic_eoi_delayed_reassert(int vector)
{
    if (trace_event_get_state(TRACE_IOAPIC_EOI_DELAYED_REASSERT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 24 "../xemu/hw/intc/trace-events"
            qemu_log("ioapic_eoi_delayed_reassert " "delayed reassert on EOI broadcast for vector %d" "\n", vector);
#line 1046 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_IOAPIC_MEM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_MEM_READ) || \
    false)

static inline void trace_ioapic_mem_read(uint8_t addr, uint8_t regsel, uint8_t size, uint32_t val)
{
    if (trace_event_get_state(TRACE_IOAPIC_MEM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 25 "../xemu/hw/intc/trace-events"
            qemu_log("ioapic_mem_read " "ioapic mem read addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" retval 0x%"PRIx32 "\n", addr, regsel, size, val);
#line 1061 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_IOAPIC_MEM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_MEM_WRITE) || \
    false)

static inline void trace_ioapic_mem_write(uint8_t addr, uint8_t regsel, uint8_t size, uint32_t val)
{
    if (trace_event_get_state(TRACE_IOAPIC_MEM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 26 "../xemu/hw/intc/trace-events"
            qemu_log("ioapic_mem_write " "ioapic mem write addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" val 0x%"PRIx32 "\n", addr, regsel, size, val);
#line 1076 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_IOAPIC_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_SET_IRQ) || \
    false)

static inline void trace_ioapic_set_irq(int vector, int level)
{
    if (trace_event_get_state(TRACE_IOAPIC_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 27 "../xemu/hw/intc/trace-events"
            qemu_log("ioapic_set_irq " "vector: %d level: %d" "\n", vector, level);
#line 1091 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_KVM_REPORT_IRQ_DELIVERED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_KVM_REPORT_IRQ_DELIVERED) || \
    false)

static inline void trace_kvm_report_irq_delivered(int irq_delivered)
{
    if (trace_event_get_state(TRACE_KVM_REPORT_IRQ_DELIVERED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 30 "../xemu/hw/intc/trace-events"
            qemu_log("kvm_report_irq_delivered " "coalescing %d" "\n", irq_delivered);
#line 1106 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_KVM_RESET_IRQ_DELIVERED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_KVM_RESET_IRQ_DELIVERED) || \
    false)

static inline void trace_kvm_reset_irq_delivered(int irq_delivered)
{
    if (trace_event_get_state(TRACE_KVM_RESET_IRQ_DELIVERED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 31 "../xemu/hw/intc/trace-events"
            qemu_log("kvm_reset_irq_delivered " "old coalescing %d" "\n", irq_delivered);
#line 1121 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_KVM_GET_IRQ_DELIVERED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_KVM_GET_IRQ_DELIVERED) || \
    false)

static inline void trace_kvm_get_irq_delivered(int irq_delivered)
{
    if (trace_event_get_state(TRACE_KVM_GET_IRQ_DELIVERED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 32 "../xemu/hw/intc/trace-events"
            qemu_log("kvm_get_irq_delivered " "returning coalescing %d" "\n", irq_delivered);
#line 1136 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SLAVIO_INTCTL_MEM_READL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTL_MEM_READL) || \
    false)

static inline void trace_slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret)
{
    if (trace_event_get_state(TRACE_SLAVIO_INTCTL_MEM_READL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 35 "../xemu/hw/intc/trace-events"
            qemu_log("slavio_intctl_mem_readl " "read cpu %d reg 0x%"PRIx64" = 0x%x" "\n", cpu, addr, ret);
#line 1151 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SLAVIO_INTCTL_MEM_WRITEL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTL_MEM_WRITEL) || \
    false)

static inline void trace_slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_SLAVIO_INTCTL_MEM_WRITEL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 36 "../xemu/hw/intc/trace-events"
            qemu_log("slavio_intctl_mem_writel " "write cpu %d reg 0x%"PRIx64" = 0x%x" "\n", cpu, addr, val);
#line 1166 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR) || \
    false)

static inline void trace_slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending)
{
    if (trace_event_get_state(TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 37 "../xemu/hw/intc/trace-events"
            qemu_log("slavio_intctl_mem_writel_clear " "Cleared cpu %d irq mask 0x%x, curmask 0x%x" "\n", cpu, val, intreg_pending);
#line 1181 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET) || \
    false)

static inline void trace_slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending)
{
    if (trace_event_get_state(TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 38 "../xemu/hw/intc/trace-events"
            qemu_log("slavio_intctl_mem_writel_set " "Set cpu %d irq mask 0x%x, curmask 0x%x" "\n", cpu, val, intreg_pending);
#line 1196 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SLAVIO_INTCTLM_MEM_READL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTLM_MEM_READL) || \
    false)

static inline void trace_slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret)
{
    if (trace_event_get_state(TRACE_SLAVIO_INTCTLM_MEM_READL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 39 "../xemu/hw/intc/trace-events"
            qemu_log("slavio_intctlm_mem_readl " "read system reg 0x%"PRIx64" = 0x%x" "\n", addr, ret);
#line 1211 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTLM_MEM_WRITEL) || \
    false)

static inline void trace_slavio_intctlm_mem_writel(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_SLAVIO_INTCTLM_MEM_WRITEL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 40 "../xemu/hw/intc/trace-events"
            qemu_log("slavio_intctlm_mem_writel " "write system reg 0x%"PRIx64" = 0x%x" "\n", addr, val);
#line 1226 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE) || \
    false)

static inline void trace_slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled)
{
    if (trace_event_get_state(TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 41 "../xemu/hw/intc/trace-events"
            qemu_log("slavio_intctlm_mem_writel_enable " "Enabled master irq mask 0x%x, curmask 0x%x" "\n", val, intregm_disabled);
#line 1241 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE) || \
    false)

static inline void trace_slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled)
{
    if (trace_event_get_state(TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 42 "../xemu/hw/intc/trace-events"
            qemu_log("slavio_intctlm_mem_writel_disable " "Disabled master irq mask 0x%x, curmask 0x%x" "\n", val, intregm_disabled);
#line 1256 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET) || \
    false)

static inline void trace_slavio_intctlm_mem_writel_target(uint32_t cpu)
{
    if (trace_event_get_state(TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 43 "../xemu/hw/intc/trace-events"
            qemu_log("slavio_intctlm_mem_writel_target " "Set master irq cpu %d" "\n", cpu);
#line 1271 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SLAVIO_CHECK_INTERRUPTS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_CHECK_INTERRUPTS) || \
    false)

static inline void trace_slavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled)
{
    if (trace_event_get_state(TRACE_SLAVIO_CHECK_INTERRUPTS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 44 "../xemu/hw/intc/trace-events"
            qemu_log("slavio_check_interrupts " "pending 0x%x disabled 0x%x" "\n", pending, intregm_disabled);
#line 1286 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SLAVIO_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_SET_IRQ) || \
    false)

static inline void trace_slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level)
{
    if (trace_event_get_state(TRACE_SLAVIO_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 45 "../xemu/hw/intc/trace-events"
            qemu_log("slavio_set_irq " "Set cpu %d irq %d -> pil %d level %d" "\n", target_cpu, irq, pil, level);
#line 1301 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SLAVIO_SET_TIMER_IRQ_CPU_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_SET_TIMER_IRQ_CPU) || \
    false)

static inline void trace_slavio_set_timer_irq_cpu(int cpu, int level)
{
    if (trace_event_get_state(TRACE_SLAVIO_SET_TIMER_IRQ_CPU)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 46 "../xemu/hw/intc/trace-events"
            qemu_log("slavio_set_timer_irq_cpu " "Set cpu %d local timer level %d" "\n", cpu, level);
#line 1316 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GRLIB_IRQMP_CHECK_IRQS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_IRQMP_CHECK_IRQS) || \
    false)

static inline void trace_grlib_irqmp_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uint32_t lvl1, uint32_t lvl2)
{
    if (trace_event_get_state(TRACE_GRLIB_IRQMP_CHECK_IRQS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 49 "../xemu/hw/intc/trace-events"
            qemu_log("grlib_irqmp_check_irqs " "pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x" "\n", pend, force, mask, lvl1, lvl2);
#line 1331 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GRLIB_IRQMP_ACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_IRQMP_ACK) || \
    false)

static inline void trace_grlib_irqmp_ack(int intno)
{
    if (trace_event_get_state(TRACE_GRLIB_IRQMP_ACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 50 "../xemu/hw/intc/trace-events"
            qemu_log("grlib_irqmp_ack " "interrupt:%d" "\n", intno);
#line 1346 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GRLIB_IRQMP_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_IRQMP_SET_IRQ) || \
    false)

static inline void trace_grlib_irqmp_set_irq(int irq)
{
    if (trace_event_get_state(TRACE_GRLIB_IRQMP_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 51 "../xemu/hw/intc/trace-events"
            qemu_log("grlib_irqmp_set_irq " "Raise CPU IRQ %d" "\n", irq);
#line 1361 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GRLIB_IRQMP_READL_UNKNOWN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_IRQMP_READL_UNKNOWN) || \
    false)

static inline void trace_grlib_irqmp_readl_unknown(uint64_t addr)
{
    if (trace_event_get_state(TRACE_GRLIB_IRQMP_READL_UNKNOWN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 52 "../xemu/hw/intc/trace-events"
            qemu_log("grlib_irqmp_readl_unknown " "addr 0x%"PRIx64 "\n", addr);
#line 1376 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN) || \
    false)

static inline void trace_grlib_irqmp_writel_unknown(uint64_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 53 "../xemu/hw/intc/trace-events"
            qemu_log("grlib_irqmp_writel_unknown " "addr 0x%"PRIx64" value 0x%x" "\n", addr, value);
#line 1391 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XICS_ICP_CHECK_IPI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XICS_ICP_CHECK_IPI) || \
    false)

static inline void trace_xics_icp_check_ipi(int server, uint8_t mfrr)
{
    if (trace_event_get_state(TRACE_XICS_ICP_CHECK_IPI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 56 "../xemu/hw/intc/trace-events"
            qemu_log("xics_icp_check_ipi " "CPU %d can take IPI mfrr=0x%x" "\n", server, mfrr);
#line 1406 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XICS_ICP_ACCEPT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XICS_ICP_ACCEPT) || \
    false)

static inline void trace_xics_icp_accept(uint32_t old_xirr, uint32_t new_xirr)
{
    if (trace_event_get_state(TRACE_XICS_ICP_ACCEPT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 57 "../xemu/hw/intc/trace-events"
            qemu_log("xics_icp_accept " "icp_accept: XIRR 0x%"PRIx32"->0x%"PRIx32 "\n", old_xirr, new_xirr);
#line 1421 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XICS_ICP_EOI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XICS_ICP_EOI) || \
    false)

static inline void trace_xics_icp_eoi(int server, uint32_t xirr, uint32_t new_xirr)
{
    if (trace_event_get_state(TRACE_XICS_ICP_EOI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 58 "../xemu/hw/intc/trace-events"
            qemu_log("xics_icp_eoi " "icp_eoi: server %d given XIRR 0x%"PRIx32" new XIRR 0x%"PRIx32 "\n", server, xirr, new_xirr);
#line 1436 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XICS_ICP_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XICS_ICP_IRQ) || \
    false)

static inline void trace_xics_icp_irq(int server, int nr, uint8_t priority)
{
    if (trace_event_get_state(TRACE_XICS_ICP_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 59 "../xemu/hw/intc/trace-events"
            qemu_log("xics_icp_irq " "cpu %d trying to deliver irq 0x%"PRIx32" priority 0x%x" "\n", server, nr, priority);
#line 1451 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XICS_ICP_RAISE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XICS_ICP_RAISE) || \
    false)

static inline void trace_xics_icp_raise(uint32_t xirr, uint8_t pending_priority)
{
    if (trace_event_get_state(TRACE_XICS_ICP_RAISE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 60 "../xemu/hw/intc/trace-events"
            qemu_log("xics_icp_raise " "raising IRQ new XIRR=0x%x new pending priority=0x%x" "\n", xirr, pending_priority);
#line 1466 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XICS_ICS_SET_IRQ_MSI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XICS_ICS_SET_IRQ_MSI) || \
    false)

static inline void trace_xics_ics_set_irq_msi(int srcno, int nr)
{
    if (trace_event_get_state(TRACE_XICS_ICS_SET_IRQ_MSI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 61 "../xemu/hw/intc/trace-events"
            qemu_log("xics_ics_set_irq_msi " "set_irq_msi: srcno %d [irq 0x%x]" "\n", srcno, nr);
#line 1481 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XICS_MASKED_PENDING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XICS_MASKED_PENDING) || \
    false)

static inline void trace_xics_masked_pending(void)
{
    if (trace_event_get_state(TRACE_XICS_MASKED_PENDING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 62 "../xemu/hw/intc/trace-events"
            qemu_log("xics_masked_pending " "set_irq_msi: masked pending" "\n");
#line 1496 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XICS_ICS_SET_IRQ_LSI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XICS_ICS_SET_IRQ_LSI) || \
    false)

static inline void trace_xics_ics_set_irq_lsi(int srcno, int nr)
{
    if (trace_event_get_state(TRACE_XICS_ICS_SET_IRQ_LSI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 63 "../xemu/hw/intc/trace-events"
            qemu_log("xics_ics_set_irq_lsi " "set_irq_lsi: srcno %d [irq 0x%x]" "\n", srcno, nr);
#line 1511 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XICS_ICS_WRITE_XIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XICS_ICS_WRITE_XIVE) || \
    false)

static inline void trace_xics_ics_write_xive(int nr, int srcno, int server, uint8_t priority)
{
    if (trace_event_get_state(TRACE_XICS_ICS_WRITE_XIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 64 "../xemu/hw/intc/trace-events"
            qemu_log("xics_ics_write_xive " "ics_write_xive: irq 0x%x [src %d] server 0x%x prio 0x%x" "\n", nr, srcno, server, priority);
#line 1526 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XICS_ICS_REJECT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XICS_ICS_REJECT) || \
    false)

static inline void trace_xics_ics_reject(int nr, int srcno)
{
    if (trace_event_get_state(TRACE_XICS_ICS_REJECT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 65 "../xemu/hw/intc/trace-events"
            qemu_log("xics_ics_reject " "reject irq 0x%x [src %d]" "\n", nr, srcno);
#line 1541 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XICS_ICS_EOI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XICS_ICS_EOI) || \
    false)

static inline void trace_xics_ics_eoi(int nr)
{
    if (trace_event_get_state(TRACE_XICS_ICS_EOI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 66 "../xemu/hw/intc/trace-events"
            qemu_log("xics_ics_eoi " "ics_eoi: irq 0x%x" "\n", nr);
#line 1556 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_FLIC_CREATE_DEVICE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_FLIC_CREATE_DEVICE) || \
    false)

static inline void trace_flic_create_device(int err)
{
    if (trace_event_get_state(TRACE_FLIC_CREATE_DEVICE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 69 "../xemu/hw/intc/trace-events"
            qemu_log("flic_create_device " "flic: create device failed %d" "\n", err);
#line 1571 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_FLIC_RESET_FAILED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_FLIC_RESET_FAILED) || \
    false)

static inline void trace_flic_reset_failed(int err)
{
    if (trace_event_get_state(TRACE_FLIC_RESET_FAILED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 70 "../xemu/hw/intc/trace-events"
            qemu_log("flic_reset_failed " "flic: reset failed %d" "\n", err);
#line 1586 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_QEMU_S390_AIRQ_SUPPRESSED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QEMU_S390_AIRQ_SUPPRESSED) || \
    false)

static inline void trace_qemu_s390_airq_suppressed(uint8_t type, uint8_t isc)
{
    if (trace_event_get_state(TRACE_QEMU_S390_AIRQ_SUPPRESSED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 73 "../xemu/hw/intc/trace-events"
            qemu_log("qemu_s390_airq_suppressed " "flic: adapter I/O interrupt suppressed (type 0x%x isc 0x%x)" "\n", type, isc);
#line 1601 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_QEMU_S390_SUPPRESS_AIRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QEMU_S390_SUPPRESS_AIRQ) || \
    false)

static inline void trace_qemu_s390_suppress_airq(uint8_t isc, const char *from, const char *to)
{
    if (trace_event_get_state(TRACE_QEMU_S390_SUPPRESS_AIRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 74 "../xemu/hw/intc/trace-events"
            qemu_log("qemu_s390_suppress_airq " "flic: for isc 0x%x, suppress airq by modifying ais mode from %s to %s" "\n", isc, from, to);
#line 1616 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_VIC_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_VIC_SET_IRQ) || \
    false)

static inline void trace_aspeed_vic_set_irq(int irq, int level)
{
    if (trace_event_get_state(TRACE_ASPEED_VIC_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 77 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_vic_set_irq " "Enabling IRQ %d: %d" "\n", irq, level);
#line 1631 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_VIC_UPDATE_FIQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_VIC_UPDATE_FIQ) || \
    false)

static inline void trace_aspeed_vic_update_fiq(int flags)
{
    if (trace_event_get_state(TRACE_ASPEED_VIC_UPDATE_FIQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 78 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_vic_update_fiq " "Raising FIQ: %d" "\n", flags);
#line 1646 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_VIC_UPDATE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_VIC_UPDATE_IRQ) || \
    false)

static inline void trace_aspeed_vic_update_irq(int flags)
{
    if (trace_event_get_state(TRACE_ASPEED_VIC_UPDATE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 79 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_vic_update_irq " "Raising IRQ: %d" "\n", flags);
#line 1661 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_VIC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_VIC_READ) || \
    false)

static inline void trace_aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_VIC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 80 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_vic_read " "From 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, value);
#line 1676 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_VIC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_VIC_WRITE) || \
    false)

static inline void trace_aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_VIC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 81 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_vic_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data);
#line 1691 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_READ) || \
    false)

static inline void trace_aspeed_intc_read(const char *s, uint64_t offset, unsigned size, uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 83 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_read " "%s: From 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", s, offset, size, value);
#line 1706 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_WRITE) || \
    false)

static inline void trace_aspeed_intc_write(const char *s, uint64_t offset, unsigned size, uint32_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 84 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_write " "%s: To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", s, offset, size, data);
#line 1721 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_SET_IRQ) || \
    false)

static inline void trace_aspeed_intc_set_irq(const char *s, int inpin_idx, int level)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 85 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_set_irq " "%s: Set IRQ %d: %d" "\n", s, inpin_idx, level);
#line 1736 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_CLEAR_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_CLEAR_IRQ) || \
    false)

static inline void trace_aspeed_intc_clear_irq(const char *s, int inpin_idx, int outpin_idx, int level)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_CLEAR_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 86 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_clear_irq " "%s: Clear IRQ %d-%d: %d" "\n", s, inpin_idx, outpin_idx, level);
#line 1751 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_UPDATE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_UPDATE_IRQ) || \
    false)

static inline void trace_aspeed_intc_update_irq(const char *s, int inpin_idx, int outpin_idx, int level)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_UPDATE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 87 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_update_irq " "%s: Update IRQ: %d-%d: %d" "\n", s, inpin_idx, outpin_idx, level);
#line 1766 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_PENDING_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_PENDING_IRQ) || \
    false)

static inline void trace_aspeed_intc_pending_irq(const char *s, int inpin_idx, uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_PENDING_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 88 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_pending_irq " "%s: Pending IRQ: %d: 0x%x" "\n", s, inpin_idx, value);
#line 1781 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_TRIGGER_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_TRIGGER_IRQ) || \
    false)

static inline void trace_aspeed_intc_trigger_irq(const char *s, int inpin_idx, int outpin_idx, uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_TRIGGER_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 89 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_trigger_irq " "%s: Trigger IRQ: %d-%d: 0x%x" "\n", s, inpin_idx, outpin_idx, value);
#line 1796 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_ALL_ISR_DONE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_ALL_ISR_DONE) || \
    false)

static inline void trace_aspeed_intc_all_isr_done(const char *s, int inpin_idx)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_ALL_ISR_DONE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 90 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_all_isr_done " "%s: All source ISR execution are done: %d" "\n", s, inpin_idx);
#line 1811 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_ENABLE) || \
    false)

static inline void trace_aspeed_intc_enable(const char *s, uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_ENABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 91 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_enable " "%s: Enable: 0x%x" "\n", s, value);
#line 1826 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_SELECT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_SELECT) || \
    false)

static inline void trace_aspeed_intc_select(const char *s, uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_SELECT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 92 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_select " "%s: Select: 0x%x" "\n", s, value);
#line 1841 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_MASK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_MASK) || \
    false)

static inline void trace_aspeed_intc_mask(const char *s, uint32_t change, uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_MASK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 93 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_mask " "%s: Mask: 0x%x: 0x%x" "\n", s, change, value);
#line 1856 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_UNMASK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_UNMASK) || \
    false)

static inline void trace_aspeed_intc_unmask(const char *s, uint32_t change, uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_UNMASK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 94 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_unmask " "%s: UnMask: 0x%x: 0x%x" "\n", s, change, value);
#line 1871 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_ASPEED_INTC_ALL_ISR_DONE_BIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_ALL_ISR_DONE_BIT) || \
    false)

static inline void trace_aspeed_intc_all_isr_done_bit(const char *s, int inpin_idx, int bit)
{
    if (trace_event_get_state(TRACE_ASPEED_INTC_ALL_ISR_DONE_BIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 95 "../xemu/hw/intc/trace-events"
            qemu_log("aspeed_intc_all_isr_done_bit " "%s: All source ISR execution are done from specific bit: %d-%d" "\n", s, inpin_idx, bit);
#line 1886 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_ENABLE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_ENABLE_IRQ) || \
    false)

static inline void trace_gic_enable_irq(int irq)
{
    if (trace_event_get_state(TRACE_GIC_ENABLE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 98 "../xemu/hw/intc/trace-events"
            qemu_log("gic_enable_irq " "irq %d enabled" "\n", irq);
#line 1901 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_DISABLE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_DISABLE_IRQ) || \
    false)

static inline void trace_gic_disable_irq(int irq)
{
    if (trace_event_get_state(TRACE_GIC_DISABLE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 99 "../xemu/hw/intc/trace-events"
            qemu_log("gic_disable_irq " "irq %d disabled" "\n", irq);
#line 1916 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_SET_IRQ) || \
    false)

static inline void trace_gic_set_irq(int irq, int level, int cpumask, int target)
{
    if (trace_event_get_state(TRACE_GIC_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 100 "../xemu/hw/intc/trace-events"
            qemu_log("gic_set_irq " "irq %d level %d cpumask 0x%x target 0x%x" "\n", irq, level, cpumask, target);
#line 1931 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_UPDATE_BESTIRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_UPDATE_BESTIRQ) || \
    false)

static inline void trace_gic_update_bestirq(const char *s, int cpu, int irq, int prio, int priority_mask, int running_priority)
{
    if (trace_event_get_state(TRACE_GIC_UPDATE_BESTIRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 101 "../xemu/hw/intc/trace-events"
            qemu_log("gic_update_bestirq " "%s %d irq %d priority %d cpu priority mask %d cpu running priority %d" "\n", s, cpu, irq, prio, priority_mask, running_priority);
#line 1946 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_UPDATE_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_UPDATE_SET_IRQ) || \
    false)

static inline void trace_gic_update_set_irq(int cpu, const char *name, int level)
{
    if (trace_event_get_state(TRACE_GIC_UPDATE_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 102 "../xemu/hw/intc/trace-events"
            qemu_log("gic_update_set_irq " "cpu[%d]: %s = %d" "\n", cpu, name, level);
#line 1961 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_ACKNOWLEDGE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_ACKNOWLEDGE_IRQ) || \
    false)

static inline void trace_gic_acknowledge_irq(const char *s, int cpu, int irq)
{
    if (trace_event_get_state(TRACE_GIC_ACKNOWLEDGE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 103 "../xemu/hw/intc/trace-events"
            qemu_log("gic_acknowledge_irq " "%s %d acknowledged irq %d" "\n", s, cpu, irq);
#line 1976 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_CPU_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_CPU_WRITE) || \
    false)

static inline void trace_gic_cpu_write(const char *s, int cpu, int addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_GIC_CPU_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 104 "../xemu/hw/intc/trace-events"
            qemu_log("gic_cpu_write " "%s %d iface write at 0x%08x 0x%08" PRIx32 "\n", s, cpu, addr, val);
#line 1991 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_CPU_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_CPU_READ) || \
    false)

static inline void trace_gic_cpu_read(const char *s, int cpu, int addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_GIC_CPU_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 105 "../xemu/hw/intc/trace-events"
            qemu_log("gic_cpu_read " "%s %d iface read at 0x%08x: 0x%08" PRIx32 "\n", s, cpu, addr, val);
#line 2006 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_HYP_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_HYP_READ) || \
    false)

static inline void trace_gic_hyp_read(int addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_GIC_HYP_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 106 "../xemu/hw/intc/trace-events"
            qemu_log("gic_hyp_read " "hyp read at 0x%08x: 0x%08" PRIx32 "\n", addr, val);
#line 2021 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_HYP_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_HYP_WRITE) || \
    false)

static inline void trace_gic_hyp_write(int addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_GIC_HYP_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 107 "../xemu/hw/intc/trace-events"
            qemu_log("gic_hyp_write " "hyp write at 0x%08x: 0x%08" PRIx32 "\n", addr, val);
#line 2036 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_DIST_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_DIST_READ) || \
    false)

static inline void trace_gic_dist_read(int addr, unsigned int size, uint32_t val)
{
    if (trace_event_get_state(TRACE_GIC_DIST_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 108 "../xemu/hw/intc/trace-events"
            qemu_log("gic_dist_read " "dist read at 0x%08x size %u: 0x%08" PRIx32 "\n", addr, size, val);
#line 2051 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_DIST_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_DIST_WRITE) || \
    false)

static inline void trace_gic_dist_write(int addr, unsigned int size, uint32_t val)
{
    if (trace_event_get_state(TRACE_GIC_DIST_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 109 "../xemu/hw/intc/trace-events"
            qemu_log("gic_dist_write " "dist write at 0x%08x size %u: 0x%08" PRIx32 "\n", addr, size, val);
#line 2066 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_LR_ENTRY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_LR_ENTRY) || \
    false)

static inline void trace_gic_lr_entry(int cpu, int entry, uint32_t val)
{
    if (trace_event_get_state(TRACE_GIC_LR_ENTRY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 110 "../xemu/hw/intc/trace-events"
            qemu_log("gic_lr_entry " "cpu %d: new lr entry %d: 0x%08" PRIx32 "\n", cpu, entry, val);
#line 2081 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GIC_UPDATE_MAINTENANCE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GIC_UPDATE_MAINTENANCE_IRQ) || \
    false)

static inline void trace_gic_update_maintenance_irq(int cpu, int val)
{
    if (trace_event_get_state(TRACE_GIC_UPDATE_MAINTENANCE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 111 "../xemu/hw/intc/trace-events"
            qemu_log("gic_update_maintenance_irq " "cpu %d: maintenance = %d" "\n", cpu, val);
#line 2096 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_PMR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_PMR_READ) || \
    false)

static inline void trace_gicv3_icc_pmr_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_PMR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 114 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_pmr_read " "GICv3 ICC_PMR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2111 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_PMR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_PMR_WRITE) || \
    false)

static inline void trace_gicv3_icc_pmr_write(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_PMR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 115 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_pmr_write " "GICv3 ICC_PMR write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2126 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_BPR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_BPR_READ) || \
    false)

static inline void trace_gicv3_icc_bpr_read(int grp, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_BPR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 116 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_bpr_read " "GICv3 ICC_BPR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val);
#line 2141 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_BPR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_BPR_WRITE) || \
    false)

static inline void trace_gicv3_icc_bpr_write(int grp, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_BPR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 117 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_bpr_write " "GICv3 ICC_BPR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val);
#line 2156 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_AP_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_AP_READ) || \
    false)

static inline void trace_gicv3_icc_ap_read(int grp, int regno, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_AP_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 118 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_ap_read " "GICv3 ICC_AP%dR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, regno, cpu, val);
#line 2171 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_AP_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_AP_WRITE) || \
    false)

static inline void trace_gicv3_icc_ap_write(int grp, int regno, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_AP_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 119 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_ap_write " "GICv3 ICC_AP%dR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, regno, cpu, val);
#line 2186 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_IGRPEN_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_IGRPEN_READ) || \
    false)

static inline void trace_gicv3_icc_igrpen_read(int grp, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_IGRPEN_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 120 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_igrpen_read " "GICv3 ICC_IGRPEN%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val);
#line 2201 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_IGRPEN_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_IGRPEN_WRITE) || \
    false)

static inline void trace_gicv3_icc_igrpen_write(int grp, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_IGRPEN_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 121 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_igrpen_write " "GICv3 ICC_IGRPEN%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val);
#line 2216 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_IGRPEN1_EL3_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_IGRPEN1_EL3_READ) || \
    false)

static inline void trace_gicv3_icc_igrpen1_el3_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_IGRPEN1_EL3_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 122 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_igrpen1_el3_read " "GICv3 ICC_IGRPEN1_EL3 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2231 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE) || \
    false)

static inline void trace_gicv3_icc_igrpen1_el3_write(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 123 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_igrpen1_el3_write " "GICv3 ICC_IGRPEN1_EL3 write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2246 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_CTLR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_CTLR_READ) || \
    false)

static inline void trace_gicv3_icc_ctlr_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_CTLR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 124 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_ctlr_read " "GICv3 ICC_CTLR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2261 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_CTLR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_CTLR_WRITE) || \
    false)

static inline void trace_gicv3_icc_ctlr_write(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_CTLR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 125 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_ctlr_write " "GICv3 ICC_CTLR write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2276 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_CTLR_EL3_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_CTLR_EL3_READ) || \
    false)

static inline void trace_gicv3_icc_ctlr_el3_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_CTLR_EL3_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 126 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_ctlr_el3_read " "GICv3 ICC_CTLR_EL3 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2291 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_CTLR_EL3_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_CTLR_EL3_WRITE) || \
    false)

static inline void trace_gicv3_icc_ctlr_el3_write(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_CTLR_EL3_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 127 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_ctlr_el3_write " "GICv3 ICC_CTLR_EL3 write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2306 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_CPUIF_UPDATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_CPUIF_UPDATE) || \
    false)

static inline void trace_gicv3_cpuif_update(uint32_t cpuid, int irq, int grp, int prio)
{
    if (trace_event_get_state(TRACE_GICV3_CPUIF_UPDATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 128 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_cpuif_update " "GICv3 CPU i/f 0x%x HPPI update: irq %d group %d prio %d" "\n", cpuid, irq, grp, prio);
#line 2321 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_CPUIF_SET_IRQS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_CPUIF_SET_IRQS) || \
    false)

static inline void trace_gicv3_cpuif_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel)
{
    if (trace_event_get_state(TRACE_GICV3_CPUIF_SET_IRQS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 129 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_cpuif_set_irqs " "GICv3 CPU i/f 0x%x HPPI update: setting FIQ %d IRQ %d" "\n", cpuid, fiqlevel, irqlevel);
#line 2336 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_GENERATE_SGI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_GENERATE_SGI) || \
    false)

static inline void trace_gicv3_icc_generate_sgi(uint32_t cpuid, int irq, int irm, uint32_t aff, uint32_t targetlist)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_GENERATE_SGI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 130 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_generate_sgi " "GICv3 CPU i/f 0x%x generating SGI %d IRM %d target affinity 0x%xxx targetlist 0x%x" "\n", cpuid, irq, irm, aff, targetlist);
#line 2351 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_IAR0_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_IAR0_READ) || \
    false)

static inline void trace_gicv3_icc_iar0_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_IAR0_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 131 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_iar0_read " "GICv3 ICC_IAR0 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2366 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_IAR1_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_IAR1_READ) || \
    false)

static inline void trace_gicv3_icc_iar1_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_IAR1_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 132 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_iar1_read " "GICv3 ICC_IAR1 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2381 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_NMIAR1_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_NMIAR1_READ) || \
    false)

static inline void trace_gicv3_icc_nmiar1_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_NMIAR1_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 133 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_nmiar1_read " "GICv3 ICC_NMIAR1 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2396 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_EOIR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_EOIR_WRITE) || \
    false)

static inline void trace_gicv3_icc_eoir_write(int grp, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_EOIR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 134 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_eoir_write " "GICv3 ICC_EOIR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val);
#line 2411 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_HPPIR0_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_HPPIR0_READ) || \
    false)

static inline void trace_gicv3_icc_hppir0_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_HPPIR0_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 135 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_hppir0_read " "GICv3 ICC_HPPIR0 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2426 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_HPPIR1_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_HPPIR1_READ) || \
    false)

static inline void trace_gicv3_icc_hppir1_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_HPPIR1_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 136 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_hppir1_read " "GICv3 ICC_HPPIR1 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2441 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_DIR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_DIR_WRITE) || \
    false)

static inline void trace_gicv3_icc_dir_write(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_DIR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 137 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_dir_write " "GICv3 ICC_DIR write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2456 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICC_RPR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_RPR_READ) || \
    false)

static inline void trace_gicv3_icc_rpr_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICC_RPR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 138 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icc_rpr_read " "GICv3 ICC_RPR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2471 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_AP_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_AP_READ) || \
    false)

static inline void trace_gicv3_ich_ap_read(int grp, int regno, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_AP_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 139 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_ap_read " "GICv3 ICH_AP%dR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, regno, cpu, val);
#line 2486 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_AP_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_AP_WRITE) || \
    false)

static inline void trace_gicv3_ich_ap_write(int grp, int regno, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_AP_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 140 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_ap_write " "GICv3 ICH_AP%dR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, regno, cpu, val);
#line 2501 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_HCR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_HCR_READ) || \
    false)

static inline void trace_gicv3_ich_hcr_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_HCR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 141 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_hcr_read " "GICv3 ICH_HCR_EL2 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2516 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_HCR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_HCR_WRITE) || \
    false)

static inline void trace_gicv3_ich_hcr_write(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_HCR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 142 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_hcr_write " "GICv3 ICH_HCR_EL2 write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2531 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_VMCR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_VMCR_READ) || \
    false)

static inline void trace_gicv3_ich_vmcr_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_VMCR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 143 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_vmcr_read " "GICv3 ICH_VMCR_EL2 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2546 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_VMCR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_VMCR_WRITE) || \
    false)

static inline void trace_gicv3_ich_vmcr_write(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_VMCR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 144 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_vmcr_write " "GICv3 ICH_VMCR_EL2 write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2561 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_LR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_LR_READ) || \
    false)

static inline void trace_gicv3_ich_lr_read(int regno, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_LR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 145 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_lr_read " "GICv3 ICH_LR%d_EL2 read cpu 0x%x value 0x%" PRIx64 "\n", regno, cpu, val);
#line 2576 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_LR32_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_LR32_READ) || \
    false)

static inline void trace_gicv3_ich_lr32_read(int regno, uint32_t cpu, uint32_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_LR32_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 146 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_lr32_read " "GICv3 ICH_LR%d read cpu 0x%x value 0x%" PRIx32 "\n", regno, cpu, val);
#line 2591 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_LRC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_LRC_READ) || \
    false)

static inline void trace_gicv3_ich_lrc_read(int regno, uint32_t cpu, uint32_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_LRC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 147 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_lrc_read " "GICv3 ICH_LRC%d read cpu 0x%x value 0x%" PRIx32 "\n", regno, cpu, val);
#line 2606 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_LR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_LR_WRITE) || \
    false)

static inline void trace_gicv3_ich_lr_write(int regno, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_LR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 148 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_lr_write " "GICv3 ICH_LR%d_EL2 write cpu 0x%x value 0x%" PRIx64 "\n", regno, cpu, val);
#line 2621 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_LR32_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_LR32_WRITE) || \
    false)

static inline void trace_gicv3_ich_lr32_write(int regno, uint32_t cpu, uint32_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_LR32_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 149 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_lr32_write " "GICv3 ICH_LR%d write cpu 0x%x value 0x%" PRIx32 "\n", regno, cpu, val);
#line 2636 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_LRC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_LRC_WRITE) || \
    false)

static inline void trace_gicv3_ich_lrc_write(int regno, uint32_t cpu, uint32_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_LRC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 150 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_lrc_write " "GICv3 ICH_LRC%d write cpu 0x%x value 0x%" PRIx32 "\n", regno, cpu, val);
#line 2651 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_VTR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_VTR_READ) || \
    false)

static inline void trace_gicv3_ich_vtr_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_VTR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 151 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_vtr_read " "GICv3 ICH_VTR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2666 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_MISR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_MISR_READ) || \
    false)

static inline void trace_gicv3_ich_misr_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_MISR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 152 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_misr_read " "GICv3 ICH_MISR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2681 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_EISR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_EISR_READ) || \
    false)

static inline void trace_gicv3_ich_eisr_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_EISR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 153 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_eisr_read " "GICv3 ICH_EISR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2696 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICH_ELRSR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_ELRSR_READ) || \
    false)

static inline void trace_gicv3_ich_elrsr_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICH_ELRSR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 154 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_ich_elrsr_read " "GICv3 ICH_ELRSR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2711 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_AP_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_AP_READ) || \
    false)

static inline void trace_gicv3_icv_ap_read(int grp, int regno, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_AP_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 155 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_ap_read " "GICv3 ICV_AP%dR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, regno, cpu, val);
#line 2726 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_AP_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_AP_WRITE) || \
    false)

static inline void trace_gicv3_icv_ap_write(int grp, int regno, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_AP_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 156 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_ap_write " "GICv3 ICV_AP%dR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, regno, cpu, val);
#line 2741 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_BPR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_BPR_READ) || \
    false)

static inline void trace_gicv3_icv_bpr_read(int grp, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_BPR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 157 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_bpr_read " "GICv3 ICV_BPR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val);
#line 2756 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_BPR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_BPR_WRITE) || \
    false)

static inline void trace_gicv3_icv_bpr_write(int grp, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_BPR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 158 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_bpr_write " "GICv3 ICV_BPR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val);
#line 2771 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_PMR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_PMR_READ) || \
    false)

static inline void trace_gicv3_icv_pmr_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_PMR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 159 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_pmr_read " "GICv3 ICV_PMR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2786 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_PMR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_PMR_WRITE) || \
    false)

static inline void trace_gicv3_icv_pmr_write(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_PMR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 160 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_pmr_write " "GICv3 ICV_PMR write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2801 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_IGRPEN_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_IGRPEN_READ) || \
    false)

static inline void trace_gicv3_icv_igrpen_read(int grp, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_IGRPEN_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 161 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_igrpen_read " "GICv3 ICV_IGRPEN%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val);
#line 2816 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_IGRPEN_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_IGRPEN_WRITE) || \
    false)

static inline void trace_gicv3_icv_igrpen_write(int grp, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_IGRPEN_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 162 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_igrpen_write " "GICv3 ICV_IGRPEN%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val);
#line 2831 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_CTLR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_CTLR_READ) || \
    false)

static inline void trace_gicv3_icv_ctlr_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_CTLR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 163 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_ctlr_read " "GICv3 ICV_CTLR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2846 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_CTLR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_CTLR_WRITE) || \
    false)

static inline void trace_gicv3_icv_ctlr_write(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_CTLR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 164 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_ctlr_write " "GICv3 ICV_CTLR write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2861 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_RPR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_RPR_READ) || \
    false)

static inline void trace_gicv3_icv_rpr_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_RPR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 165 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_rpr_read " "GICv3 ICV_RPR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2876 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_HPPIR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_HPPIR_READ) || \
    false)

static inline void trace_gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_HPPIR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 166 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_hppir_read " "GICv3 ICV_HPPIR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val);
#line 2891 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_DIR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_DIR_WRITE) || \
    false)

static inline void trace_gicv3_icv_dir_write(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_DIR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 167 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_dir_write " "GICv3 ICV_DIR write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2906 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_IAR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_IAR_READ) || \
    false)

static inline void trace_gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_IAR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 168 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_iar_read " "GICv3 ICV_IAR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val);
#line 2921 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_NMIAR1_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_NMIAR1_READ) || \
    false)

static inline void trace_gicv3_icv_nmiar1_read(uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_NMIAR1_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 169 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_nmiar1_read " "GICv3 ICV_NMIAR1 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val);
#line 2936 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ICV_EOIR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_EOIR_WRITE) || \
    false)

static inline void trace_gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val)
{
    if (trace_event_get_state(TRACE_GICV3_ICV_EOIR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 170 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_icv_eoir_write " "GICv3 ICV_EOIR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val);
#line 2951 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_CPUIF_VIRT_UPDATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_CPUIF_VIRT_UPDATE) || \
    false)

static inline void trace_gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int hppvlpi, int grp, int prio)
{
    if (trace_event_get_state(TRACE_GICV3_CPUIF_VIRT_UPDATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 171 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_cpuif_virt_update " "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d grp %d prio %d" "\n", cpuid, idx, hppvlpi, grp, prio);
#line 2966 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_CPUIF_VIRT_SET_IRQS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_CPUIF_VIRT_SET_IRQS) || \
    false)

static inline void trace_gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel)
{
    if (trace_event_get_state(TRACE_GICV3_CPUIF_VIRT_SET_IRQS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 172 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_cpuif_virt_set_irqs " "GICv3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d" "\n", cpuid, fiqlevel, irqlevel);
#line 2981 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_CPUIF_VIRT_SET_MAINT_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_CPUIF_VIRT_SET_MAINT_IRQ) || \
    false)

static inline void trace_gicv3_cpuif_virt_set_maint_irq(uint32_t cpuid, int maintlevel)
{
    if (trace_event_get_state(TRACE_GICV3_CPUIF_VIRT_SET_MAINT_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 173 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_cpuif_virt_set_maint_irq " "GICv3 CPU i/f 0x%x virt HPPI update: setting maintenance-irq %d" "\n", cpuid, maintlevel);
#line 2996 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_DIST_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_DIST_READ) || \
    false)

static inline void trace_gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure)
{
    if (trace_event_get_state(TRACE_GICV3_DIST_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 176 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_dist_read " "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", offset, data, size, secure);
#line 3011 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_DIST_BADREAD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_DIST_BADREAD) || \
    false)

static inline void trace_gicv3_dist_badread(uint64_t offset, unsigned size, bool secure)
{
    if (trace_event_get_state(TRACE_GICV3_DIST_BADREAD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 177 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_dist_badread " "GICv3 distributor read: offset 0x%" PRIx64 " size %u secure %d: error" "\n", offset, size, secure);
#line 3026 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_DIST_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_DIST_WRITE) || \
    false)

static inline void trace_gicv3_dist_write(uint64_t offset, uint64_t data, unsigned size, bool secure)
{
    if (trace_event_get_state(TRACE_GICV3_DIST_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 178 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_dist_write " "GICv3 distributor write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", offset, data, size, secure);
#line 3041 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_DIST_BADWRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_DIST_BADWRITE) || \
    false)

static inline void trace_gicv3_dist_badwrite(uint64_t offset, uint64_t data, unsigned size, bool secure)
{
    if (trace_event_get_state(TRACE_GICV3_DIST_BADWRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 179 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_dist_badwrite " "GICv3 distributor write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d: error" "\n", offset, data, size, secure);
#line 3056 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_DIST_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_DIST_SET_IRQ) || \
    false)

static inline void trace_gicv3_dist_set_irq(int irq, int level)
{
    if (trace_event_get_state(TRACE_GICV3_DIST_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 180 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_dist_set_irq " "GICv3 distributor interrupt %d level changed to %d" "\n", irq, level);
#line 3071 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_REDIST_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_REDIST_READ) || \
    false)

static inline void trace_gicv3_redist_read(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure)
{
    if (trace_event_get_state(TRACE_GICV3_REDIST_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 183 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_redist_read " "GICv3 redistributor 0x%x read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", cpu, offset, data, size, secure);
#line 3086 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_REDIST_BADREAD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_REDIST_BADREAD) || \
    false)

static inline void trace_gicv3_redist_badread(uint32_t cpu, uint64_t offset, unsigned size, bool secure)
{
    if (trace_event_get_state(TRACE_GICV3_REDIST_BADREAD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 184 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_redist_badread " "GICv3 redistributor 0x%x read: offset 0x%" PRIx64 " size %u secure %d: error" "\n", cpu, offset, size, secure);
#line 3101 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_REDIST_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_REDIST_WRITE) || \
    false)

static inline void trace_gicv3_redist_write(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure)
{
    if (trace_event_get_state(TRACE_GICV3_REDIST_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 185 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_redist_write " "GICv3 redistributor 0x%x write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", cpu, offset, data, size, secure);
#line 3116 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_REDIST_BADWRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_REDIST_BADWRITE) || \
    false)

static inline void trace_gicv3_redist_badwrite(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure)
{
    if (trace_event_get_state(TRACE_GICV3_REDIST_BADWRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 186 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_redist_badwrite " "GICv3 redistributor 0x%x write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d: error" "\n", cpu, offset, data, size, secure);
#line 3131 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_REDIST_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_REDIST_SET_IRQ) || \
    false)

static inline void trace_gicv3_redist_set_irq(uint32_t cpu, int irq, int level)
{
    if (trace_event_get_state(TRACE_GICV3_REDIST_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 187 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_redist_set_irq " "GICv3 redistributor 0x%x interrupt %d level changed to %d" "\n", cpu, irq, level);
#line 3146 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_REDIST_SEND_SGI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_REDIST_SEND_SGI) || \
    false)

static inline void trace_gicv3_redist_send_sgi(uint32_t cpu, int irq)
{
    if (trace_event_get_state(TRACE_GICV3_REDIST_SEND_SGI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 188 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_redist_send_sgi " "GICv3 redistributor 0x%x pending SGI %d" "\n", cpu, irq);
#line 3161 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_READ) || \
    false)

static inline void trace_gicv3_its_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 191 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_read " "GICv3 ITS read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3176 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_BADREAD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_BADREAD) || \
    false)

static inline void trace_gicv3_its_badread(uint64_t offset, unsigned size)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_BADREAD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 192 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_badread " "GICv3 ITS read: offset 0x%" PRIx64 " size %u: error" "\n", offset, size);
#line 3191 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_WRITE) || \
    false)

static inline void trace_gicv3_its_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 193 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_write " "GICv3 ITS write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3206 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_BADWRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_BADWRITE) || \
    false)

static inline void trace_gicv3_its_badwrite(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_BADWRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 194 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_badwrite " "GICv3 ITS write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u: error" "\n", offset, data, size);
#line 3221 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_TRANSLATION_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_TRANSLATION_WRITE) || \
    false)

static inline void trace_gicv3_its_translation_write(uint64_t offset, uint64_t data, unsigned size, uint32_t requester_id)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_TRANSLATION_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 195 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_translation_write " "GICv3 ITS TRANSLATER write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u requester_id 0x%x" "\n", offset, data, size, requester_id);
#line 3236 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_PROCESS_COMMAND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_PROCESS_COMMAND) || \
    false)

static inline void trace_gicv3_its_process_command(uint32_t rd_offset, uint8_t cmd)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_PROCESS_COMMAND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 196 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_process_command " "GICv3 ITS: processing command at offset 0x%x: 0x%x" "\n", rd_offset, cmd);
#line 3251 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_INT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_INT) || \
    false)

static inline void trace_gicv3_its_cmd_int(uint32_t devid, uint32_t eventid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_INT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 197 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_int " "GICv3 ITS: command INT DeviceID 0x%x EventID 0x%x" "\n", devid, eventid);
#line 3266 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_CLEAR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_CLEAR) || \
    false)

static inline void trace_gicv3_its_cmd_clear(uint32_t devid, uint32_t eventid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_CLEAR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 198 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_clear " "GICv3 ITS: command CLEAR DeviceID 0x%x EventID 0x%x" "\n", devid, eventid);
#line 3281 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_DISCARD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_DISCARD) || \
    false)

static inline void trace_gicv3_its_cmd_discard(uint32_t devid, uint32_t eventid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_DISCARD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 199 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_discard " "GICv3 ITS: command DISCARD DeviceID 0x%x EventID 0x%x" "\n", devid, eventid);
#line 3296 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_SYNC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_SYNC) || \
    false)

static inline void trace_gicv3_its_cmd_sync(void)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_SYNC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 200 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_sync " "GICv3 ITS: command SYNC" "\n");
#line 3311 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_MAPD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_MAPD) || \
    false)

static inline void trace_gicv3_its_cmd_mapd(uint32_t devid, uint32_t size, uint64_t ittaddr, int valid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_MAPD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 201 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_mapd " "GICv3 ITS: command MAPD DeviceID 0x%x Size 0x%x ITT_addr 0x%" PRIx64 " V %d" "\n", devid, size, ittaddr, valid);
#line 3326 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_MAPC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_MAPC) || \
    false)

static inline void trace_gicv3_its_cmd_mapc(uint32_t icid, uint64_t rdbase, int valid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_MAPC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 202 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_mapc " "GICv3 ITS: command MAPC ICID 0x%x RDbase 0x%" PRIx64 " V %d" "\n", icid, rdbase, valid);
#line 3341 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_MAPI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_MAPI) || \
    false)

static inline void trace_gicv3_its_cmd_mapi(uint32_t devid, uint32_t eventid, uint32_t icid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_MAPI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 203 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_mapi " "GICv3 ITS: command MAPI DeviceID 0x%x EventID 0x%x ICID 0x%x" "\n", devid, eventid, icid);
#line 3356 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_MAPTI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_MAPTI) || \
    false)

static inline void trace_gicv3_its_cmd_mapti(uint32_t devid, uint32_t eventid, uint32_t icid, uint32_t intid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_MAPTI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 204 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_mapti " "GICv3 ITS: command MAPTI DeviceID 0x%x EventID 0x%x ICID 0x%x pINTID 0x%x" "\n", devid, eventid, icid, intid);
#line 3371 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_INV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_INV) || \
    false)

static inline void trace_gicv3_its_cmd_inv(uint32_t devid, uint32_t eventid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_INV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 205 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_inv " "GICv3 ITS: command INV DeviceID 0x%x EventID 0x%x" "\n", devid, eventid);
#line 3386 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_INVALL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_INVALL) || \
    false)

static inline void trace_gicv3_its_cmd_invall(void)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_INVALL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 206 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_invall " "GICv3 ITS: command INVALL" "\n");
#line 3401 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_MOVALL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_MOVALL) || \
    false)

static inline void trace_gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_MOVALL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 207 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_movall " "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " RDbase2 0x%" PRIx64 "\n", rd1, rd2);
#line 3416 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_MOVI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_MOVI) || \
    false)

static inline void trace_gicv3_its_cmd_movi(uint32_t devid, uint32_t eventid, uint32_t icid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_MOVI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 208 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_movi " "GICv3 ITS: command MOVI DeviceID 0x%x EventID 0x%x ICID 0x%x" "\n", devid, eventid, icid);
#line 3431 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_VMAPI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VMAPI) || \
    false)

static inline void trace_gicv3_its_cmd_vmapi(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t doorbell)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VMAPI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 209 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_vmapi " "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x Dbell_pINTID 0x%x" "\n", devid, eventid, vpeid, doorbell);
#line 3446 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_VMAPTI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VMAPTI) || \
    false)

static inline void trace_gicv3_its_cmd_vmapti(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t vintid, uint32_t doorbell)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VMAPTI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 210 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_vmapti " "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x vINTID 0x%x Dbell_pINTID 0x%x" "\n", devid, eventid, vpeid, vintid, doorbell);
#line 3461 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_VMAPP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VMAPP) || \
    false)

static inline void trace_gicv3_its_cmd_vmapp(uint32_t vpeid, uint64_t rdbase, int valid, uint64_t vptaddr, uint32_t vptsize)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VMAPP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 211 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_vmapp " "GICv3 ITS: command VMAPP vPEID 0x%x RDbase 0x%" PRIx64 " V %d VPT_addr 0x%" PRIx64 " VPT_size 0x%x" "\n", vpeid, rdbase, valid, vptaddr, vptsize);
#line 3476 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_VMOVP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VMOVP) || \
    false)

static inline void trace_gicv3_its_cmd_vmovp(uint32_t vpeid, uint64_t rdbase)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VMOVP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 212 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_vmovp " "GICv3 ITS: command VMOVP vPEID 0x%x RDbase 0x%" PRIx64 "\n", vpeid, rdbase);
#line 3491 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_VSYNC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VSYNC) || \
    false)

static inline void trace_gicv3_its_cmd_vsync(void)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VSYNC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 213 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_vsync " "GICv3 ITS: command VSYNC" "\n");
#line 3506 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_VMOVI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VMOVI) || \
    false)

static inline void trace_gicv3_its_cmd_vmovi(uint32_t devid, uint32_t eventid, uint32_t vpeid, int dbvalid, uint32_t doorbell)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VMOVI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 214 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_vmovi " "GICv3 ITS: command VMOVI DeviceID 0x%x EventID 0x%x vPEID 0x%x D %d Dbell_pINTID 0x%x" "\n", devid, eventid, vpeid, dbvalid, doorbell);
#line 3521 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_VINVALL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VINVALL) || \
    false)

static inline void trace_gicv3_its_cmd_vinvall(uint32_t vpeid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VINVALL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 215 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_vinvall " "GICv3 ITS: command VINVALL vPEID 0x%x" "\n", vpeid);
#line 3536 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CMD_UNKNOWN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_UNKNOWN) || \
    false)

static inline void trace_gicv3_its_cmd_unknown(unsigned cmd)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CMD_UNKNOWN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 216 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cmd_unknown " "GICv3 ITS: unknown command 0x%x" "\n", cmd);
#line 3551 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CTE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CTE_READ) || \
    false)

static inline void trace_gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CTE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 217 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cte_read " "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x" "\n", icid, valid, rdbase);
#line 3566 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CTE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CTE_WRITE) || \
    false)

static inline void trace_gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CTE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 218 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cte_write " "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x" "\n", icid, valid, rdbase);
#line 3581 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_CTE_READ_FAULT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CTE_READ_FAULT) || \
    false)

static inline void trace_gicv3_its_cte_read_fault(uint32_t icid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_CTE_READ_FAULT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 219 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_cte_read_fault " "GICv3 ITS: Collection Table read for ICID 0x%x: faulted" "\n", icid);
#line 3596 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_ITE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_ITE_READ) || \
    false)

static inline void trace_gicv3_its_ite_read(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, uint32_t intid, uint32_t icid, uint32_t vpeid, uint32_t doorbell)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_ITE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 220 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_ite_read " "GICv3 ITS: Interrupt Table read for ITTaddr 0x%" PRIx64 " EventID 0x%x: valid %d inttype %d intid 0x%x ICID 0x%x vPEID 0x%x doorbell 0x%x" "\n", ittaddr, eventid, valid, inttype, intid, icid, vpeid, doorbell);
#line 3611 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_ITE_READ_FAULT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_ITE_READ_FAULT) || \
    false)

static inline void trace_gicv3_its_ite_read_fault(uint64_t ittaddr, uint32_t eventid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_ITE_READ_FAULT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 221 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_ite_read_fault " "GICv3 ITS: Interrupt Table read for ITTaddr 0x%" PRIx64 " EventID 0x%x: faulted" "\n", ittaddr, eventid);
#line 3626 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_ITE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_ITE_WRITE) || \
    false)

static inline void trace_gicv3_its_ite_write(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, uint32_t intid, uint32_t icid, uint32_t vpeid, uint32_t doorbell)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_ITE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 222 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_ite_write " "GICv3 ITS: Interrupt Table write for ITTaddr 0x%" PRIx64 " EventID 0x%x: valid %d inttype %d intid 0x%x ICID 0x%x vPEID 0x%x doorbell 0x%x" "\n", ittaddr, eventid, valid, inttype, intid, icid, vpeid, doorbell);
#line 3641 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_DTE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_DTE_READ) || \
    false)

static inline void trace_gicv3_its_dte_read(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_DTE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 223 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_dte_read " "GICv3 ITS: Device Table read for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64 "\n", devid, valid, size, ittaddr);
#line 3656 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_DTE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_DTE_WRITE) || \
    false)

static inline void trace_gicv3_its_dte_write(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_DTE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 224 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_dte_write " "GICv3 ITS: Device Table write for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64 "\n", devid, valid, size, ittaddr);
#line 3671 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_DTE_READ_FAULT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_DTE_READ_FAULT) || \
    false)

static inline void trace_gicv3_its_dte_read_fault(uint32_t devid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_DTE_READ_FAULT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 225 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_dte_read_fault " "GICv3 ITS: Device Table read for DeviceID 0x%x: faulted" "\n", devid);
#line 3686 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_VTE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_VTE_READ) || \
    false)

static inline void trace_gicv3_its_vte_read(uint32_t vpeid, int valid, uint32_t vptsize, uint64_t vptaddr, uint32_t rdbase)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_VTE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 226 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_vte_read " "GICv3 ITS: vPE Table read for vPEID 0x%x: valid %d VPTsize 0x%x VPTaddr 0x%" PRIx64 " RDbase 0x%x" "\n", vpeid, valid, vptsize, vptaddr, rdbase);
#line 3701 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_VTE_READ_FAULT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_VTE_READ_FAULT) || \
    false)

static inline void trace_gicv3_its_vte_read_fault(uint32_t vpeid)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_VTE_READ_FAULT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 227 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_vte_read_fault " "GICv3 ITS: vPE Table read for vPEID 0x%x: faulted" "\n", vpeid);
#line 3716 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GICV3_ITS_VTE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_VTE_WRITE) || \
    false)

static inline void trace_gicv3_its_vte_write(uint32_t vpeid, int valid, uint32_t vptsize, uint64_t vptaddr, uint32_t rdbase)
{
    if (trace_event_get_state(TRACE_GICV3_ITS_VTE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 228 "../xemu/hw/intc/trace-events"
            qemu_log("gicv3_its_vte_write " "GICv3 ITS: vPE Table write for vPEID 0x%x: valid %d VPTsize 0x%x VPTaddr 0x%" PRIx64 " RDbase 0x%x" "\n", vpeid, valid, vptsize, vptaddr, rdbase);
#line 3731 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_RECOMPUTE_STATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_RECOMPUTE_STATE) || \
    false)

static inline void trace_nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio)
{
    if (trace_event_get_state(TRACE_NVIC_RECOMPUTE_STATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 231 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_recompute_state " "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d" "\n", vectpending, vectpending_prio, exception_prio);
#line 3746 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_RECOMPUTE_STATE_SECURE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_RECOMPUTE_STATE_SECURE) || \
    false)

static inline void trace_nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio)
{
    if (trace_event_get_state(TRACE_NVIC_RECOMPUTE_STATE_SECURE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 232 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_recompute_state_secure " "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d" "\n", vectpending, vectpending_is_s_banked, vectpending_prio, exception_prio);
#line 3761 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_SET_PRIO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_SET_PRIO) || \
    false)

static inline void trace_nvic_set_prio(int irq, bool secure, uint8_t prio)
{
    if (trace_event_get_state(TRACE_NVIC_SET_PRIO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 233 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_set_prio " "NVIC set irq %d secure-bank %d priority %d" "\n", irq, secure, prio);
#line 3776 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_IRQ_UPDATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_IRQ_UPDATE) || \
    false)

static inline void trace_nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level)
{
    if (trace_event_get_state(TRACE_NVIC_IRQ_UPDATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 234 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_irq_update " "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d" "\n", vectpending, pendprio, exception_prio, level);
#line 3791 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_ESCALATE_PRIO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_ESCALATE_PRIO) || \
    false)

static inline void trace_nvic_escalate_prio(int irq, int irqprio, int runprio)
{
    if (trace_event_get_state(TRACE_NVIC_ESCALATE_PRIO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 235 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_escalate_prio " "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d" "\n", irq, irqprio, runprio);
#line 3806 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_ESCALATE_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_ESCALATE_DISABLED) || \
    false)

static inline void trace_nvic_escalate_disabled(int irq)
{
    if (trace_event_get_state(TRACE_NVIC_ESCALATE_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 236 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_escalate_disabled " "NVIC escalating irq %d to HardFault: disabled" "\n", irq);
#line 3821 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_SET_PENDING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_SET_PENDING) || \
    false)

static inline void trace_nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, int en, int prio)
{
    if (trace_event_get_state(TRACE_NVIC_SET_PENDING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 237 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_set_pending " "NVIC set pending irq %d secure-bank %d targets_secure %d derived %d (enabled: %d priority %d)" "\n", irq, secure, targets_secure, derived, en, prio);
#line 3836 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_CLEAR_PENDING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_CLEAR_PENDING) || \
    false)

static inline void trace_nvic_clear_pending(int irq, bool secure, int en, int prio)
{
    if (trace_event_get_state(TRACE_NVIC_CLEAR_PENDING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 238 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_clear_pending " "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)" "\n", irq, secure, en, prio);
#line 3851 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_ACKNOWLEDGE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_ACKNOWLEDGE_IRQ) || \
    false)

static inline void trace_nvic_acknowledge_irq(int irq, int prio)
{
    if (trace_event_get_state(TRACE_NVIC_ACKNOWLEDGE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 239 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_acknowledge_irq " "NVIC acknowledge IRQ: %d now active (prio %d)" "\n", irq, prio);
#line 3866 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_GET_PENDING_IRQ_INFO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_GET_PENDING_IRQ_INFO) || \
    false)

static inline void trace_nvic_get_pending_irq_info(int irq, bool secure)
{
    if (trace_event_get_state(TRACE_NVIC_GET_PENDING_IRQ_INFO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 240 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_get_pending_irq_info " "NVIC next IRQ %d: targets_secure: %d" "\n", irq, secure);
#line 3881 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_COMPLETE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_COMPLETE_IRQ) || \
    false)

static inline void trace_nvic_complete_irq(int irq, bool secure)
{
    if (trace_event_get_state(TRACE_NVIC_COMPLETE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 241 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_complete_irq " "NVIC complete IRQ %d (secure %d)" "\n", irq, secure);
#line 3896 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_SET_IRQ_LEVEL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_SET_IRQ_LEVEL) || \
    false)

static inline void trace_nvic_set_irq_level(int irq, int level)
{
    if (trace_event_get_state(TRACE_NVIC_SET_IRQ_LEVEL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 242 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_set_irq_level " "NVIC external irq %d level set to %d" "\n", irq, level);
#line 3911 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_SET_NMI_LEVEL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_SET_NMI_LEVEL) || \
    false)

static inline void trace_nvic_set_nmi_level(int level)
{
    if (trace_event_get_state(TRACE_NVIC_SET_NMI_LEVEL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 243 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_set_nmi_level " "NVIC external NMI level set to %d" "\n", level);
#line 3926 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_SYSREG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_SYSREG_READ) || \
    false)

static inline void trace_nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_NVIC_SYSREG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 244 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_sysreg_read " "NVIC sysreg read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n", addr, value, size);
#line 3941 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_NVIC_SYSREG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NVIC_SYSREG_WRITE) || \
    false)

static inline void trace_nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_NVIC_SYSREG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 245 "../xemu/hw/intc/trace-events"
            qemu_log("nvic_sysreg_write " "NVIC sysreg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n", addr, value, size);
#line 3956 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_HEATHROW_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HEATHROW_WRITE) || \
    false)

static inline void trace_heathrow_write(uint64_t addr, unsigned int n, uint64_t value)
{
    if (trace_event_get_state(TRACE_HEATHROW_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 248 "../xemu/hw/intc/trace-events"
            qemu_log("heathrow_write " "0x%"PRIx64" %u: 0x%"PRIx64 "\n", addr, n, value);
#line 3971 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_HEATHROW_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HEATHROW_READ) || \
    false)

static inline void trace_heathrow_read(uint64_t addr, unsigned int n, uint64_t value)
{
    if (trace_event_get_state(TRACE_HEATHROW_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 249 "../xemu/hw/intc/trace-events"
            qemu_log("heathrow_read " "0x%"PRIx64" %u: 0x%"PRIx64 "\n", addr, n, value);
#line 3986 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_HEATHROW_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HEATHROW_SET_IRQ) || \
    false)

static inline void trace_heathrow_set_irq(int num, int level)
{
    if (trace_event_get_state(TRACE_HEATHROW_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 250 "../xemu/hw/intc/trace-events"
            qemu_log("heathrow_set_irq " "set_irq: num=0x%02x level=%d" "\n", num, level);
#line 4001 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_BCM2835_IC_SET_GPU_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_IC_SET_GPU_IRQ) || \
    false)

static inline void trace_bcm2835_ic_set_gpu_irq(int irq, int level)
{
    if (trace_event_get_state(TRACE_BCM2835_IC_SET_GPU_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 253 "../xemu/hw/intc/trace-events"
            qemu_log("bcm2835_ic_set_gpu_irq " "GPU irq #%d level %d" "\n", irq, level);
#line 4016 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_BCM2835_IC_SET_CPU_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_IC_SET_CPU_IRQ) || \
    false)

static inline void trace_bcm2835_ic_set_cpu_irq(int irq, int level)
{
    if (trace_event_get_state(TRACE_BCM2835_IC_SET_CPU_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 254 "../xemu/hw/intc/trace-events"
            qemu_log("bcm2835_ic_set_cpu_irq " "CPU irq #%d level %d" "\n", irq, level);
#line 4031 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_CLAIM_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_CLAIM_IRQ) || \
    false)

static inline void trace_spapr_xive_claim_irq(uint32_t lisn, bool lsi)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_CLAIM_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 257 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_claim_irq " "lisn=0x%x lsi=%d" "\n", lisn, lsi);
#line 4046 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_FREE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_FREE_IRQ) || \
    false)

static inline void trace_spapr_xive_free_irq(uint32_t lisn)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_FREE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 258 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_free_irq " "lisn=0x%x" "\n", lisn);
#line 4061 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_SET_IRQ) || \
    false)

static inline void trace_spapr_xive_set_irq(uint32_t lisn, uint32_t val)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 259 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_set_irq " "lisn=0x%x val=%d" "\n", lisn, val);
#line 4076 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_GET_SOURCE_INFO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_GET_SOURCE_INFO) || \
    false)

static inline void trace_spapr_xive_get_source_info(uint64_t flags, uint64_t lisn)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_GET_SOURCE_INFO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 260 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_get_source_info " "flags=0x%"PRIx64" lisn=0x%"PRIx64 "\n", flags, lisn);
#line 4091 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG) || \
    false)

static inline void trace_spapr_xive_set_source_config(uint64_t flags, uint64_t lisn, uint64_t target, uint64_t priority, uint64_t eisn)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 261 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_set_source_config " "flags=0x%"PRIx64" lisn=0x%"PRIx64" target=0x%"PRIx64" priority=0x%"PRIx64" eisn=0x%"PRIx64 "\n", flags, lisn, target, priority, eisn);
#line 4106 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG) || \
    false)

static inline void trace_spapr_xive_get_source_config(uint64_t flags, uint64_t lisn)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 262 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_get_source_config " "flags=0x%"PRIx64" lisn=0x%"PRIx64 "\n", flags, lisn);
#line 4121 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_GET_QUEUE_INFO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_GET_QUEUE_INFO) || \
    false)

static inline void trace_spapr_xive_get_queue_info(uint64_t flags, uint64_t target, uint64_t priority)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_GET_QUEUE_INFO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 263 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_get_queue_info " "flags=0x%"PRIx64" target=0x%"PRIx64" priority=0x%"PRIx64 "\n", flags, target, priority);
#line 4136 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG) || \
    false)

static inline void trace_spapr_xive_set_queue_config(uint64_t flags, uint64_t target, uint64_t priority, uint64_t qpage, uint64_t qsize)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 264 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_set_queue_config " "flags=0x%"PRIx64" target=0x%"PRIx64" priority=0x%"PRIx64" qpage=0x%"PRIx64" qsize=0x%"PRIx64 "\n", flags, target, priority, qpage, qsize);
#line 4151 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG) || \
    false)

static inline void trace_spapr_xive_get_queue_config(uint64_t flags, uint64_t target, uint64_t priority)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 265 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_get_queue_config " "flags=0x%"PRIx64" target=0x%"PRIx64" priority=0x%"PRIx64 "\n", flags, target, priority);
#line 4166 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE) || \
    false)

static inline void trace_spapr_xive_set_os_reporting_line(uint64_t flags)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 266 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_set_os_reporting_line " "flags=0x%"PRIx64 "\n", flags);
#line 4181 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE) || \
    false)

static inline void trace_spapr_xive_get_os_reporting_line(uint64_t flags)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 267 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_get_os_reporting_line " "flags=0x%"PRIx64 "\n", flags);
#line 4196 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_ESB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_ESB) || \
    false)

static inline void trace_spapr_xive_esb(uint64_t flags, uint64_t lisn, uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_ESB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 268 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_esb " "flags=0x%"PRIx64" lisn=0x%"PRIx64" offset=0x%"PRIx64" data=0x%"PRIx64 "\n", flags, lisn, offset, data);
#line 4211 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_SYNC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_SYNC) || \
    false)

static inline void trace_spapr_xive_sync(uint64_t flags, uint64_t lisn)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_SYNC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 269 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_sync " "flags=0x%"PRIx64" lisn=0x%"PRIx64 "\n", flags, lisn);
#line 4226 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SPAPR_XIVE_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_RESET) || \
    false)

static inline void trace_spapr_xive_reset(uint64_t flags)
{
    if (trace_event_get_state(TRACE_SPAPR_XIVE_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 270 "../xemu/hw/intc/trace-events"
            qemu_log("spapr_xive_reset " "flags=0x%"PRIx64 "\n", flags);
#line 4241 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_KVM_XIVE_CPU_CONNECT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_KVM_XIVE_CPU_CONNECT) || \
    false)

static inline void trace_kvm_xive_cpu_connect(uint32_t id)
{
    if (trace_event_get_state(TRACE_KVM_XIVE_CPU_CONNECT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 273 "../xemu/hw/intc/trace-events"
            qemu_log("kvm_xive_cpu_connect " "connect CPU%d to KVM device" "\n", id);
#line 4256 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_KVM_XIVE_SOURCE_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_KVM_XIVE_SOURCE_RESET) || \
    false)

static inline void trace_kvm_xive_source_reset(uint32_t srcno)
{
    if (trace_event_get_state(TRACE_KVM_XIVE_SOURCE_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 274 "../xemu/hw/intc/trace-events"
            qemu_log("kvm_xive_source_reset " "IRQ 0x%x" "\n", srcno);
#line 4271 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_TCTX_ACCEPT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_TCTX_ACCEPT) || \
    false)

static inline void trace_xive_tctx_accept(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, uint8_t cppr, uint8_t nsr)
{
    if (trace_event_get_state(TRACE_XIVE_TCTX_ACCEPT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 277 "../xemu/hw/intc/trace-events"
            qemu_log("xive_tctx_accept " "target=%d ring=0x%x IPB=0x%02x PIPR=0x%02x CPPR=0x%02x NSR=0x%02x ACK" "\n", index, ring, ipb, pipr, cppr, nsr);
#line 4286 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_TCTX_NOTIFY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_TCTX_NOTIFY) || \
    false)

static inline void trace_xive_tctx_notify(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, uint8_t cppr, uint8_t nsr)
{
    if (trace_event_get_state(TRACE_XIVE_TCTX_NOTIFY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 278 "../xemu/hw/intc/trace-events"
            qemu_log("xive_tctx_notify " "target=%d ring=0x%x IPB=0x%02x PIPR=0x%02x CPPR=0x%02x NSR=0x%02x raise !" "\n", index, ring, ipb, pipr, cppr, nsr);
#line 4301 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_TCTX_SET_CPPR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_TCTX_SET_CPPR) || \
    false)

static inline void trace_xive_tctx_set_cppr(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, uint8_t cppr, uint8_t nsr)
{
    if (trace_event_get_state(TRACE_XIVE_TCTX_SET_CPPR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 279 "../xemu/hw/intc/trace-events"
            qemu_log("xive_tctx_set_cppr " "target=%d ring=0x%x IPB=0x%02x PIPR=0x%02x new CPPR=0x%02x NSR=0x%02x" "\n", index, ring, ipb, pipr, cppr, nsr);
#line 4316 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_SOURCE_ESB_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_SOURCE_ESB_READ) || \
    false)

static inline void trace_xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value)
{
    if (trace_event_get_state(TRACE_XIVE_SOURCE_ESB_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 280 "../xemu/hw/intc/trace-events"
            qemu_log("xive_source_esb_read " "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64 "\n", addr, srcno, value);
#line 4331 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_SOURCE_ESB_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_SOURCE_ESB_WRITE) || \
    false)

static inline void trace_xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value)
{
    if (trace_event_get_state(TRACE_XIVE_SOURCE_ESB_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 281 "../xemu/hw/intc/trace-events"
            qemu_log("xive_source_esb_write " "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64 "\n", addr, srcno, value);
#line 4346 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_SOURCE_NOTIFY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_SOURCE_NOTIFY) || \
    false)

static inline void trace_xive_source_notify(uint32_t srcno)
{
    if (trace_event_get_state(TRACE_XIVE_SOURCE_NOTIFY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 282 "../xemu/hw/intc/trace-events"
            qemu_log("xive_source_notify " "Processing notification for queued IRQ 0x%x" "\n", srcno);
#line 4361 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_SOURCE_BLOCKED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_SOURCE_BLOCKED) || \
    false)

static inline void trace_xive_source_blocked(uint32_t srcno)
{
    if (trace_event_get_state(TRACE_XIVE_SOURCE_BLOCKED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 283 "../xemu/hw/intc/trace-events"
            qemu_log("xive_source_blocked " "No action needed for IRQ 0x%x currently" "\n", srcno);
#line 4376 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_ROUTER_END_NOTIFY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_ROUTER_END_NOTIFY) || \
    false)

static inline void trace_xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data)
{
    if (trace_event_get_state(TRACE_XIVE_ROUTER_END_NOTIFY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 284 "../xemu/hw/intc/trace-events"
            qemu_log("xive_router_end_notify " "END 0x%02x/0x%04x -> enqueue 0x%08x" "\n", end_blk, end_idx, end_data);
#line 4391 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_ROUTER_END_ESCALATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_ROUTER_END_ESCALATE) || \
    false)

static inline void trace_xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint32_t esc_idx, uint32_t end_data)
{
    if (trace_event_get_state(TRACE_XIVE_ROUTER_END_ESCALATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 285 "../xemu/hw/intc/trace-events"
            qemu_log("xive_router_end_escalate " "END 0x%02x/0x%04x -> escalate END 0x%02x/0x%04x data 0x%08x" "\n", end_blk, end_idx, esc_blk, esc_idx, end_data);
#line 4406 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_TCTX_TM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_TCTX_TM_WRITE) || \
    false)

static inline void trace_xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uint64_t value)
{
    if (trace_event_get_state(TRACE_XIVE_TCTX_TM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 286 "../xemu/hw/intc/trace-events"
            qemu_log("xive_tctx_tm_write " "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64 "\n", index, offset, size, value);
#line 4421 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_TCTX_TM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_TCTX_TM_READ) || \
    false)

static inline void trace_xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint64_t value)
{
    if (trace_event_get_state(TRACE_XIVE_TCTX_TM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 287 "../xemu/hw/intc/trace-events"
            qemu_log("xive_tctx_tm_read " "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64 "\n", index, offset, size, value);
#line 4436 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_PRESENTER_NOTIFY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_PRESENTER_NOTIFY) || \
    false)

static inline void trace_xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring, uint8_t group_level)
{
    if (trace_event_get_state(TRACE_XIVE_PRESENTER_NOTIFY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 288 "../xemu/hw/intc/trace-events"
            qemu_log("xive_presenter_notify " "found NVT 0x%x/0x%x ring=0x%x group_level=%d" "\n", nvt_blk, nvt_idx, ring, group_level);
#line 4451 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_END_SOURCE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_END_SOURCE_READ) || \
    false)

static inline void trace_xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr)
{
    if (trace_event_get_state(TRACE_XIVE_END_SOURCE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 289 "../xemu/hw/intc/trace-events"
            qemu_log("xive_end_source_read " "END 0x%x/0x%x @0x%"PRIx64 "\n", end_blk, end_idx, addr);
#line 4466 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_NVP_BACKLOG_OP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_NVP_BACKLOG_OP) || \
    false)

static inline void trace_xive_nvp_backlog_op(uint8_t blk, uint32_t idx, uint8_t op, uint8_t priority, uint8_t rc)
{
    if (trace_event_get_state(TRACE_XIVE_NVP_BACKLOG_OP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 292 "../xemu/hw/intc/trace-events"
            qemu_log("xive_nvp_backlog_op " "NVP 0x%x/0x%x operation=%d priority=%d rc=%d" "\n", blk, idx, op, priority, rc);
#line 4481 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_NVGC_BACKLOG_OP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_NVGC_BACKLOG_OP) || \
    false)

static inline void trace_xive_nvgc_backlog_op(bool c, uint8_t blk, uint32_t idx, uint8_t op, uint8_t priority, uint32_t rc)
{
    if (trace_event_get_state(TRACE_XIVE_NVGC_BACKLOG_OP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 293 "../xemu/hw/intc/trace-events"
            qemu_log("xive_nvgc_backlog_op " "NVGC crowd=%d 0x%x/0x%x operation=%d priority=%d rc=%d" "\n", c, blk, idx, op, priority, rc);
#line 4496 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_REDISTRIBUTE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_REDISTRIBUTE) || \
    false)

static inline void trace_xive_redistribute(uint32_t index, uint8_t ring, uint8_t end_blk, uint32_t end_idx)
{
    if (trace_event_get_state(TRACE_XIVE_REDISTRIBUTE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 294 "../xemu/hw/intc/trace-events"
            qemu_log("xive_redistribute " "Redistribute from target=%d ring=0x%x NVP 0x%x/0x%x" "\n", index, ring, end_blk, end_idx);
#line 4511 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_END_ENQUEUE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_END_ENQUEUE) || \
    false)

static inline void trace_xive_end_enqueue(uint8_t end_blk, uint32_t end_idx, uint32_t end_data)
{
    if (trace_event_get_state(TRACE_XIVE_END_ENQUEUE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 295 "../xemu/hw/intc/trace-events"
            qemu_log("xive_end_enqueue " "Queue event for END 0x%x/0x%x data=0x%x" "\n", end_blk, end_idx, end_data);
#line 4526 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_ESCALATE_END_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_ESCALATE_END) || \
    false)

static inline void trace_xive_escalate_end(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint32_t esc_idx, uint32_t esc_data)
{
    if (trace_event_get_state(TRACE_XIVE_ESCALATE_END)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 296 "../xemu/hw/intc/trace-events"
            qemu_log("xive_escalate_end " "Escalate from END 0x%x/0x%x to END 0x%x/0x%x data=0x%x" "\n", end_blk, end_idx, esc_blk, esc_idx, esc_data);
#line 4541 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_XIVE_ESCALATE_ESB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XIVE_ESCALATE_ESB) || \
    false)

static inline void trace_xive_escalate_esb(uint8_t end_blk, uint32_t end_idx, uint32_t lisn)
{
    if (trace_event_get_state(TRACE_XIVE_ESCALATE_ESB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 297 "../xemu/hw/intc/trace-events"
            qemu_log("xive_escalate_esb " "Escalate from END 0x%x/0x%x to LISN=0x%x" "\n", end_blk, end_idx, lisn);
#line 4556 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_PNV_XIVE_IC_HW_TRIGGER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PNV_XIVE_IC_HW_TRIGGER) || \
    false)

static inline void trace_pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_PNV_XIVE_IC_HW_TRIGGER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 300 "../xemu/hw/intc/trace-events"
            qemu_log("pnv_xive_ic_hw_trigger " "@0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 4571 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GOLDFISH_IRQ_REQUEST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_IRQ_REQUEST) || \
    false)

static inline void trace_goldfish_irq_request(void *dev, int idx, int irq, int level)
{
    if (trace_event_get_state(TRACE_GOLDFISH_IRQ_REQUEST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 303 "../xemu/hw/intc/trace-events"
            qemu_log("goldfish_irq_request " "pic: %p goldfish-irq.%d irq: %d level: %d" "\n", dev, idx, irq, level);
#line 4586 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GOLDFISH_PIC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_PIC_READ) || \
    false)

static inline void trace_goldfish_pic_read(void *dev, int idx, unsigned int addr, unsigned int size, uint64_t value)
{
    if (trace_event_get_state(TRACE_GOLDFISH_PIC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 304 "../xemu/hw/intc/trace-events"
            qemu_log("goldfish_pic_read " "pic: %p goldfish-irq.%d reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", dev, idx, addr, size, value);
#line 4601 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GOLDFISH_PIC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_PIC_WRITE) || \
    false)

static inline void trace_goldfish_pic_write(void *dev, int idx, unsigned int addr, unsigned int size, uint64_t value)
{
    if (trace_event_get_state(TRACE_GOLDFISH_PIC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 305 "../xemu/hw/intc/trace-events"
            qemu_log("goldfish_pic_write " "pic: %p goldfish-irq.%d reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", dev, idx, addr, size, value);
#line 4616 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GOLDFISH_PIC_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_PIC_RESET) || \
    false)

static inline void trace_goldfish_pic_reset(void *dev, int idx)
{
    if (trace_event_get_state(TRACE_GOLDFISH_PIC_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 306 "../xemu/hw/intc/trace-events"
            qemu_log("goldfish_pic_reset " "pic: %p goldfish-irq.%d" "\n", dev, idx);
#line 4631 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GOLDFISH_PIC_REALIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_PIC_REALIZE) || \
    false)

static inline void trace_goldfish_pic_realize(void *dev, int idx)
{
    if (trace_event_get_state(TRACE_GOLDFISH_PIC_REALIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 307 "../xemu/hw/intc/trace-events"
            qemu_log("goldfish_pic_realize " "pic: %p goldfish-irq.%d" "\n", dev, idx);
#line 4646 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_GOLDFISH_PIC_INSTANCE_INIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_PIC_INSTANCE_INIT) || \
    false)

static inline void trace_goldfish_pic_instance_init(void *dev)
{
    if (trace_event_get_state(TRACE_GOLDFISH_PIC_INSTANCE_INIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 308 "../xemu/hw/intc/trace-events"
            qemu_log("goldfish_pic_instance_init " "pic: %p goldfish-irq" "\n", dev);
#line 4661 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SH_INTC_SOURCES_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SH_INTC_SOURCES) || \
    false)

static inline void trace_sh_intc_sources(int p, int a, int c, int m, unsigned short v, const char *s1, const char *s2, const char *s3)
{
    if (trace_event_get_state(TRACE_SH_INTC_SOURCES)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 311 "../xemu/hw/intc/trace-events"
            qemu_log("sh_intc_sources " "(%d/%d/%d/%d) interrupt source 0x%x %s%s%s" "\n", p, a, c, m, v, s1, s2, s3);
#line 4676 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SH_INTC_PENDING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SH_INTC_PENDING) || \
    false)

static inline void trace_sh_intc_pending(int p, unsigned short v)
{
    if (trace_event_get_state(TRACE_SH_INTC_PENDING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 312 "../xemu/hw/intc/trace-events"
            qemu_log("sh_intc_pending " "(%d) returning interrupt source 0x%x" "\n", p, v);
#line 4691 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SH_INTC_REGISTER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SH_INTC_REGISTER) || \
    false)

static inline void trace_sh_intc_register(const char *s, int id, unsigned short v, int c, int m)
{
    if (trace_event_get_state(TRACE_SH_INTC_REGISTER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 313 "../xemu/hw/intc/trace-events"
            qemu_log("sh_intc_register " "%s %u -> 0x%04x (%d/%d)" "\n", s, id, v, c, m);
#line 4706 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SH_INTC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SH_INTC_READ) || \
    false)

static inline void trace_sh_intc_read(unsigned size, uint64_t offset, unsigned long val)
{
    if (trace_event_get_state(TRACE_SH_INTC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 314 "../xemu/hw/intc/trace-events"
            qemu_log("sh_intc_read " "size %u 0x%" PRIx64 " -> 0x%lx" "\n", size, offset, val);
#line 4721 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SH_INTC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SH_INTC_WRITE) || \
    false)

static inline void trace_sh_intc_write(unsigned size, uint64_t offset, unsigned long val)
{
    if (trace_event_get_state(TRACE_SH_INTC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 315 "../xemu/hw/intc/trace-events"
            qemu_log("sh_intc_write " "size %u 0x%" PRIx64 " <- 0x%lx" "\n", size, offset, val);
#line 4736 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_SH_INTC_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SH_INTC_SET) || \
    false)

static inline void trace_sh_intc_set(int id, int enable)
{
    if (trace_event_get_state(TRACE_SH_INTC_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 316 "../xemu/hw/intc/trace-events"
            qemu_log("sh_intc_set " "setting interrupt group %d to %d" "\n", id, enable);
#line 4751 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_LOONGSON_IPI_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOONGSON_IPI_READ) || \
    false)

static inline void trace_loongson_ipi_read(unsigned size, uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_LOONGSON_IPI_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 319 "../xemu/hw/intc/trace-events"
            qemu_log("loongson_ipi_read " "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64 "\n", size, addr, val);
#line 4766 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_LOONGSON_IPI_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOONGSON_IPI_WRITE) || \
    false)

static inline void trace_loongson_ipi_write(unsigned size, uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_LOONGSON_IPI_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 320 "../xemu/hw/intc/trace-events"
            qemu_log("loongson_ipi_write " "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64 "\n", size, addr, val);
#line 4781 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_LOONGARCH_PCH_PIC_IRQ_HANDLER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_PCH_PIC_IRQ_HANDLER) || \
    false)

static inline void trace_loongarch_pch_pic_irq_handler(int irq, int level)
{
    if (trace_event_get_state(TRACE_LOONGARCH_PCH_PIC_IRQ_HANDLER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 322 "../xemu/hw/intc/trace-events"
            qemu_log("loongarch_pch_pic_irq_handler " "irq %d level %d" "\n", irq, level);
#line 4796 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_LOONGARCH_PCH_PIC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_PCH_PIC_READ) || \
    false)

static inline void trace_loongarch_pch_pic_read(unsigned size, uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_LOONGARCH_PCH_PIC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 323 "../xemu/hw/intc/trace-events"
            qemu_log("loongarch_pch_pic_read " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", size, addr, val);
#line 4811 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_LOONGARCH_PCH_PIC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_PCH_PIC_WRITE) || \
    false)

static inline void trace_loongarch_pch_pic_write(unsigned size, uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_LOONGARCH_PCH_PIC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 324 "../xemu/hw/intc/trace-events"
            qemu_log("loongarch_pch_pic_write " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", size, addr, val);
#line 4826 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_LOONGARCH_MSI_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_MSI_SET_IRQ) || \
    false)

static inline void trace_loongarch_msi_set_irq(int irq_num)
{
    if (trace_event_get_state(TRACE_LOONGARCH_MSI_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 327 "../xemu/hw/intc/trace-events"
            qemu_log("loongarch_msi_set_irq " "set msi irq %d" "\n", irq_num);
#line 4841 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_LOONGARCH_EXTIOI_SETIRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_EXTIOI_SETIRQ) || \
    false)

static inline void trace_loongarch_extioi_setirq(int irq, int level)
{
    if (trace_event_get_state(TRACE_LOONGARCH_EXTIOI_SETIRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 330 "../xemu/hw/intc/trace-events"
            qemu_log("loongarch_extioi_setirq " "set extirq irq %d level %d" "\n", irq, level);
#line 4856 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_LOONGARCH_EXTIOI_READW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_EXTIOI_READW) || \
    false)

static inline void trace_loongarch_extioi_readw(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_LOONGARCH_EXTIOI_READW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 331 "../xemu/hw/intc/trace-events"
            qemu_log("loongarch_extioi_readw " "addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", addr, val);
#line 4871 "trace/trace-hw_intc.h"
        }
    }
}

#define TRACE_LOONGARCH_EXTIOI_WRITEW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_EXTIOI_WRITEW) || \
    false)

static inline void trace_loongarch_extioi_writew(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_LOONGARCH_EXTIOI_WRITEW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 332 "../xemu/hw/intc/trace-events"
            qemu_log("loongarch_extioi_writew " "addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", addr, val);
#line 4886 "trace/trace-hw_intc.h"
        }
    }
}
#endif /* TRACE_HW_INTC_GENERATED_TRACERS_H */
