/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_HW_DISPLAY_GENERATED_TRACERS_H
#define TRACE_HW_DISPLAY_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_JAZZ_LED_READ_EVENT;
extern TraceEvent _TRACE_JAZZ_LED_WRITE_EVENT;
extern TraceEvent _TRACE_XENFB_MOUSE_EVENT_EVENT;
extern TraceEvent _TRACE_XENFB_KEY_EVENT_EVENT;
extern TraceEvent _TRACE_XENFB_INPUT_CONNECTED_EVENT;
extern TraceEvent _TRACE_G364FB_READ_EVENT;
extern TraceEvent _TRACE_G364FB_WRITE_EVENT;
extern TraceEvent _TRACE_VMWARE_VALUE_READ_EVENT;
extern TraceEvent _TRACE_VMWARE_VALUE_WRITE_EVENT;
extern TraceEvent _TRACE_VMWARE_PALETTE_READ_EVENT;
extern TraceEvent _TRACE_VMWARE_PALETTE_WRITE_EVENT;
extern TraceEvent _TRACE_VMWARE_SCRATCH_READ_EVENT;
extern TraceEvent _TRACE_VMWARE_SCRATCH_WRITE_EVENT;
extern TraceEvent _TRACE_VMWARE_SETMODE_EVENT;
extern TraceEvent _TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_EVENT;
extern TraceEvent _TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_EVENT;
extern TraceEvent _TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_EVENT;
extern TraceEvent _TRACE_VMWARE_UPDATE_RECT_DELAYED_FLUSH_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_FEATURES_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_GET_EDID_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_MAP_BLOB_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_UNMAP_BLOB_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_UNREF_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_FLUSH_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_CREATE_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_UPDATE_CURSOR_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_FENCE_CTRL_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_FENCE_RESP_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_INC_INFLIGHT_FENCES_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_DEC_INFLIGHT_FENCES_EVENT;
extern TraceEvent _TRACE_VIRTIO_GPU_CMD_SUSPENDED_EVENT;
extern TraceEvent _TRACE_QXL_IO_WRITE_VGA_EVENT;
extern TraceEvent _TRACE_QXL_CREATE_GUEST_PRIMARY_EVENT;
extern TraceEvent _TRACE_QXL_CREATE_GUEST_PRIMARY_REST_EVENT;
extern TraceEvent _TRACE_QXL_DESTROY_PRIMARY_EVENT;
extern TraceEvent _TRACE_QXL_ENTER_VGA_MODE_EVENT;
extern TraceEvent _TRACE_QXL_EXIT_VGA_MODE_EVENT;
extern TraceEvent _TRACE_QXL_HARD_RESET_EVENT;
extern TraceEvent _TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_EVENT;
extern TraceEvent _TRACE_QXL_INTERFACE_ATTACH_WORKER_EVENT;
extern TraceEvent _TRACE_QXL_INTERFACE_GET_INIT_INFO_EVENT;
extern TraceEvent _TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_EVENT;
extern TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_EVENT;
extern TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_EVENT;
extern TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_EVENT;
extern TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_EVENT;
extern TraceEvent _TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_EVENT;
extern TraceEvent _TRACE_QXL_IO_LOG_EVENT;
extern TraceEvent _TRACE_QXL_IO_READ_UNEXPECTED_EVENT;
extern TraceEvent _TRACE_QXL_IO_UNEXPECTED_VGA_MODE_EVENT;
extern TraceEvent _TRACE_QXL_IO_WRITE_EVENT;
extern TraceEvent _TRACE_QXL_MEMSLOT_ADD_GUEST_EVENT;
extern TraceEvent _TRACE_QXL_POST_LOAD_EVENT;
extern TraceEvent _TRACE_QXL_PRE_LOAD_EVENT;
extern TraceEvent _TRACE_QXL_PRE_SAVE_EVENT;
extern TraceEvent _TRACE_QXL_RESET_SURFACES_EVENT;
extern TraceEvent _TRACE_QXL_RING_COMMAND_CHECK_EVENT;
extern TraceEvent _TRACE_QXL_RING_COMMAND_GET_EVENT;
extern TraceEvent _TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_EVENT;
extern TraceEvent _TRACE_QXL_RING_CURSOR_CHECK_EVENT;
extern TraceEvent _TRACE_QXL_RING_CURSOR_GET_EVENT;
extern TraceEvent _TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_EVENT;
extern TraceEvent _TRACE_QXL_RING_RES_PUSH_EVENT;
extern TraceEvent _TRACE_QXL_RING_RES_PUSH_REST_EVENT;
extern TraceEvent _TRACE_QXL_RING_RES_PUT_EVENT;
extern TraceEvent _TRACE_QXL_SET_MODE_EVENT;
extern TraceEvent _TRACE_QXL_SOFT_RESET_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACES_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_MONITORS_CONFIG_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_LOADVM_COMMANDS_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_OOM_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_RESET_CURSOR_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_RESET_IMAGE_CACHE_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_RESET_MEMSLOTS_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_UPDATE_AREA_EVENT;
extern TraceEvent _TRACE_QXL_SPICE_UPDATE_AREA_REST_EVENT;
extern TraceEvent _TRACE_QXL_SURFACES_DIRTY_EVENT;
extern TraceEvent _TRACE_QXL_SEND_EVENTS_EVENT;
extern TraceEvent _TRACE_QXL_SEND_EVENTS_VM_STOPPED_EVENT;
extern TraceEvent _TRACE_QXL_SET_GUEST_BUG_EVENT;
extern TraceEvent _TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_EVENT;
extern TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_EVENT;
extern TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_EVENT;
extern TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_EVENT;
extern TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_EVENT;
extern TraceEvent _TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_EVENT;
extern TraceEvent _TRACE_QXL_RENDER_BLIT_EVENT;
extern TraceEvent _TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_EVENT;
extern TraceEvent _TRACE_QXL_RENDER_UPDATE_AREA_DONE_EVENT;
extern TraceEvent _TRACE_VGA_STD_READ_IO_EVENT;
extern TraceEvent _TRACE_VGA_STD_WRITE_IO_EVENT;
extern TraceEvent _TRACE_VGA_VBE_READ_EVENT;
extern TraceEvent _TRACE_VGA_VBE_WRITE_EVENT;
extern TraceEvent _TRACE_VGA_CIRRUS_READ_IO_EVENT;
extern TraceEvent _TRACE_VGA_CIRRUS_WRITE_IO_EVENT;
extern TraceEvent _TRACE_VGA_CIRRUS_WRITE_BLT_EVENT;
extern TraceEvent _TRACE_VGA_CIRRUS_WRITE_GR_EVENT;
extern TraceEvent _TRACE_VGA_CIRRUS_BITBLT_START_EVENT;
extern TraceEvent _TRACE_SII9022_READ_REG_EVENT;
extern TraceEvent _TRACE_SII9022_WRITE_REG_EVENT;
extern TraceEvent _TRACE_SII9022_SWITCH_MODE_EVENT;
extern TraceEvent _TRACE_ATI_MM_READ_EVENT;
extern TraceEvent _TRACE_ATI_MM_WRITE_EVENT;
extern TraceEvent _TRACE_ARTIST_REG_READ_EVENT;
extern TraceEvent _TRACE_ARTIST_REG_WRITE_EVENT;
extern TraceEvent _TRACE_ARTIST_VRAM_READ_EVENT;
extern TraceEvent _TRACE_ARTIST_VRAM_WRITE_EVENT;
extern TraceEvent _TRACE_ARTIST_FILL_WINDOW_EVENT;
extern TraceEvent _TRACE_ARTIST_BLOCK_MOVE_EVENT;
extern TraceEvent _TRACE_ARTIST_DRAW_LINE_EVENT;
extern TraceEvent _TRACE_CG3_READ_EVENT;
extern TraceEvent _TRACE_CG3_WRITE_EVENT;
extern TraceEvent _TRACE_DPCD_READ_EVENT;
extern TraceEvent _TRACE_DPCD_WRITE_EVENT;
extern TraceEvent _TRACE_SM501_SYSTEM_CONFIG_READ_EVENT;
extern TraceEvent _TRACE_SM501_SYSTEM_CONFIG_WRITE_EVENT;
extern TraceEvent _TRACE_SM501_I2C_READ_EVENT;
extern TraceEvent _TRACE_SM501_I2C_WRITE_EVENT;
extern TraceEvent _TRACE_SM501_PALETTE_READ_EVENT;
extern TraceEvent _TRACE_SM501_PALETTE_WRITE_EVENT;
extern TraceEvent _TRACE_SM501_DISP_CTRL_READ_EVENT;
extern TraceEvent _TRACE_SM501_DISP_CTRL_WRITE_EVENT;
extern TraceEvent _TRACE_SM501_2D_ENGINE_READ_EVENT;
extern TraceEvent _TRACE_SM501_2D_ENGINE_WRITE_EVENT;
extern TraceEvent _TRACE_MACFB_CTRL_READ_EVENT;
extern TraceEvent _TRACE_MACFB_CTRL_WRITE_EVENT;
extern TraceEvent _TRACE_MACFB_SENSE_READ_EVENT;
extern TraceEvent _TRACE_MACFB_SENSE_WRITE_EVENT;
extern TraceEvent _TRACE_MACFB_UPDATE_MODE_EVENT;
extern TraceEvent _TRACE_DM163_REDRAW_EVENT;
extern TraceEvent _TRACE_DM163_DCK_EVENT;
extern TraceEvent _TRACE_DM163_EN_B_EVENT;
extern TraceEvent _TRACE_DM163_RST_B_EVENT;
extern TraceEvent _TRACE_DM163_LAT_B_EVENT;
extern TraceEvent _TRACE_DM163_SIN_EVENT;
extern TraceEvent _TRACE_DM163_SELBK_EVENT;
extern TraceEvent _TRACE_DM163_ACTIVATED_ROWS_EVENT;
extern TraceEvent _TRACE_DM163_BITS_PPI_EVENT;
extern TraceEvent _TRACE_DM163_LEDS_EVENT;
extern TraceEvent _TRACE_DM163_CHANNELS_EVENT;
extern TraceEvent _TRACE_DM163_REFRESH_RATE_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_READ_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_WRITE_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_CREATE_TASK_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_DESTROY_TASK_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_MAP_MEMORY_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_MAP_MEMORY_RANGE_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_REMAP_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_UNMAP_MEMORY_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_READ_MEMORY_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_RAISE_IRQ_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_NEW_FRAME_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_MODE_CHANGE_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_CURSOR_SET_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_CURSOR_SHOW_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_CURSOR_MOVE_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_COMMON_INIT_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_COMMON_REALIZE_MODES_PROPERTY_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_DISPLAY_MODE_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_MMIO_IOSFC_READ_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_MMIO_IOSFC_WRITE_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_IOSFC_MAP_MEMORY_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_IOSFC_MAP_MEMORY_NEW_REGION_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_IOSFC_UNMAP_MEMORY_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_IOSFC_UNMAP_MEMORY_REGION_EVENT;
extern TraceEvent _TRACE_APPLE_GFX_IOSFC_RAISE_IRQ_EVENT;
extern uint16_t _TRACE_JAZZ_LED_READ_DSTATE;
extern uint16_t _TRACE_JAZZ_LED_WRITE_DSTATE;
extern uint16_t _TRACE_XENFB_MOUSE_EVENT_DSTATE;
extern uint16_t _TRACE_XENFB_KEY_EVENT_DSTATE;
extern uint16_t _TRACE_XENFB_INPUT_CONNECTED_DSTATE;
extern uint16_t _TRACE_G364FB_READ_DSTATE;
extern uint16_t _TRACE_G364FB_WRITE_DSTATE;
extern uint16_t _TRACE_VMWARE_VALUE_READ_DSTATE;
extern uint16_t _TRACE_VMWARE_VALUE_WRITE_DSTATE;
extern uint16_t _TRACE_VMWARE_PALETTE_READ_DSTATE;
extern uint16_t _TRACE_VMWARE_PALETTE_WRITE_DSTATE;
extern uint16_t _TRACE_VMWARE_SCRATCH_READ_DSTATE;
extern uint16_t _TRACE_VMWARE_SCRATCH_WRITE_DSTATE;
extern uint16_t _TRACE_VMWARE_SETMODE_DSTATE;
extern uint16_t _TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_DSTATE;
extern uint16_t _TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_DSTATE;
extern uint16_t _TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_DSTATE;
extern uint16_t _TRACE_VMWARE_UPDATE_RECT_DELAYED_FLUSH_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_FEATURES_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_GET_EDID_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_MAP_BLOB_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_UNMAP_BLOB_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_UNREF_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_FLUSH_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_CREATE_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_UPDATE_CURSOR_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_FENCE_CTRL_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_FENCE_RESP_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_INC_INFLIGHT_FENCES_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_DEC_INFLIGHT_FENCES_DSTATE;
extern uint16_t _TRACE_VIRTIO_GPU_CMD_SUSPENDED_DSTATE;
extern uint16_t _TRACE_QXL_IO_WRITE_VGA_DSTATE;
extern uint16_t _TRACE_QXL_CREATE_GUEST_PRIMARY_DSTATE;
extern uint16_t _TRACE_QXL_CREATE_GUEST_PRIMARY_REST_DSTATE;
extern uint16_t _TRACE_QXL_DESTROY_PRIMARY_DSTATE;
extern uint16_t _TRACE_QXL_ENTER_VGA_MODE_DSTATE;
extern uint16_t _TRACE_QXL_EXIT_VGA_MODE_DSTATE;
extern uint16_t _TRACE_QXL_HARD_RESET_DSTATE;
extern uint16_t _TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_DSTATE;
extern uint16_t _TRACE_QXL_INTERFACE_ATTACH_WORKER_DSTATE;
extern uint16_t _TRACE_QXL_INTERFACE_GET_INIT_INFO_DSTATE;
extern uint16_t _TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_DSTATE;
extern uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_DSTATE;
extern uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_DSTATE;
extern uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_DSTATE;
extern uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_DSTATE;
extern uint16_t _TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_DSTATE;
extern uint16_t _TRACE_QXL_IO_LOG_DSTATE;
extern uint16_t _TRACE_QXL_IO_READ_UNEXPECTED_DSTATE;
extern uint16_t _TRACE_QXL_IO_UNEXPECTED_VGA_MODE_DSTATE;
extern uint16_t _TRACE_QXL_IO_WRITE_DSTATE;
extern uint16_t _TRACE_QXL_MEMSLOT_ADD_GUEST_DSTATE;
extern uint16_t _TRACE_QXL_POST_LOAD_DSTATE;
extern uint16_t _TRACE_QXL_PRE_LOAD_DSTATE;
extern uint16_t _TRACE_QXL_PRE_SAVE_DSTATE;
extern uint16_t _TRACE_QXL_RESET_SURFACES_DSTATE;
extern uint16_t _TRACE_QXL_RING_COMMAND_CHECK_DSTATE;
extern uint16_t _TRACE_QXL_RING_COMMAND_GET_DSTATE;
extern uint16_t _TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_DSTATE;
extern uint16_t _TRACE_QXL_RING_CURSOR_CHECK_DSTATE;
extern uint16_t _TRACE_QXL_RING_CURSOR_GET_DSTATE;
extern uint16_t _TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_DSTATE;
extern uint16_t _TRACE_QXL_RING_RES_PUSH_DSTATE;
extern uint16_t _TRACE_QXL_RING_RES_PUSH_REST_DSTATE;
extern uint16_t _TRACE_QXL_RING_RES_PUT_DSTATE;
extern uint16_t _TRACE_QXL_SET_MODE_DSTATE;
extern uint16_t _TRACE_QXL_SOFT_RESET_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACES_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_MONITORS_CONFIG_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_LOADVM_COMMANDS_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_OOM_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_RESET_CURSOR_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_RESET_IMAGE_CACHE_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_RESET_MEMSLOTS_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_UPDATE_AREA_DSTATE;
extern uint16_t _TRACE_QXL_SPICE_UPDATE_AREA_REST_DSTATE;
extern uint16_t _TRACE_QXL_SURFACES_DIRTY_DSTATE;
extern uint16_t _TRACE_QXL_SEND_EVENTS_DSTATE;
extern uint16_t _TRACE_QXL_SEND_EVENTS_VM_STOPPED_DSTATE;
extern uint16_t _TRACE_QXL_SET_GUEST_BUG_DSTATE;
extern uint16_t _TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_DSTATE;
extern uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_DSTATE;
extern uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_DSTATE;
extern uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_DSTATE;
extern uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_DSTATE;
extern uint16_t _TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_DSTATE;
extern uint16_t _TRACE_QXL_RENDER_BLIT_DSTATE;
extern uint16_t _TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_DSTATE;
extern uint16_t _TRACE_QXL_RENDER_UPDATE_AREA_DONE_DSTATE;
extern uint16_t _TRACE_VGA_STD_READ_IO_DSTATE;
extern uint16_t _TRACE_VGA_STD_WRITE_IO_DSTATE;
extern uint16_t _TRACE_VGA_VBE_READ_DSTATE;
extern uint16_t _TRACE_VGA_VBE_WRITE_DSTATE;
extern uint16_t _TRACE_VGA_CIRRUS_READ_IO_DSTATE;
extern uint16_t _TRACE_VGA_CIRRUS_WRITE_IO_DSTATE;
extern uint16_t _TRACE_VGA_CIRRUS_WRITE_BLT_DSTATE;
extern uint16_t _TRACE_VGA_CIRRUS_WRITE_GR_DSTATE;
extern uint16_t _TRACE_VGA_CIRRUS_BITBLT_START_DSTATE;
extern uint16_t _TRACE_SII9022_READ_REG_DSTATE;
extern uint16_t _TRACE_SII9022_WRITE_REG_DSTATE;
extern uint16_t _TRACE_SII9022_SWITCH_MODE_DSTATE;
extern uint16_t _TRACE_ATI_MM_READ_DSTATE;
extern uint16_t _TRACE_ATI_MM_WRITE_DSTATE;
extern uint16_t _TRACE_ARTIST_REG_READ_DSTATE;
extern uint16_t _TRACE_ARTIST_REG_WRITE_DSTATE;
extern uint16_t _TRACE_ARTIST_VRAM_READ_DSTATE;
extern uint16_t _TRACE_ARTIST_VRAM_WRITE_DSTATE;
extern uint16_t _TRACE_ARTIST_FILL_WINDOW_DSTATE;
extern uint16_t _TRACE_ARTIST_BLOCK_MOVE_DSTATE;
extern uint16_t _TRACE_ARTIST_DRAW_LINE_DSTATE;
extern uint16_t _TRACE_CG3_READ_DSTATE;
extern uint16_t _TRACE_CG3_WRITE_DSTATE;
extern uint16_t _TRACE_DPCD_READ_DSTATE;
extern uint16_t _TRACE_DPCD_WRITE_DSTATE;
extern uint16_t _TRACE_SM501_SYSTEM_CONFIG_READ_DSTATE;
extern uint16_t _TRACE_SM501_SYSTEM_CONFIG_WRITE_DSTATE;
extern uint16_t _TRACE_SM501_I2C_READ_DSTATE;
extern uint16_t _TRACE_SM501_I2C_WRITE_DSTATE;
extern uint16_t _TRACE_SM501_PALETTE_READ_DSTATE;
extern uint16_t _TRACE_SM501_PALETTE_WRITE_DSTATE;
extern uint16_t _TRACE_SM501_DISP_CTRL_READ_DSTATE;
extern uint16_t _TRACE_SM501_DISP_CTRL_WRITE_DSTATE;
extern uint16_t _TRACE_SM501_2D_ENGINE_READ_DSTATE;
extern uint16_t _TRACE_SM501_2D_ENGINE_WRITE_DSTATE;
extern uint16_t _TRACE_MACFB_CTRL_READ_DSTATE;
extern uint16_t _TRACE_MACFB_CTRL_WRITE_DSTATE;
extern uint16_t _TRACE_MACFB_SENSE_READ_DSTATE;
extern uint16_t _TRACE_MACFB_SENSE_WRITE_DSTATE;
extern uint16_t _TRACE_MACFB_UPDATE_MODE_DSTATE;
extern uint16_t _TRACE_DM163_REDRAW_DSTATE;
extern uint16_t _TRACE_DM163_DCK_DSTATE;
extern uint16_t _TRACE_DM163_EN_B_DSTATE;
extern uint16_t _TRACE_DM163_RST_B_DSTATE;
extern uint16_t _TRACE_DM163_LAT_B_DSTATE;
extern uint16_t _TRACE_DM163_SIN_DSTATE;
extern uint16_t _TRACE_DM163_SELBK_DSTATE;
extern uint16_t _TRACE_DM163_ACTIVATED_ROWS_DSTATE;
extern uint16_t _TRACE_DM163_BITS_PPI_DSTATE;
extern uint16_t _TRACE_DM163_LEDS_DSTATE;
extern uint16_t _TRACE_DM163_CHANNELS_DSTATE;
extern uint16_t _TRACE_DM163_REFRESH_RATE_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_READ_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_WRITE_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_CREATE_TASK_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_DESTROY_TASK_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_MAP_MEMORY_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_MAP_MEMORY_RANGE_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_REMAP_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_UNMAP_MEMORY_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_READ_MEMORY_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_RAISE_IRQ_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_NEW_FRAME_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_MODE_CHANGE_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_CURSOR_SET_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_CURSOR_SHOW_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_CURSOR_MOVE_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_COMMON_INIT_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_COMMON_REALIZE_MODES_PROPERTY_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_DISPLAY_MODE_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_MMIO_IOSFC_READ_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_MMIO_IOSFC_WRITE_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_IOSFC_MAP_MEMORY_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_IOSFC_MAP_MEMORY_NEW_REGION_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_IOSFC_UNMAP_MEMORY_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_IOSFC_UNMAP_MEMORY_REGION_DSTATE;
extern uint16_t _TRACE_APPLE_GFX_IOSFC_RAISE_IRQ_DSTATE;
#define TRACE_JAZZ_LED_READ_ENABLED 1
#define TRACE_JAZZ_LED_WRITE_ENABLED 1
#define TRACE_XENFB_MOUSE_EVENT_ENABLED 1
#define TRACE_XENFB_KEY_EVENT_ENABLED 1
#define TRACE_XENFB_INPUT_CONNECTED_ENABLED 1
#define TRACE_G364FB_READ_ENABLED 1
#define TRACE_G364FB_WRITE_ENABLED 1
#define TRACE_VMWARE_VALUE_READ_ENABLED 1
#define TRACE_VMWARE_VALUE_WRITE_ENABLED 1
#define TRACE_VMWARE_PALETTE_READ_ENABLED 1
#define TRACE_VMWARE_PALETTE_WRITE_ENABLED 1
#define TRACE_VMWARE_SCRATCH_READ_ENABLED 1
#define TRACE_VMWARE_SCRATCH_WRITE_ENABLED 1
#define TRACE_VMWARE_SETMODE_ENABLED 1
#define TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_ENABLED 1
#define TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_ENABLED 1
#define TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_ENABLED 1
#define TRACE_VMWARE_UPDATE_RECT_DELAYED_FLUSH_ENABLED 1
#define TRACE_VIRTIO_GPU_FEATURES_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_GET_EDID_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_RES_MAP_BLOB_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_RES_UNMAP_BLOB_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_RES_UNREF_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_RES_FLUSH_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_CTX_CREATE_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_ENABLED 1
#define TRACE_VIRTIO_GPU_UPDATE_CURSOR_ENABLED 1
#define TRACE_VIRTIO_GPU_FENCE_CTRL_ENABLED 1
#define TRACE_VIRTIO_GPU_FENCE_RESP_ENABLED 1
#define TRACE_VIRTIO_GPU_INC_INFLIGHT_FENCES_ENABLED 1
#define TRACE_VIRTIO_GPU_DEC_INFLIGHT_FENCES_ENABLED 1
#define TRACE_VIRTIO_GPU_CMD_SUSPENDED_ENABLED 1
#define TRACE_QXL_IO_WRITE_VGA_ENABLED 0
#define TRACE_QXL_CREATE_GUEST_PRIMARY_ENABLED 1
#define TRACE_QXL_CREATE_GUEST_PRIMARY_REST_ENABLED 1
#define TRACE_QXL_DESTROY_PRIMARY_ENABLED 1
#define TRACE_QXL_ENTER_VGA_MODE_ENABLED 1
#define TRACE_QXL_EXIT_VGA_MODE_ENABLED 1
#define TRACE_QXL_HARD_RESET_ENABLED 1
#define TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_ENABLED 1
#define TRACE_QXL_INTERFACE_ATTACH_WORKER_ENABLED 1
#define TRACE_QXL_INTERFACE_GET_INIT_INFO_ENABLED 1
#define TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_ENABLED 1
#define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_ENABLED 1
#define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_ENABLED 1
#define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_ENABLED 1
#define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_ENABLED 1
#define TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_ENABLED 1
#define TRACE_QXL_IO_LOG_ENABLED 1
#define TRACE_QXL_IO_READ_UNEXPECTED_ENABLED 1
#define TRACE_QXL_IO_UNEXPECTED_VGA_MODE_ENABLED 1
#define TRACE_QXL_IO_WRITE_ENABLED 1
#define TRACE_QXL_MEMSLOT_ADD_GUEST_ENABLED 1
#define TRACE_QXL_POST_LOAD_ENABLED 1
#define TRACE_QXL_PRE_LOAD_ENABLED 1
#define TRACE_QXL_PRE_SAVE_ENABLED 1
#define TRACE_QXL_RESET_SURFACES_ENABLED 1
#define TRACE_QXL_RING_COMMAND_CHECK_ENABLED 1
#define TRACE_QXL_RING_COMMAND_GET_ENABLED 1
#define TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_ENABLED 1
#define TRACE_QXL_RING_CURSOR_CHECK_ENABLED 1
#define TRACE_QXL_RING_CURSOR_GET_ENABLED 1
#define TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_ENABLED 1
#define TRACE_QXL_RING_RES_PUSH_ENABLED 1
#define TRACE_QXL_RING_RES_PUSH_REST_ENABLED 1
#define TRACE_QXL_RING_RES_PUT_ENABLED 1
#define TRACE_QXL_SET_MODE_ENABLED 1
#define TRACE_QXL_SOFT_RESET_ENABLED 1
#define TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_ENABLED 1
#define TRACE_QXL_SPICE_DESTROY_SURFACES_ENABLED 1
#define TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_ENABLED 1
#define TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_ENABLED 1
#define TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_ENABLED 1
#define TRACE_QXL_SPICE_MONITORS_CONFIG_ENABLED 1
#define TRACE_QXL_SPICE_LOADVM_COMMANDS_ENABLED 1
#define TRACE_QXL_SPICE_OOM_ENABLED 1
#define TRACE_QXL_SPICE_RESET_CURSOR_ENABLED 1
#define TRACE_QXL_SPICE_RESET_IMAGE_CACHE_ENABLED 1
#define TRACE_QXL_SPICE_RESET_MEMSLOTS_ENABLED 1
#define TRACE_QXL_SPICE_UPDATE_AREA_ENABLED 1
#define TRACE_QXL_SPICE_UPDATE_AREA_REST_ENABLED 1
#define TRACE_QXL_SURFACES_DIRTY_ENABLED 1
#define TRACE_QXL_SEND_EVENTS_ENABLED 1
#define TRACE_QXL_SEND_EVENTS_VM_STOPPED_ENABLED 1
#define TRACE_QXL_SET_GUEST_BUG_ENABLED 1
#define TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_ENABLED 1
#define TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_ENABLED 1
#define TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_ENABLED 1
#define TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_ENABLED 1
#define TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_ENABLED 1
#define TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_ENABLED 1
#define TRACE_QXL_RENDER_BLIT_ENABLED 1
#define TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_ENABLED 1
#define TRACE_QXL_RENDER_UPDATE_AREA_DONE_ENABLED 1
#define TRACE_VGA_STD_READ_IO_ENABLED 1
#define TRACE_VGA_STD_WRITE_IO_ENABLED 1
#define TRACE_VGA_VBE_READ_ENABLED 1
#define TRACE_VGA_VBE_WRITE_ENABLED 1
#define TRACE_VGA_CIRRUS_READ_IO_ENABLED 1
#define TRACE_VGA_CIRRUS_WRITE_IO_ENABLED 1
#define TRACE_VGA_CIRRUS_WRITE_BLT_ENABLED 1
#define TRACE_VGA_CIRRUS_WRITE_GR_ENABLED 1
#define TRACE_VGA_CIRRUS_BITBLT_START_ENABLED 1
#define TRACE_SII9022_READ_REG_ENABLED 1
#define TRACE_SII9022_WRITE_REG_ENABLED 1
#define TRACE_SII9022_SWITCH_MODE_ENABLED 1
#define TRACE_ATI_MM_READ_ENABLED 1
#define TRACE_ATI_MM_WRITE_ENABLED 1
#define TRACE_ARTIST_REG_READ_ENABLED 1
#define TRACE_ARTIST_REG_WRITE_ENABLED 1
#define TRACE_ARTIST_VRAM_READ_ENABLED 1
#define TRACE_ARTIST_VRAM_WRITE_ENABLED 1
#define TRACE_ARTIST_FILL_WINDOW_ENABLED 1
#define TRACE_ARTIST_BLOCK_MOVE_ENABLED 1
#define TRACE_ARTIST_DRAW_LINE_ENABLED 1
#define TRACE_CG3_READ_ENABLED 1
#define TRACE_CG3_WRITE_ENABLED 1
#define TRACE_DPCD_READ_ENABLED 1
#define TRACE_DPCD_WRITE_ENABLED 1
#define TRACE_SM501_SYSTEM_CONFIG_READ_ENABLED 1
#define TRACE_SM501_SYSTEM_CONFIG_WRITE_ENABLED 1
#define TRACE_SM501_I2C_READ_ENABLED 1
#define TRACE_SM501_I2C_WRITE_ENABLED 1
#define TRACE_SM501_PALETTE_READ_ENABLED 1
#define TRACE_SM501_PALETTE_WRITE_ENABLED 1
#define TRACE_SM501_DISP_CTRL_READ_ENABLED 1
#define TRACE_SM501_DISP_CTRL_WRITE_ENABLED 1
#define TRACE_SM501_2D_ENGINE_READ_ENABLED 1
#define TRACE_SM501_2D_ENGINE_WRITE_ENABLED 1
#define TRACE_MACFB_CTRL_READ_ENABLED 1
#define TRACE_MACFB_CTRL_WRITE_ENABLED 1
#define TRACE_MACFB_SENSE_READ_ENABLED 1
#define TRACE_MACFB_SENSE_WRITE_ENABLED 1
#define TRACE_MACFB_UPDATE_MODE_ENABLED 1
#define TRACE_DM163_REDRAW_ENABLED 1
#define TRACE_DM163_DCK_ENABLED 1
#define TRACE_DM163_EN_B_ENABLED 1
#define TRACE_DM163_RST_B_ENABLED 1
#define TRACE_DM163_LAT_B_ENABLED 1
#define TRACE_DM163_SIN_ENABLED 1
#define TRACE_DM163_SELBK_ENABLED 1
#define TRACE_DM163_ACTIVATED_ROWS_ENABLED 1
#define TRACE_DM163_BITS_PPI_ENABLED 1
#define TRACE_DM163_LEDS_ENABLED 1
#define TRACE_DM163_CHANNELS_ENABLED 1
#define TRACE_DM163_REFRESH_RATE_ENABLED 1
#define TRACE_APPLE_GFX_READ_ENABLED 1
#define TRACE_APPLE_GFX_WRITE_ENABLED 1
#define TRACE_APPLE_GFX_CREATE_TASK_ENABLED 1
#define TRACE_APPLE_GFX_DESTROY_TASK_ENABLED 1
#define TRACE_APPLE_GFX_MAP_MEMORY_ENABLED 1
#define TRACE_APPLE_GFX_MAP_MEMORY_RANGE_ENABLED 1
#define TRACE_APPLE_GFX_REMAP_ENABLED 1
#define TRACE_APPLE_GFX_UNMAP_MEMORY_ENABLED 1
#define TRACE_APPLE_GFX_READ_MEMORY_ENABLED 1
#define TRACE_APPLE_GFX_RAISE_IRQ_ENABLED 1
#define TRACE_APPLE_GFX_NEW_FRAME_ENABLED 1
#define TRACE_APPLE_GFX_MODE_CHANGE_ENABLED 1
#define TRACE_APPLE_GFX_CURSOR_SET_ENABLED 1
#define TRACE_APPLE_GFX_CURSOR_SHOW_ENABLED 1
#define TRACE_APPLE_GFX_CURSOR_MOVE_ENABLED 1
#define TRACE_APPLE_GFX_COMMON_INIT_ENABLED 1
#define TRACE_APPLE_GFX_COMMON_REALIZE_MODES_PROPERTY_ENABLED 1
#define TRACE_APPLE_GFX_DISPLAY_MODE_ENABLED 1
#define TRACE_APPLE_GFX_MMIO_IOSFC_READ_ENABLED 1
#define TRACE_APPLE_GFX_MMIO_IOSFC_WRITE_ENABLED 1
#define TRACE_APPLE_GFX_IOSFC_MAP_MEMORY_ENABLED 1
#define TRACE_APPLE_GFX_IOSFC_MAP_MEMORY_NEW_REGION_ENABLED 1
#define TRACE_APPLE_GFX_IOSFC_UNMAP_MEMORY_ENABLED 1
#define TRACE_APPLE_GFX_IOSFC_UNMAP_MEMORY_REGION_ENABLED 1
#define TRACE_APPLE_GFX_IOSFC_RAISE_IRQ_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_JAZZ_LED_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_JAZZ_LED_READ) || \
    false)

static inline void trace_jazz_led_read(uint64_t addr, uint8_t val)
{
    if (trace_event_get_state(TRACE_JAZZ_LED_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 4 "../xemu/hw/display/trace-events"
            qemu_log("jazz_led_read " "read addr=0x%"PRIx64": 0x%x" "\n", addr, val);
#line 578 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_JAZZ_LED_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_JAZZ_LED_WRITE) || \
    false)

static inline void trace_jazz_led_write(uint64_t addr, uint8_t new)
{
    if (trace_event_get_state(TRACE_JAZZ_LED_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../xemu/hw/display/trace-events"
            qemu_log("jazz_led_write " "write addr=0x%"PRIx64": 0x%x" "\n", addr, new);
#line 593 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_XENFB_MOUSE_EVENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XENFB_MOUSE_EVENT) || \
    false)

static inline void trace_xenfb_mouse_event(void *opaque, int dx, int dy, int dz, int button_state, int abs_pointer_wanted)
{
    if (trace_event_get_state(TRACE_XENFB_MOUSE_EVENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 8 "../xemu/hw/display/trace-events"
            qemu_log("xenfb_mouse_event " "%p x %d y %d z %d bs 0x%x abs %d" "\n", opaque, dx, dy, dz, button_state, abs_pointer_wanted);
#line 608 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_XENFB_KEY_EVENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XENFB_KEY_EVENT) || \
    false)

static inline void trace_xenfb_key_event(void *opaque, int scancode, int button_state)
{
    if (trace_event_get_state(TRACE_XENFB_KEY_EVENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 9 "../xemu/hw/display/trace-events"
            qemu_log("xenfb_key_event " "%p scancode %d bs 0x%x" "\n", opaque, scancode, button_state);
#line 623 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_XENFB_INPUT_CONNECTED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XENFB_INPUT_CONNECTED) || \
    false)

static inline void trace_xenfb_input_connected(void *xendev, int abs_pointer_wanted)
{
    if (trace_event_get_state(TRACE_XENFB_INPUT_CONNECTED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 10 "../xemu/hw/display/trace-events"
            qemu_log("xenfb_input_connected " "%p abs %d" "\n", xendev, abs_pointer_wanted);
#line 638 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_G364FB_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_G364FB_READ) || \
    false)

static inline void trace_g364fb_read(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_G364FB_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 13 "../xemu/hw/display/trace-events"
            qemu_log("g364fb_read " "read addr=0x%"PRIx64": 0x%x" "\n", addr, val);
#line 653 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_G364FB_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_G364FB_WRITE) || \
    false)

static inline void trace_g364fb_write(uint64_t addr, uint32_t new)
{
    if (trace_event_get_state(TRACE_G364FB_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 14 "../xemu/hw/display/trace-events"
            qemu_log("g364fb_write " "write addr=0x%"PRIx64": 0x%x" "\n", addr, new);
#line 668 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VMWARE_VALUE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VMWARE_VALUE_READ) || \
    false)

static inline void trace_vmware_value_read(uint32_t index, uint32_t value)
{
    if (trace_event_get_state(TRACE_VMWARE_VALUE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 17 "../xemu/hw/display/trace-events"
            qemu_log("vmware_value_read " "index %d, value 0x%x" "\n", index, value);
#line 683 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VMWARE_VALUE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VMWARE_VALUE_WRITE) || \
    false)

static inline void trace_vmware_value_write(uint32_t index, uint32_t value)
{
    if (trace_event_get_state(TRACE_VMWARE_VALUE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 18 "../xemu/hw/display/trace-events"
            qemu_log("vmware_value_write " "index %d, value 0x%x" "\n", index, value);
#line 698 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VMWARE_PALETTE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VMWARE_PALETTE_READ) || \
    false)

static inline void trace_vmware_palette_read(uint32_t index, uint32_t value)
{
    if (trace_event_get_state(TRACE_VMWARE_PALETTE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 19 "../xemu/hw/display/trace-events"
            qemu_log("vmware_palette_read " "index %d, value 0x%x" "\n", index, value);
#line 713 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VMWARE_PALETTE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VMWARE_PALETTE_WRITE) || \
    false)

static inline void trace_vmware_palette_write(uint32_t index, uint32_t value)
{
    if (trace_event_get_state(TRACE_VMWARE_PALETTE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 20 "../xemu/hw/display/trace-events"
            qemu_log("vmware_palette_write " "index %d, value 0x%x" "\n", index, value);
#line 728 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VMWARE_SCRATCH_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VMWARE_SCRATCH_READ) || \
    false)

static inline void trace_vmware_scratch_read(uint32_t index, uint32_t value)
{
    if (trace_event_get_state(TRACE_VMWARE_SCRATCH_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 21 "../xemu/hw/display/trace-events"
            qemu_log("vmware_scratch_read " "index %d, value 0x%x" "\n", index, value);
#line 743 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VMWARE_SCRATCH_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VMWARE_SCRATCH_WRITE) || \
    false)

static inline void trace_vmware_scratch_write(uint32_t index, uint32_t value)
{
    if (trace_event_get_state(TRACE_VMWARE_SCRATCH_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 22 "../xemu/hw/display/trace-events"
            qemu_log("vmware_scratch_write " "index %d, value 0x%x" "\n", index, value);
#line 758 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VMWARE_SETMODE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VMWARE_SETMODE) || \
    false)

static inline void trace_vmware_setmode(uint32_t w, uint32_t h, uint32_t bpp)
{
    if (trace_event_get_state(TRACE_VMWARE_SETMODE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 23 "../xemu/hw/display/trace-events"
            qemu_log("vmware_setmode " "%dx%d @ %d bpp" "\n", w, h, bpp);
#line 773 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO) || \
    false)

static inline void trace_vmware_verify_rect_less_than_zero(const char *name, const char *param, int x)
{
    if (trace_event_get_state(TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 24 "../xemu/hw/display/trace-events"
            qemu_log("vmware_verify_rect_less_than_zero " "%s: %s was < 0 (%d)" "\n", name, param, x);
#line 788 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND) || \
    false)

static inline void trace_vmware_verify_rect_greater_than_bound(const char *name, const char *param, int bound, int x)
{
    if (trace_event_get_state(TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 25 "../xemu/hw/display/trace-events"
            qemu_log("vmware_verify_rect_greater_than_bound " "%s: %s was > %d (%d)" "\n", name, param, bound, x);
#line 803 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED) || \
    false)

static inline void trace_vmware_verify_rect_surface_bound_exceeded(const char *name, const char *component, int bound, const char *param1, int value1, const char *param2, int value2)
{
    if (trace_event_get_state(TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 26 "../xemu/hw/display/trace-events"
            qemu_log("vmware_verify_rect_surface_bound_exceeded " "%s: %s > %d (%s: %d, %s: %d)" "\n", name, component, bound, param1, value1, param2, value2);
#line 818 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VMWARE_UPDATE_RECT_DELAYED_FLUSH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VMWARE_UPDATE_RECT_DELAYED_FLUSH) || \
    false)

static inline void trace_vmware_update_rect_delayed_flush(void)
{
    if (trace_event_get_state(TRACE_VMWARE_UPDATE_RECT_DELAYED_FLUSH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 27 "../xemu/hw/display/trace-events"
            qemu_log("vmware_update_rect_delayed_flush " "display update FIFO full - forcing flush" "\n");
#line 833 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_FEATURES_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_FEATURES) || \
    false)

static inline void trace_virtio_gpu_features(bool virgl)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_FEATURES)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 30 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_features " "virgl %d" "\n", virgl);
#line 848 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO) || \
    false)

static inline void trace_virtio_gpu_cmd_get_display_info(void)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 34 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_get_display_info " "" "\n");
#line 863 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_GET_EDID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_GET_EDID) || \
    false)

static inline void trace_virtio_gpu_cmd_get_edid(uint32_t scanout)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_GET_EDID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 35 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_get_edid " "scanout %d" "\n", scanout);
#line 878 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_SET_SCANOUT) || \
    false)

static inline void trace_virtio_gpu_cmd_set_scanout(uint32_t id, uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_SET_SCANOUT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 36 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_set_scanout " "id %d, res 0x%x, w %d, h %d, x %d, y %d" "\n", id, res, w, h, x, y);
#line 893 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB) || \
    false)

static inline void trace_virtio_gpu_cmd_set_scanout_blob(uint32_t id, uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 37 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_set_scanout_blob " "id %d, res 0x%x, w %d, h %d, x %d, y %d" "\n", id, res, w, h, x, y);
#line 908 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D) || \
    false)

static inline void trace_virtio_gpu_cmd_res_create_2d(uint32_t res, uint32_t fmt, uint32_t w, uint32_t h)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 38 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_res_create_2d " "res 0x%x, fmt 0x%x, w %d, h %d" "\n", res, fmt, w, h);
#line 923 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D) || \
    false)

static inline void trace_virtio_gpu_cmd_res_create_3d(uint32_t res, uint32_t fmt, uint32_t w, uint32_t h, uint32_t d)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 39 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_res_create_3d " "res 0x%x, fmt 0x%x, w %d, h %d, d %d" "\n", res, fmt, w, h, d);
#line 938 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB) || \
    false)

static inline void trace_virtio_gpu_cmd_res_create_blob(uint32_t res, uint64_t size)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 40 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_res_create_blob " "res 0x%x, size %" PRId64 "\n", res, size);
#line 953 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_RES_MAP_BLOB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_MAP_BLOB) || \
    false)

static inline void trace_virtio_gpu_cmd_res_map_blob(uint32_t res, void *vmr, void *mr)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_MAP_BLOB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 41 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_res_map_blob " "res 0x%x, vmr %p, mr %p" "\n", res, vmr, mr);
#line 968 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_RES_UNMAP_BLOB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_UNMAP_BLOB) || \
    false)

static inline void trace_virtio_gpu_cmd_res_unmap_blob(uint32_t res, void *mr, bool finish_unmapping)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_UNMAP_BLOB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 42 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_res_unmap_blob " "res 0x%x, mr %p, finish_unmapping %d" "\n", res, mr, finish_unmapping);
#line 983 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_RES_UNREF_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_UNREF) || \
    false)

static inline void trace_virtio_gpu_cmd_res_unref(uint32_t res)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_UNREF)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 43 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_res_unref " "res 0x%x" "\n", res);
#line 998 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH) || \
    false)

static inline void trace_virtio_gpu_cmd_res_back_attach(uint32_t res)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 44 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_res_back_attach " "res 0x%x" "\n", res);
#line 1013 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH) || \
    false)

static inline void trace_virtio_gpu_cmd_res_back_detach(uint32_t res)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 45 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_res_back_detach " "res 0x%x" "\n", res);
#line 1028 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D) || \
    false)

static inline void trace_virtio_gpu_cmd_res_xfer_toh_2d(uint32_t res)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 46 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_res_xfer_toh_2d " "res 0x%x" "\n", res);
#line 1043 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D) || \
    false)

static inline void trace_virtio_gpu_cmd_res_xfer_toh_3d(uint32_t res)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 47 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_res_xfer_toh_3d " "res 0x%x" "\n", res);
#line 1058 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D) || \
    false)

static inline void trace_virtio_gpu_cmd_res_xfer_fromh_3d(uint32_t res)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 48 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_res_xfer_fromh_3d " "res 0x%x" "\n", res);
#line 1073 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_RES_FLUSH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_FLUSH) || \
    false)

static inline void trace_virtio_gpu_cmd_res_flush(uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_FLUSH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 49 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_res_flush " "res 0x%x, w %d, h %d, x %d, y %d" "\n", res, w, h, x, y);
#line 1088 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_CTX_CREATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_CTX_CREATE) || \
    false)

static inline void trace_virtio_gpu_cmd_ctx_create(uint32_t ctx, const char *name)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_CTX_CREATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 50 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_ctx_create " "ctx 0x%x, name %s" "\n", ctx, name);
#line 1103 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_CTX_DESTROY) || \
    false)

static inline void trace_virtio_gpu_cmd_ctx_destroy(uint32_t ctx)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_CTX_DESTROY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 51 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_ctx_destroy " "ctx 0x%x" "\n", ctx);
#line 1118 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH) || \
    false)

static inline void trace_virtio_gpu_cmd_ctx_res_attach(uint32_t ctx, uint32_t res)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 52 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_ctx_res_attach " "ctx 0x%x, res 0x%x" "\n", ctx, res);
#line 1133 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH) || \
    false)

static inline void trace_virtio_gpu_cmd_ctx_res_detach(uint32_t ctx, uint32_t res)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 53 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_ctx_res_detach " "ctx 0x%x, res 0x%x" "\n", ctx, res);
#line 1148 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT) || \
    false)

static inline void trace_virtio_gpu_cmd_ctx_submit(uint32_t ctx, uint32_t size)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 54 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_ctx_submit " "ctx 0x%x, size %d" "\n", ctx, size);
#line 1163 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_UPDATE_CURSOR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_UPDATE_CURSOR) || \
    false)

static inline void trace_virtio_gpu_update_cursor(uint32_t scanout, uint32_t x, uint32_t y, const char *type, uint32_t res)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_UPDATE_CURSOR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 55 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_update_cursor " "scanout %d, x %d, y %d, %s, res 0x%x" "\n", scanout, x, y, type, res);
#line 1178 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_FENCE_CTRL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_FENCE_CTRL) || \
    false)

static inline void trace_virtio_gpu_fence_ctrl(uint64_t fence, uint32_t type)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_FENCE_CTRL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 56 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_fence_ctrl " "fence 0x%" PRIx64 ", type 0x%x" "\n", fence, type);
#line 1193 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_FENCE_RESP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_FENCE_RESP) || \
    false)

static inline void trace_virtio_gpu_fence_resp(uint64_t fence)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_FENCE_RESP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 57 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_fence_resp " "fence 0x%" PRIx64 "\n", fence);
#line 1208 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_INC_INFLIGHT_FENCES_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_INC_INFLIGHT_FENCES) || \
    false)

static inline void trace_virtio_gpu_inc_inflight_fences(uint32_t inflight)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_INC_INFLIGHT_FENCES)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 58 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_inc_inflight_fences " "in-flight+ %u" "\n", inflight);
#line 1223 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_DEC_INFLIGHT_FENCES_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_DEC_INFLIGHT_FENCES) || \
    false)

static inline void trace_virtio_gpu_dec_inflight_fences(uint32_t inflight)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_DEC_INFLIGHT_FENCES)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 59 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_dec_inflight_fences " "in-flight- %u" "\n", inflight);
#line 1238 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VIRTIO_GPU_CMD_SUSPENDED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_SUSPENDED) || \
    false)

static inline void trace_virtio_gpu_cmd_suspended(uint32_t cmd)
{
    if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_SUSPENDED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 60 "../xemu/hw/display/trace-events"
            qemu_log("virtio_gpu_cmd_suspended " "cmd 0x%x" "\n", cmd);
#line 1253 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_IO_WRITE_VGA_BACKEND_DSTATE() ( \
    false)

static inline void trace_qxl_io_write_vga(int qid, const char *mode, uint32_t addr, uint32_t val)
{
}

#define TRACE_QXL_CREATE_GUEST_PRIMARY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_CREATE_GUEST_PRIMARY) || \
    false)

static inline void trace_qxl_create_guest_primary(int qid, uint32_t width, uint32_t height, uint64_t mem, uint32_t format, uint32_t position)
{
    if (trace_event_get_state(TRACE_QXL_CREATE_GUEST_PRIMARY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 64 "../xemu/hw/display/trace-events"
            qemu_log("qxl_create_guest_primary " "%d %ux%u mem=0x%" PRIx64 " %u,%u" "\n", qid, width, height, mem, format, position);
#line 1275 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_CREATE_GUEST_PRIMARY_REST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_CREATE_GUEST_PRIMARY_REST) || \
    false)

static inline void trace_qxl_create_guest_primary_rest(int qid, int32_t stride, uint32_t type, uint32_t flags)
{
    if (trace_event_get_state(TRACE_QXL_CREATE_GUEST_PRIMARY_REST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 65 "../xemu/hw/display/trace-events"
            qemu_log("qxl_create_guest_primary_rest " "%d %d,%d,%d" "\n", qid, stride, type, flags);
#line 1290 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_DESTROY_PRIMARY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_DESTROY_PRIMARY) || \
    false)

static inline void trace_qxl_destroy_primary(int qid)
{
    if (trace_event_get_state(TRACE_QXL_DESTROY_PRIMARY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 66 "../xemu/hw/display/trace-events"
            qemu_log("qxl_destroy_primary " "%d" "\n", qid);
#line 1305 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_ENTER_VGA_MODE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_ENTER_VGA_MODE) || \
    false)

static inline void trace_qxl_enter_vga_mode(int qid)
{
    if (trace_event_get_state(TRACE_QXL_ENTER_VGA_MODE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 67 "../xemu/hw/display/trace-events"
            qemu_log("qxl_enter_vga_mode " "%d" "\n", qid);
#line 1320 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_EXIT_VGA_MODE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_EXIT_VGA_MODE) || \
    false)

static inline void trace_qxl_exit_vga_mode(int qid)
{
    if (trace_event_get_state(TRACE_QXL_EXIT_VGA_MODE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 68 "../xemu/hw/display/trace-events"
            qemu_log("qxl_exit_vga_mode " "%d" "\n", qid);
#line 1335 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_HARD_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_HARD_RESET) || \
    false)

static inline void trace_qxl_hard_reset(int qid, int64_t loadvm)
{
    if (trace_event_get_state(TRACE_QXL_HARD_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 69 "../xemu/hw/display/trace-events"
            qemu_log("qxl_hard_reset " "%d loadvm=%"PRId64 "\n", qid, loadvm);
#line 1350 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO) || \
    false)

static inline void trace_qxl_interface_async_complete_io(int qid, uint32_t current_async, void *cookie)
{
    if (trace_event_get_state(TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 70 "../xemu/hw/display/trace-events"
            qemu_log("qxl_interface_async_complete_io " "%d current=%d cookie=%p" "\n", qid, current_async, cookie);
#line 1365 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_INTERFACE_ATTACH_WORKER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_ATTACH_WORKER) || \
    false)

static inline void trace_qxl_interface_attach_worker(int qid)
{
    if (trace_event_get_state(TRACE_QXL_INTERFACE_ATTACH_WORKER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 71 "../xemu/hw/display/trace-events"
            qemu_log("qxl_interface_attach_worker " "%d" "\n", qid);
#line 1380 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_INTERFACE_GET_INIT_INFO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_GET_INIT_INFO) || \
    false)

static inline void trace_qxl_interface_get_init_info(int qid)
{
    if (trace_event_get_state(TRACE_QXL_INTERFACE_GET_INIT_INFO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 72 "../xemu/hw/display/trace-events"
            qemu_log("qxl_interface_get_init_info " "%d" "\n", qid);
#line 1395 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL) || \
    false)

static inline void trace_qxl_interface_set_compression_level(int qid, int64_t level)
{
    if (trace_event_get_state(TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 73 "../xemu/hw/display/trace-events"
            qemu_log("qxl_interface_set_compression_level " "%d %"PRId64 "\n", qid, level);
#line 1410 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE) || \
    false)

static inline void trace_qxl_interface_update_area_complete(int qid, uint32_t surface_id, uint32_t dirty_left, uint32_t dirty_right, uint32_t dirty_top, uint32_t dirty_bottom)
{
    if (trace_event_get_state(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 74 "../xemu/hw/display/trace-events"
            qemu_log("qxl_interface_update_area_complete " "%d surface=%d [%d,%d,%d,%d]" "\n", qid, surface_id, dirty_left, dirty_right, dirty_top, dirty_bottom);
#line 1425 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST) || \
    false)

static inline void trace_qxl_interface_update_area_complete_rest(int qid, uint32_t num_updated_rects)
{
    if (trace_event_get_state(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 75 "../xemu/hw/display/trace-events"
            qemu_log("qxl_interface_update_area_complete_rest " "%d #=%d" "\n", qid, num_updated_rects);
#line 1440 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW) || \
    false)

static inline void trace_qxl_interface_update_area_complete_overflow(int qid, int max)
{
    if (trace_event_get_state(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 76 "../xemu/hw/display/trace-events"
            qemu_log("qxl_interface_update_area_complete_overflow " "%d max=%d" "\n", qid, max);
#line 1455 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH) || \
    false)

static inline void trace_qxl_interface_update_area_complete_schedule_bh(int qid, uint32_t num_dirty)
{
    if (trace_event_get_state(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 77 "../xemu/hw/display/trace-events"
            qemu_log("qxl_interface_update_area_complete_schedule_bh " "%d #dirty=%d" "\n", qid, num_dirty);
#line 1470 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED) || \
    false)

static inline void trace_qxl_io_destroy_primary_ignored(int qid, const char *mode)
{
    if (trace_event_get_state(TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 78 "../xemu/hw/display/trace-events"
            qemu_log("qxl_io_destroy_primary_ignored " "%d %s" "\n", qid, mode);
#line 1485 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_IO_LOG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_IO_LOG) || \
    false)

static inline void trace_qxl_io_log(int qid, const char *log_buf)
{
    if (trace_event_get_state(TRACE_QXL_IO_LOG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 79 "../xemu/hw/display/trace-events"
            qemu_log("qxl_io_log " "%d %s" "\n", qid, log_buf);
#line 1500 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_IO_READ_UNEXPECTED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_IO_READ_UNEXPECTED) || \
    false)

static inline void trace_qxl_io_read_unexpected(int qid)
{
    if (trace_event_get_state(TRACE_QXL_IO_READ_UNEXPECTED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 80 "../xemu/hw/display/trace-events"
            qemu_log("qxl_io_read_unexpected " "%d" "\n", qid);
#line 1515 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_IO_UNEXPECTED_VGA_MODE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_IO_UNEXPECTED_VGA_MODE) || \
    false)

static inline void trace_qxl_io_unexpected_vga_mode(int qid, uint64_t addr, uint64_t val, const char *desc)
{
    if (trace_event_get_state(TRACE_QXL_IO_UNEXPECTED_VGA_MODE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 81 "../xemu/hw/display/trace-events"
            qemu_log("qxl_io_unexpected_vga_mode " "%d 0x%"PRIx64"=%"PRIu64" (%s)" "\n", qid, addr, val, desc);
#line 1530 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_IO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_IO_WRITE) || \
    false)

static inline void trace_qxl_io_write(int qid, const char *mode, uint64_t addr, const char *aname, uint64_t val, unsigned size, int async)
{
    if (trace_event_get_state(TRACE_QXL_IO_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 82 "../xemu/hw/display/trace-events"
            qemu_log("qxl_io_write " "%d %s addr=%"PRIu64 " (%s) val=%"PRIu64" size=%u async=%d" "\n", qid, mode, addr, aname, val, size, async);
#line 1545 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_MEMSLOT_ADD_GUEST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_MEMSLOT_ADD_GUEST) || \
    false)

static inline void trace_qxl_memslot_add_guest(int qid, uint32_t slot_id, uint64_t guest_start, uint64_t guest_end)
{
    if (trace_event_get_state(TRACE_QXL_MEMSLOT_ADD_GUEST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 83 "../xemu/hw/display/trace-events"
            qemu_log("qxl_memslot_add_guest " "%d %u: guest phys 0x%"PRIx64 " - 0x%" PRIx64 "\n", qid, slot_id, guest_start, guest_end);
#line 1560 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_POST_LOAD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_POST_LOAD) || \
    false)

static inline void trace_qxl_post_load(int qid, const char *mode)
{
    if (trace_event_get_state(TRACE_QXL_POST_LOAD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 84 "../xemu/hw/display/trace-events"
            qemu_log("qxl_post_load " "%d %s" "\n", qid, mode);
#line 1575 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_PRE_LOAD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_PRE_LOAD) || \
    false)

static inline void trace_qxl_pre_load(int qid)
{
    if (trace_event_get_state(TRACE_QXL_PRE_LOAD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 85 "../xemu/hw/display/trace-events"
            qemu_log("qxl_pre_load " "%d" "\n", qid);
#line 1590 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_PRE_SAVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_PRE_SAVE) || \
    false)

static inline void trace_qxl_pre_save(int qid)
{
    if (trace_event_get_state(TRACE_QXL_PRE_SAVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 86 "../xemu/hw/display/trace-events"
            qemu_log("qxl_pre_save " "%d" "\n", qid);
#line 1605 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RESET_SURFACES_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RESET_SURFACES) || \
    false)

static inline void trace_qxl_reset_surfaces(int qid)
{
    if (trace_event_get_state(TRACE_QXL_RESET_SURFACES)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 87 "../xemu/hw/display/trace-events"
            qemu_log("qxl_reset_surfaces " "%d" "\n", qid);
#line 1620 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RING_COMMAND_CHECK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_COMMAND_CHECK) || \
    false)

static inline void trace_qxl_ring_command_check(int qid, const char *mode)
{
    if (trace_event_get_state(TRACE_QXL_RING_COMMAND_CHECK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 88 "../xemu/hw/display/trace-events"
            qemu_log("qxl_ring_command_check " "%d %s" "\n", qid, mode);
#line 1635 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RING_COMMAND_GET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_COMMAND_GET) || \
    false)

static inline void trace_qxl_ring_command_get(int qid, const char *mode)
{
    if (trace_event_get_state(TRACE_QXL_RING_COMMAND_GET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 89 "../xemu/hw/display/trace-events"
            qemu_log("qxl_ring_command_get " "%d %s" "\n", qid, mode);
#line 1650 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION) || \
    false)

static inline void trace_qxl_ring_command_req_notification(int qid)
{
    if (trace_event_get_state(TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 90 "../xemu/hw/display/trace-events"
            qemu_log("qxl_ring_command_req_notification " "%d" "\n", qid);
#line 1665 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RING_CURSOR_CHECK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_CURSOR_CHECK) || \
    false)

static inline void trace_qxl_ring_cursor_check(int qid, const char *mode)
{
    if (trace_event_get_state(TRACE_QXL_RING_CURSOR_CHECK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 91 "../xemu/hw/display/trace-events"
            qemu_log("qxl_ring_cursor_check " "%d %s" "\n", qid, mode);
#line 1680 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RING_CURSOR_GET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_CURSOR_GET) || \
    false)

static inline void trace_qxl_ring_cursor_get(int qid, const char *mode)
{
    if (trace_event_get_state(TRACE_QXL_RING_CURSOR_GET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 92 "../xemu/hw/display/trace-events"
            qemu_log("qxl_ring_cursor_get " "%d %s" "\n", qid, mode);
#line 1695 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION) || \
    false)

static inline void trace_qxl_ring_cursor_req_notification(int qid)
{
    if (trace_event_get_state(TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 93 "../xemu/hw/display/trace-events"
            qemu_log("qxl_ring_cursor_req_notification " "%d" "\n", qid);
#line 1710 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RING_RES_PUSH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_RES_PUSH) || \
    false)

static inline void trace_qxl_ring_res_push(int qid, const char *mode, uint32_t surface_count, uint32_t free_res, void *last_release, const char *notify)
{
    if (trace_event_get_state(TRACE_QXL_RING_RES_PUSH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 94 "../xemu/hw/display/trace-events"
            qemu_log("qxl_ring_res_push " "%d %s s#=%d res#=%d last=%p notify=%s" "\n", qid, mode, surface_count, free_res, last_release, notify);
#line 1725 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RING_RES_PUSH_REST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_RES_PUSH_REST) || \
    false)

static inline void trace_qxl_ring_res_push_rest(int qid, uint32_t ring_has, uint32_t ring_size, uint32_t prod, uint32_t cons)
{
    if (trace_event_get_state(TRACE_QXL_RING_RES_PUSH_REST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 95 "../xemu/hw/display/trace-events"
            qemu_log("qxl_ring_res_push_rest " "%d ring %d/%d [%d,%d]" "\n", qid, ring_has, ring_size, prod, cons);
#line 1740 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RING_RES_PUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_RES_PUT) || \
    false)

static inline void trace_qxl_ring_res_put(int qid, uint32_t free_res)
{
    if (trace_event_get_state(TRACE_QXL_RING_RES_PUT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 96 "../xemu/hw/display/trace-events"
            qemu_log("qxl_ring_res_put " "%d #res=%d" "\n", qid, free_res);
#line 1755 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SET_MODE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SET_MODE) || \
    false)

static inline void trace_qxl_set_mode(int qid, int modenr, uint32_t x_res, uint32_t y_res, uint32_t bits, uint64_t devmem)
{
    if (trace_event_get_state(TRACE_QXL_SET_MODE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 97 "../xemu/hw/display/trace-events"
            qemu_log("qxl_set_mode " "%d mode=%d [ x=%d y=%d @ bpp=%d devmem=0x%" PRIx64 " ]" "\n", qid, modenr, x_res, y_res, bits, devmem);
#line 1770 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SOFT_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SOFT_RESET) || \
    false)

static inline void trace_qxl_soft_reset(int qid)
{
    if (trace_event_get_state(TRACE_QXL_SOFT_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 98 "../xemu/hw/display/trace-events"
            qemu_log("qxl_soft_reset " "%d" "\n", qid);
#line 1785 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE) || \
    false)

static inline void trace_qxl_spice_destroy_surfaces_complete(int qid)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 99 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_destroy_surfaces_complete " "%d" "\n", qid);
#line 1800 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_DESTROY_SURFACES_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_DESTROY_SURFACES) || \
    false)

static inline void trace_qxl_spice_destroy_surfaces(int qid, int async)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_DESTROY_SURFACES)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 100 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_destroy_surfaces " "%d async=%d" "\n", qid, async);
#line 1815 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE) || \
    false)

static inline void trace_qxl_spice_destroy_surface_wait_complete(int qid, uint32_t id)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 101 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_destroy_surface_wait_complete " "%d sid=%d" "\n", qid, id);
#line 1830 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT) || \
    false)

static inline void trace_qxl_spice_destroy_surface_wait(int qid, uint32_t id, int async)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 102 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_destroy_surface_wait " "%d sid=%d async=%d" "\n", qid, id, async);
#line 1845 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC) || \
    false)

static inline void trace_qxl_spice_flush_surfaces_async(int qid, uint32_t surface_count, uint32_t num_free_res)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 103 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_flush_surfaces_async " "%d s#=%d, res#=%d" "\n", qid, surface_count, num_free_res);
#line 1860 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_MONITORS_CONFIG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_MONITORS_CONFIG) || \
    false)

static inline void trace_qxl_spice_monitors_config(int qid)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_MONITORS_CONFIG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 104 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_monitors_config " "%d" "\n", qid);
#line 1875 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_LOADVM_COMMANDS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_LOADVM_COMMANDS) || \
    false)

static inline void trace_qxl_spice_loadvm_commands(int qid, void *ext, uint32_t count)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_LOADVM_COMMANDS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 105 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_loadvm_commands " "%d ext=%p count=%d" "\n", qid, ext, count);
#line 1890 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_OOM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_OOM) || \
    false)

static inline void trace_qxl_spice_oom(int qid)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_OOM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 106 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_oom " "%d" "\n", qid);
#line 1905 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_RESET_CURSOR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_RESET_CURSOR) || \
    false)

static inline void trace_qxl_spice_reset_cursor(int qid)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_RESET_CURSOR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 107 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_reset_cursor " "%d" "\n", qid);
#line 1920 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_RESET_IMAGE_CACHE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_RESET_IMAGE_CACHE) || \
    false)

static inline void trace_qxl_spice_reset_image_cache(int qid)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_RESET_IMAGE_CACHE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 108 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_reset_image_cache " "%d" "\n", qid);
#line 1935 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_RESET_MEMSLOTS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_RESET_MEMSLOTS) || \
    false)

static inline void trace_qxl_spice_reset_memslots(int qid)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_RESET_MEMSLOTS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 109 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_reset_memslots " "%d" "\n", qid);
#line 1950 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_UPDATE_AREA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_UPDATE_AREA) || \
    false)

static inline void trace_qxl_spice_update_area(int qid, uint32_t surface_id, uint32_t left, uint32_t right, uint32_t top, uint32_t bottom)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_UPDATE_AREA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 110 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_update_area " "%d sid=%d [%d,%d,%d,%d]" "\n", qid, surface_id, left, right, top, bottom);
#line 1965 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SPICE_UPDATE_AREA_REST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_UPDATE_AREA_REST) || \
    false)

static inline void trace_qxl_spice_update_area_rest(int qid, uint32_t num_dirty_rects, uint32_t clear_dirty_region)
{
    if (trace_event_get_state(TRACE_QXL_SPICE_UPDATE_AREA_REST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 111 "../xemu/hw/display/trace-events"
            qemu_log("qxl_spice_update_area_rest " "%d #d=%d clear=%d" "\n", qid, num_dirty_rects, clear_dirty_region);
#line 1980 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SURFACES_DIRTY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SURFACES_DIRTY) || \
    false)

static inline void trace_qxl_surfaces_dirty(int qid, uint64_t offset, uint64_t size)
{
    if (trace_event_get_state(TRACE_QXL_SURFACES_DIRTY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 112 "../xemu/hw/display/trace-events"
            qemu_log("qxl_surfaces_dirty " "%d offset=0x%"PRIx64" size=0x%"PRIx64 "\n", qid, offset, size);
#line 1995 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SEND_EVENTS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SEND_EVENTS) || \
    false)

static inline void trace_qxl_send_events(int qid, uint32_t events)
{
    if (trace_event_get_state(TRACE_QXL_SEND_EVENTS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 113 "../xemu/hw/display/trace-events"
            qemu_log("qxl_send_events " "%d %d" "\n", qid, events);
#line 2010 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SEND_EVENTS_VM_STOPPED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SEND_EVENTS_VM_STOPPED) || \
    false)

static inline void trace_qxl_send_events_vm_stopped(int qid, uint32_t events)
{
    if (trace_event_get_state(TRACE_QXL_SEND_EVENTS_VM_STOPPED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 114 "../xemu/hw/display/trace-events"
            qemu_log("qxl_send_events_vm_stopped " "%d %d" "\n", qid, events);
#line 2025 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SET_GUEST_BUG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SET_GUEST_BUG) || \
    false)

static inline void trace_qxl_set_guest_bug(int qid)
{
    if (trace_event_get_state(TRACE_QXL_SET_GUEST_BUG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 115 "../xemu/hw/display/trace-events"
            qemu_log("qxl_set_guest_bug " "%d" "\n", qid);
#line 2040 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG) || \
    false)

static inline void trace_qxl_interrupt_client_monitors_config(int qid, int num_heads, void *heads)
{
    if (trace_event_get_state(TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 116 "../xemu/hw/display/trace-events"
            qemu_log("qxl_interrupt_client_monitors_config " "%d %d %p" "\n", qid, num_heads, heads);
#line 2055 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST) || \
    false)

static inline void trace_qxl_client_monitors_config_unsupported_by_guest(int qid, uint32_t int_mask, void *client_monitors_config)
{
    if (trace_event_get_state(TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 117 "../xemu/hw/display/trace-events"
            qemu_log("qxl_client_monitors_config_unsupported_by_guest " "%d 0x%X %p" "\n", qid, int_mask, client_monitors_config);
#line 2070 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE) || \
    false)

static inline void trace_qxl_client_monitors_config_unsupported_by_device(int qid, int revision)
{
    if (trace_event_get_state(TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 118 "../xemu/hw/display/trace-events"
            qemu_log("qxl_client_monitors_config_unsupported_by_device " "%d revision=%d" "\n", qid, revision);
#line 2085 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED) || \
    false)

static inline void trace_qxl_client_monitors_config_capped(int qid, int requested, int limit)
{
    if (trace_event_get_state(TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 119 "../xemu/hw/display/trace-events"
            qemu_log("qxl_client_monitors_config_capped " "%d %d %d" "\n", qid, requested, limit);
#line 2100 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC) || \
    false)

static inline void trace_qxl_client_monitors_config_crc(int qid, unsigned size, uint32_t crc32)
{
    if (trace_event_get_state(TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 120 "../xemu/hw/display/trace-events"
            qemu_log("qxl_client_monitors_config_crc " "%d %u %u" "\n", qid, size, crc32);
#line 2115 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION) || \
    false)

static inline void trace_qxl_set_client_capabilities_unsupported_by_revision(int qid, int revision)
{
    if (trace_event_get_state(TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 121 "../xemu/hw/display/trace-events"
            qemu_log("qxl_set_client_capabilities_unsupported_by_revision " "%d revision=%d" "\n", qid, revision);
#line 2130 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RENDER_BLIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RENDER_BLIT) || \
    false)

static inline void trace_qxl_render_blit(int32_t stride, int32_t left, int32_t right, int32_t top, int32_t bottom)
{
    if (trace_event_get_state(TRACE_QXL_RENDER_BLIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 124 "../xemu/hw/display/trace-events"
            qemu_log("qxl_render_blit " "stride=%d [%d, %d, %d, %d]" "\n", stride, left, right, top, bottom);
#line 2145 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED) || \
    false)

static inline void trace_qxl_render_guest_primary_resized(int32_t width, int32_t height, int32_t stride, int32_t bytes_pp, int32_t bits_pp)
{
    if (trace_event_get_state(TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 125 "../xemu/hw/display/trace-events"
            qemu_log("qxl_render_guest_primary_resized " "%dx%d, stride %d, bpp %d, depth %d" "\n", width, height, stride, bytes_pp, bits_pp);
#line 2160 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_QXL_RENDER_UPDATE_AREA_DONE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QXL_RENDER_UPDATE_AREA_DONE) || \
    false)

static inline void trace_qxl_render_update_area_done(void *cookie)
{
    if (trace_event_get_state(TRACE_QXL_RENDER_UPDATE_AREA_DONE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 126 "../xemu/hw/display/trace-events"
            qemu_log("qxl_render_update_area_done " "%p" "\n", cookie);
#line 2175 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VGA_STD_READ_IO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VGA_STD_READ_IO) || \
    false)

static inline void trace_vga_std_read_io(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_VGA_STD_READ_IO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 129 "../xemu/hw/display/trace-events"
            qemu_log("vga_std_read_io " "addr 0x%x, val 0x%x" "\n", addr, val);
#line 2190 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VGA_STD_WRITE_IO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VGA_STD_WRITE_IO) || \
    false)

static inline void trace_vga_std_write_io(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_VGA_STD_WRITE_IO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 130 "../xemu/hw/display/trace-events"
            qemu_log("vga_std_write_io " "addr 0x%x, val 0x%x" "\n", addr, val);
#line 2205 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VGA_VBE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VGA_VBE_READ) || \
    false)

static inline void trace_vga_vbe_read(uint32_t index, uint32_t val)
{
    if (trace_event_get_state(TRACE_VGA_VBE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 131 "../xemu/hw/display/trace-events"
            qemu_log("vga_vbe_read " "index 0x%x, val 0x%x" "\n", index, val);
#line 2220 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VGA_VBE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VGA_VBE_WRITE) || \
    false)

static inline void trace_vga_vbe_write(uint32_t index, uint32_t val)
{
    if (trace_event_get_state(TRACE_VGA_VBE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 132 "../xemu/hw/display/trace-events"
            qemu_log("vga_vbe_write " "index 0x%x, val 0x%x" "\n", index, val);
#line 2235 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VGA_CIRRUS_READ_IO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VGA_CIRRUS_READ_IO) || \
    false)

static inline void trace_vga_cirrus_read_io(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_VGA_CIRRUS_READ_IO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 135 "../xemu/hw/display/trace-events"
            qemu_log("vga_cirrus_read_io " "addr 0x%x, val 0x%x" "\n", addr, val);
#line 2250 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VGA_CIRRUS_WRITE_IO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VGA_CIRRUS_WRITE_IO) || \
    false)

static inline void trace_vga_cirrus_write_io(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_VGA_CIRRUS_WRITE_IO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 136 "../xemu/hw/display/trace-events"
            qemu_log("vga_cirrus_write_io " "addr 0x%x, val 0x%x" "\n", addr, val);
#line 2265 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VGA_CIRRUS_WRITE_BLT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VGA_CIRRUS_WRITE_BLT) || \
    false)

static inline void trace_vga_cirrus_write_blt(uint32_t offset, uint32_t val)
{
    if (trace_event_get_state(TRACE_VGA_CIRRUS_WRITE_BLT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 137 "../xemu/hw/display/trace-events"
            qemu_log("vga_cirrus_write_blt " "offset 0x%x, val 0x%x" "\n", offset, val);
#line 2280 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VGA_CIRRUS_WRITE_GR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VGA_CIRRUS_WRITE_GR) || \
    false)

static inline void trace_vga_cirrus_write_gr(uint8_t index, uint8_t val)
{
    if (trace_event_get_state(TRACE_VGA_CIRRUS_WRITE_GR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 138 "../xemu/hw/display/trace-events"
            qemu_log("vga_cirrus_write_gr " "GR addr 0x%02x, val 0x%02x" "\n", index, val);
#line 2295 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_VGA_CIRRUS_BITBLT_START_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VGA_CIRRUS_BITBLT_START) || \
    false)

static inline void trace_vga_cirrus_bitblt_start(uint8_t blt_rop, uint8_t blt_mode, uint8_t blt_modeext, int blt_width, int blt_height, int blt_dstpitch, int blt_srcpitch, uint32_t blt_dstaddr, uint32_t blt_srcaddr, uint8_t gr_val)
{
    if (trace_event_get_state(TRACE_VGA_CIRRUS_BITBLT_START)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 139 "../xemu/hw/display/trace-events"
            qemu_log("vga_cirrus_bitblt_start " "rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08"PRIx32" saddr=0x%08"PRIx32" writemask=0x%02x" "\n", blt_rop, blt_mode, blt_modeext, blt_width, blt_height, blt_dstpitch, blt_srcpitch, blt_dstaddr, blt_srcaddr, gr_val);
#line 2310 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SII9022_READ_REG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SII9022_READ_REG) || \
    false)

static inline void trace_sii9022_read_reg(uint8_t addr, uint8_t val)
{
    if (trace_event_get_state(TRACE_SII9022_READ_REG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 142 "../xemu/hw/display/trace-events"
            qemu_log("sii9022_read_reg " "addr 0x%02x, val 0x%02x" "\n", addr, val);
#line 2325 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SII9022_WRITE_REG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SII9022_WRITE_REG) || \
    false)

static inline void trace_sii9022_write_reg(uint8_t addr, uint8_t val)
{
    if (trace_event_get_state(TRACE_SII9022_WRITE_REG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 143 "../xemu/hw/display/trace-events"
            qemu_log("sii9022_write_reg " "addr 0x%02x, val 0x%02x" "\n", addr, val);
#line 2340 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SII9022_SWITCH_MODE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SII9022_SWITCH_MODE) || \
    false)

static inline void trace_sii9022_switch_mode(const char *mode)
{
    if (trace_event_get_state(TRACE_SII9022_SWITCH_MODE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 144 "../xemu/hw/display/trace-events"
            qemu_log("sii9022_switch_mode " "mode: %s" "\n", mode);
#line 2355 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_ATI_MM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ATI_MM_READ) || \
    false)

static inline void trace_ati_mm_read(unsigned int size, uint64_t addr, const char *name, uint64_t val)
{
    if (trace_event_get_state(TRACE_ATI_MM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 147 "../xemu/hw/display/trace-events"
            qemu_log("ati_mm_read " "%u 0x%"PRIx64 " %s -> 0x%"PRIx64 "\n", size, addr, name, val);
#line 2370 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_ATI_MM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ATI_MM_WRITE) || \
    false)

static inline void trace_ati_mm_write(unsigned int size, uint64_t addr, const char *name, uint64_t val)
{
    if (trace_event_get_state(TRACE_ATI_MM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 148 "../xemu/hw/display/trace-events"
            qemu_log("ati_mm_write " "%u 0x%"PRIx64 " %s <- 0x%"PRIx64 "\n", size, addr, name, val);
#line 2385 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_ARTIST_REG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARTIST_REG_READ) || \
    false)

static inline void trace_artist_reg_read(unsigned int size, uint64_t addr, const char *name, uint64_t val)
{
    if (trace_event_get_state(TRACE_ARTIST_REG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 151 "../xemu/hw/display/trace-events"
            qemu_log("artist_reg_read " "%u 0x%"PRIx64 "%s -> 0x%08"PRIx64 "\n", size, addr, name, val);
#line 2400 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_ARTIST_REG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARTIST_REG_WRITE) || \
    false)

static inline void trace_artist_reg_write(unsigned int size, uint64_t addr, const char *name, uint64_t val)
{
    if (trace_event_get_state(TRACE_ARTIST_REG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 152 "../xemu/hw/display/trace-events"
            qemu_log("artist_reg_write " "%u 0x%"PRIx64 "%s <- 0x%08"PRIx64 "\n", size, addr, name, val);
#line 2415 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_ARTIST_VRAM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARTIST_VRAM_READ) || \
    false)

static inline void trace_artist_vram_read(unsigned int size, uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_ARTIST_VRAM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 153 "../xemu/hw/display/trace-events"
            qemu_log("artist_vram_read " "%u 0x%08"PRIx64 " -> 0x%08"PRIx64 "\n", size, addr, val);
#line 2430 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_ARTIST_VRAM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARTIST_VRAM_WRITE) || \
    false)

static inline void trace_artist_vram_write(unsigned int size, uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_ARTIST_VRAM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 154 "../xemu/hw/display/trace-events"
            qemu_log("artist_vram_write " "%u 0x%08"PRIx64 " <- 0x%08"PRIx64 "\n", size, addr, val);
#line 2445 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_ARTIST_FILL_WINDOW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARTIST_FILL_WINDOW) || \
    false)

static inline void trace_artist_fill_window(unsigned int start_x, unsigned int start_y, unsigned int width, unsigned int height, uint32_t op, uint32_t ctlpln)
{
    if (trace_event_get_state(TRACE_ARTIST_FILL_WINDOW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 155 "../xemu/hw/display/trace-events"
            qemu_log("artist_fill_window " "start=%ux%u length=%ux%u op=0x%08x ctlpln=0x%08x" "\n", start_x, start_y, width, height, op, ctlpln);
#line 2460 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_ARTIST_BLOCK_MOVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARTIST_BLOCK_MOVE) || \
    false)

static inline void trace_artist_block_move(unsigned int start_x, unsigned int start_y, unsigned int dest_x, unsigned int dest_y, unsigned int width, unsigned int height)
{
    if (trace_event_get_state(TRACE_ARTIST_BLOCK_MOVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 156 "../xemu/hw/display/trace-events"
            qemu_log("artist_block_move " "source %ux%u -> dest %ux%u size %ux%u" "\n", start_x, start_y, dest_x, dest_y, width, height);
#line 2475 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_ARTIST_DRAW_LINE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARTIST_DRAW_LINE) || \
    false)

static inline void trace_artist_draw_line(unsigned int start_x, unsigned int start_y, unsigned int end_x, unsigned int end_y)
{
    if (trace_event_get_state(TRACE_ARTIST_DRAW_LINE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 157 "../xemu/hw/display/trace-events"
            qemu_log("artist_draw_line " "%ux%u %ux%u" "\n", start_x, start_y, end_x, end_y);
#line 2490 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_CG3_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CG3_READ) || \
    false)

static inline void trace_cg3_read(uint32_t addr, uint32_t val, unsigned size)
{
    if (trace_event_get_state(TRACE_CG3_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 160 "../xemu/hw/display/trace-events"
            qemu_log("cg3_read " "read addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u" "\n", addr, val, size);
#line 2505 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_CG3_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CG3_WRITE) || \
    false)

static inline void trace_cg3_write(uint32_t addr, uint32_t val, unsigned size)
{
    if (trace_event_get_state(TRACE_CG3_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 161 "../xemu/hw/display/trace-events"
            qemu_log("cg3_write " "write addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u" "\n", addr, val, size);
#line 2520 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DPCD_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DPCD_READ) || \
    false)

static inline void trace_dpcd_read(uint32_t addr, uint8_t val)
{
    if (trace_event_get_state(TRACE_DPCD_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 164 "../xemu/hw/display/trace-events"
            qemu_log("dpcd_read " "read addr:0x%"PRIx32" val:0x%02x" "\n", addr, val);
#line 2535 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DPCD_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DPCD_WRITE) || \
    false)

static inline void trace_dpcd_write(uint32_t addr, uint8_t val)
{
    if (trace_event_get_state(TRACE_DPCD_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 165 "../xemu/hw/display/trace-events"
            qemu_log("dpcd_write " "write addr:0x%"PRIx32" val:0x%02x" "\n", addr, val);
#line 2550 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SM501_SYSTEM_CONFIG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SM501_SYSTEM_CONFIG_READ) || \
    false)

static inline void trace_sm501_system_config_read(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_SM501_SYSTEM_CONFIG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 168 "../xemu/hw/display/trace-events"
            qemu_log("sm501_system_config_read " "addr=0x%x, val=0x%x" "\n", addr, val);
#line 2565 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SM501_SYSTEM_CONFIG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SM501_SYSTEM_CONFIG_WRITE) || \
    false)

static inline void trace_sm501_system_config_write(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_SM501_SYSTEM_CONFIG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 169 "../xemu/hw/display/trace-events"
            qemu_log("sm501_system_config_write " "addr=0x%x, val=0x%x" "\n", addr, val);
#line 2580 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SM501_I2C_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SM501_I2C_READ) || \
    false)

static inline void trace_sm501_i2c_read(uint32_t addr, uint8_t val)
{
    if (trace_event_get_state(TRACE_SM501_I2C_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 170 "../xemu/hw/display/trace-events"
            qemu_log("sm501_i2c_read " "addr=0x%x, val=0x%x" "\n", addr, val);
#line 2595 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SM501_I2C_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SM501_I2C_WRITE) || \
    false)

static inline void trace_sm501_i2c_write(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_SM501_I2C_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 171 "../xemu/hw/display/trace-events"
            qemu_log("sm501_i2c_write " "addr=0x%x, val=0x%x" "\n", addr, val);
#line 2610 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SM501_PALETTE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SM501_PALETTE_READ) || \
    false)

static inline void trace_sm501_palette_read(uint32_t addr)
{
    if (trace_event_get_state(TRACE_SM501_PALETTE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 172 "../xemu/hw/display/trace-events"
            qemu_log("sm501_palette_read " "addr=0x%x" "\n", addr);
#line 2625 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SM501_PALETTE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SM501_PALETTE_WRITE) || \
    false)

static inline void trace_sm501_palette_write(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_SM501_PALETTE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 173 "../xemu/hw/display/trace-events"
            qemu_log("sm501_palette_write " "addr=0x%x, val=0x%x" "\n", addr, val);
#line 2640 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SM501_DISP_CTRL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SM501_DISP_CTRL_READ) || \
    false)

static inline void trace_sm501_disp_ctrl_read(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_SM501_DISP_CTRL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 174 "../xemu/hw/display/trace-events"
            qemu_log("sm501_disp_ctrl_read " "addr=0x%x, val=0x%x" "\n", addr, val);
#line 2655 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SM501_DISP_CTRL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SM501_DISP_CTRL_WRITE) || \
    false)

static inline void trace_sm501_disp_ctrl_write(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_SM501_DISP_CTRL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 175 "../xemu/hw/display/trace-events"
            qemu_log("sm501_disp_ctrl_write " "addr=0x%x, val=0x%x" "\n", addr, val);
#line 2670 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SM501_2D_ENGINE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SM501_2D_ENGINE_READ) || \
    false)

static inline void trace_sm501_2d_engine_read(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_SM501_2D_ENGINE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 176 "../xemu/hw/display/trace-events"
            qemu_log("sm501_2d_engine_read " "addr=0x%x, val=0x%x" "\n", addr, val);
#line 2685 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_SM501_2D_ENGINE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SM501_2D_ENGINE_WRITE) || \
    false)

static inline void trace_sm501_2d_engine_write(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_SM501_2D_ENGINE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 177 "../xemu/hw/display/trace-events"
            qemu_log("sm501_2d_engine_write " "addr=0x%x, val=0x%x" "\n", addr, val);
#line 2700 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_MACFB_CTRL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MACFB_CTRL_READ) || \
    false)

static inline void trace_macfb_ctrl_read(uint64_t addr, uint64_t value, unsigned int size)
{
    if (trace_event_get_state(TRACE_MACFB_CTRL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 180 "../xemu/hw/display/trace-events"
            qemu_log("macfb_ctrl_read " "addr 0x%"PRIx64 " value 0x%"PRIx64 " size %u" "\n", addr, value, size);
#line 2715 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_MACFB_CTRL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MACFB_CTRL_WRITE) || \
    false)

static inline void trace_macfb_ctrl_write(uint64_t addr, uint64_t value, unsigned int size)
{
    if (trace_event_get_state(TRACE_MACFB_CTRL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 181 "../xemu/hw/display/trace-events"
            qemu_log("macfb_ctrl_write " "addr 0x%"PRIx64 " value 0x%"PRIx64 " size %u" "\n", addr, value, size);
#line 2730 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_MACFB_SENSE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MACFB_SENSE_READ) || \
    false)

static inline void trace_macfb_sense_read(uint32_t value)
{
    if (trace_event_get_state(TRACE_MACFB_SENSE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 182 "../xemu/hw/display/trace-events"
            qemu_log("macfb_sense_read " "video sense: 0x%"PRIx32 "\n", value);
#line 2745 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_MACFB_SENSE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MACFB_SENSE_WRITE) || \
    false)

static inline void trace_macfb_sense_write(uint32_t value)
{
    if (trace_event_get_state(TRACE_MACFB_SENSE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 183 "../xemu/hw/display/trace-events"
            qemu_log("macfb_sense_write " "video sense: 0x%"PRIx32 "\n", value);
#line 2760 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_MACFB_UPDATE_MODE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MACFB_UPDATE_MODE) || \
    false)

static inline void trace_macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth)
{
    if (trace_event_get_state(TRACE_MACFB_UPDATE_MODE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 184 "../xemu/hw/display/trace-events"
            qemu_log("macfb_update_mode " "setting mode to width %"PRId32 " height %"PRId32 " size %d" "\n", width, height, depth);
#line 2775 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DM163_REDRAW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DM163_REDRAW) || \
    false)

static inline void trace_dm163_redraw(uint8_t redraw)
{
    if (trace_event_get_state(TRACE_DM163_REDRAW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 187 "../xemu/hw/display/trace-events"
            qemu_log("dm163_redraw " "0x%02x" "\n", redraw);
#line 2790 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DM163_DCK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DM163_DCK) || \
    false)

static inline void trace_dm163_dck(unsigned new_state)
{
    if (trace_event_get_state(TRACE_DM163_DCK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 188 "../xemu/hw/display/trace-events"
            qemu_log("dm163_dck " "dck : %u" "\n", new_state);
#line 2805 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DM163_EN_B_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DM163_EN_B) || \
    false)

static inline void trace_dm163_en_b(unsigned new_state)
{
    if (trace_event_get_state(TRACE_DM163_EN_B)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 189 "../xemu/hw/display/trace-events"
            qemu_log("dm163_en_b " "en_b : %u" "\n", new_state);
#line 2820 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DM163_RST_B_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DM163_RST_B) || \
    false)

static inline void trace_dm163_rst_b(unsigned new_state)
{
    if (trace_event_get_state(TRACE_DM163_RST_B)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 190 "../xemu/hw/display/trace-events"
            qemu_log("dm163_rst_b " "rst_b : %u" "\n", new_state);
#line 2835 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DM163_LAT_B_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DM163_LAT_B) || \
    false)

static inline void trace_dm163_lat_b(unsigned new_state)
{
    if (trace_event_get_state(TRACE_DM163_LAT_B)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 191 "../xemu/hw/display/trace-events"
            qemu_log("dm163_lat_b " "lat_b : %u" "\n", new_state);
#line 2850 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DM163_SIN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DM163_SIN) || \
    false)

static inline void trace_dm163_sin(unsigned new_state)
{
    if (trace_event_get_state(TRACE_DM163_SIN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 192 "../xemu/hw/display/trace-events"
            qemu_log("dm163_sin " "sin : %u" "\n", new_state);
#line 2865 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DM163_SELBK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DM163_SELBK) || \
    false)

static inline void trace_dm163_selbk(unsigned new_state)
{
    if (trace_event_get_state(TRACE_DM163_SELBK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 193 "../xemu/hw/display/trace-events"
            qemu_log("dm163_selbk " "selbk : %u" "\n", new_state);
#line 2880 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DM163_ACTIVATED_ROWS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DM163_ACTIVATED_ROWS) || \
    false)

static inline void trace_dm163_activated_rows(int new_state)
{
    if (trace_event_get_state(TRACE_DM163_ACTIVATED_ROWS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 194 "../xemu/hw/display/trace-events"
            qemu_log("dm163_activated_rows " "Activated rows : 0x%" PRIx32 "" "\n", new_state);
#line 2895 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DM163_BITS_PPI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DM163_BITS_PPI) || \
    false)

static inline void trace_dm163_bits_ppi(unsigned dest_width)
{
    if (trace_event_get_state(TRACE_DM163_BITS_PPI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 195 "../xemu/hw/display/trace-events"
            qemu_log("dm163_bits_ppi " "dest_width : %u" "\n", dest_width);
#line 2910 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DM163_LEDS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DM163_LEDS) || \
    false)

static inline void trace_dm163_leds(int led, uint32_t value)
{
    if (trace_event_get_state(TRACE_DM163_LEDS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 196 "../xemu/hw/display/trace-events"
            qemu_log("dm163_leds " "led %d: 0x%x" "\n", led, value);
#line 2925 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DM163_CHANNELS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DM163_CHANNELS) || \
    false)

static inline void trace_dm163_channels(int channel, uint8_t value)
{
    if (trace_event_get_state(TRACE_DM163_CHANNELS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 197 "../xemu/hw/display/trace-events"
            qemu_log("dm163_channels " "channel %d: 0x%x" "\n", channel, value);
#line 2940 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_DM163_REFRESH_RATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DM163_REFRESH_RATE) || \
    false)

static inline void trace_dm163_refresh_rate(uint32_t rr)
{
    if (trace_event_get_state(TRACE_DM163_REFRESH_RATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 198 "../xemu/hw/display/trace-events"
            qemu_log("dm163_refresh_rate " "refresh rate %d" "\n", rr);
#line 2955 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_READ) || \
    false)

static inline void trace_apple_gfx_read(uint64_t offset, uint64_t res)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 201 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_read " "offset=0x%"PRIx64" res=0x%"PRIx64 "\n", offset, res);
#line 2970 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_WRITE) || \
    false)

static inline void trace_apple_gfx_write(uint64_t offset, uint64_t val)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 202 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_write " "offset=0x%"PRIx64" val=0x%"PRIx64 "\n", offset, val);
#line 2985 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_CREATE_TASK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_CREATE_TASK) || \
    false)

static inline void trace_apple_gfx_create_task(uint32_t vm_size, void *va)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_CREATE_TASK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 203 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_create_task " "vm_size=0x%x base_addr=%p" "\n", vm_size, va);
#line 3000 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_DESTROY_TASK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_DESTROY_TASK) || \
    false)

static inline void trace_apple_gfx_destroy_task(void *task, unsigned int num_mapped_regions)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_DESTROY_TASK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 204 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_destroy_task " "task=%p, task->mapped_regions->len=%u" "\n", task, num_mapped_regions);
#line 3015 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_MAP_MEMORY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_MAP_MEMORY) || \
    false)

static inline void trace_apple_gfx_map_memory(void *task, uint32_t range_count, uint64_t virtual_offset, uint32_t read_only)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_MAP_MEMORY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 205 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_map_memory " "task=%p range_count=0x%x virtual_offset=0x%"PRIx64" read_only=%d" "\n", task, range_count, virtual_offset, read_only);
#line 3030 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_MAP_MEMORY_RANGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_MAP_MEMORY_RANGE) || \
    false)

static inline void trace_apple_gfx_map_memory_range(uint32_t i, uint64_t phys_addr, uint64_t phys_len)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_MAP_MEMORY_RANGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 206 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_map_memory_range " "[%d] phys_addr=0x%"PRIx64" phys_len=0x%"PRIx64 "\n", i, phys_addr, phys_len);
#line 3045 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_REMAP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_REMAP) || \
    false)

static inline void trace_apple_gfx_remap(uint64_t retval, void *source_ptr, uint64_t target)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_REMAP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 207 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_remap " "retval=%"PRId64" source=%p target=0x%"PRIx64 "\n", retval, source_ptr, target);
#line 3060 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_UNMAP_MEMORY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_UNMAP_MEMORY) || \
    false)

static inline void trace_apple_gfx_unmap_memory(void *task, uint64_t virtual_offset, uint64_t length)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_UNMAP_MEMORY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 208 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_unmap_memory " "task=%p virtual_offset=0x%"PRIx64" length=0x%"PRIx64 "\n", task, virtual_offset, length);
#line 3075 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_READ_MEMORY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_READ_MEMORY) || \
    false)

static inline void trace_apple_gfx_read_memory(uint64_t phys_address, uint64_t length, void *dst)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_READ_MEMORY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 209 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_read_memory " "phys_addr=0x%"PRIx64" length=0x%"PRIx64" dest=%p" "\n", phys_address, length, dst);
#line 3090 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_RAISE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_RAISE_IRQ) || \
    false)

static inline void trace_apple_gfx_raise_irq(uint32_t vector)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_RAISE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 210 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_raise_irq " "vector=0x%x" "\n", vector);
#line 3105 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_NEW_FRAME_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_NEW_FRAME) || \
    false)

static inline void trace_apple_gfx_new_frame(void)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_NEW_FRAME)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 211 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_new_frame " "" "\n");
#line 3120 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_MODE_CHANGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_MODE_CHANGE) || \
    false)

static inline void trace_apple_gfx_mode_change(uint64_t x, uint64_t y)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_MODE_CHANGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 212 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_mode_change " "x=%"PRId64" y=%"PRId64 "\n", x, y);
#line 3135 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_CURSOR_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_CURSOR_SET) || \
    false)

static inline void trace_apple_gfx_cursor_set(uint32_t bpp, uint64_t width, uint64_t height)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_CURSOR_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 213 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_cursor_set " "bpp=%d width=%"PRId64" height=0x%"PRId64 "\n", bpp, width, height);
#line 3150 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_CURSOR_SHOW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_CURSOR_SHOW) || \
    false)

static inline void trace_apple_gfx_cursor_show(uint32_t show)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_CURSOR_SHOW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 214 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_cursor_show " "show=%d" "\n", show);
#line 3165 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_CURSOR_MOVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_CURSOR_MOVE) || \
    false)

static inline void trace_apple_gfx_cursor_move(void)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_CURSOR_MOVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 215 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_cursor_move " "" "\n");
#line 3180 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_COMMON_INIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_COMMON_INIT) || \
    false)

static inline void trace_apple_gfx_common_init(const char *device_name, size_t mmio_size)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_COMMON_INIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 216 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_common_init " "device: %s; MMIO size: %zu bytes" "\n", device_name, mmio_size);
#line 3195 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_COMMON_REALIZE_MODES_PROPERTY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_COMMON_REALIZE_MODES_PROPERTY) || \
    false)

static inline void trace_apple_gfx_common_realize_modes_property(uint32_t num_modes)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_COMMON_REALIZE_MODES_PROPERTY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 217 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_common_realize_modes_property " "using %u modes supplied by 'display-modes' device property" "\n", num_modes);
#line 3210 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_DISPLAY_MODE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_DISPLAY_MODE) || \
    false)

static inline void trace_apple_gfx_display_mode(uint32_t mode_idx, uint16_t width_px, uint16_t height_px)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_DISPLAY_MODE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 218 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_display_mode " "mode %2"PRIu32": %4"PRIu16"x%4"PRIu16 "\n", mode_idx, width_px, height_px);
#line 3225 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_MMIO_IOSFC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_MMIO_IOSFC_READ) || \
    false)

static inline void trace_apple_gfx_mmio_iosfc_read(uint64_t offset, uint64_t res)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_MMIO_IOSFC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 221 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_mmio_iosfc_read " "offset=0x%"PRIx64" res=0x%"PRIx64 "\n", offset, res);
#line 3240 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_MMIO_IOSFC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_MMIO_IOSFC_WRITE) || \
    false)

static inline void trace_apple_gfx_mmio_iosfc_write(uint64_t offset, uint64_t val)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_MMIO_IOSFC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 222 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_mmio_iosfc_write " "offset=0x%"PRIx64" val=0x%"PRIx64 "\n", offset, val);
#line 3255 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_IOSFC_MAP_MEMORY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_IOSFC_MAP_MEMORY) || \
    false)

static inline void trace_apple_gfx_iosfc_map_memory(uint64_t phys, uint64_t len, uint32_t ro, void *va, void *e, void *f, void*va_result)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_IOSFC_MAP_MEMORY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 223 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_iosfc_map_memory " "phys=0x%"PRIx64" len=0x%"PRIx64" ro=%d va=%p e=%p f=%p -> *va=%p" "\n", phys, len, ro, va, e, f, va_result);
#line 3270 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_IOSFC_MAP_MEMORY_NEW_REGION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_IOSFC_MAP_MEMORY_NEW_REGION) || \
    false)

static inline void trace_apple_gfx_iosfc_map_memory_new_region(size_t i, void *region, uint64_t start, uint64_t end)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_IOSFC_MAP_MEMORY_NEW_REGION)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 224 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_iosfc_map_memory_new_region " "index=%zu, region=%p, 0x%"PRIx64"-0x%"PRIx64 "\n", i, region, start, end);
#line 3285 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_IOSFC_UNMAP_MEMORY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_IOSFC_UNMAP_MEMORY) || \
    false)

static inline void trace_apple_gfx_iosfc_unmap_memory(void *a, void *b, void *c, void *d, void *e, void *f)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_IOSFC_UNMAP_MEMORY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 225 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_iosfc_unmap_memory " "a=%p b=%p c=%p d=%p e=%p f=%p" "\n", a, b, c, d, e, f);
#line 3300 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_IOSFC_UNMAP_MEMORY_REGION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_IOSFC_UNMAP_MEMORY_REGION) || \
    false)

static inline void trace_apple_gfx_iosfc_unmap_memory_region(void*mem, void *region)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_IOSFC_UNMAP_MEMORY_REGION)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 226 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_iosfc_unmap_memory_region " "unmapping @ %p from memory region %p" "\n", mem, region);
#line 3315 "trace/trace-hw_display.h"
        }
    }
}

#define TRACE_APPLE_GFX_IOSFC_RAISE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APPLE_GFX_IOSFC_RAISE_IRQ) || \
    false)

static inline void trace_apple_gfx_iosfc_raise_irq(uint32_t vector)
{
    if (trace_event_get_state(TRACE_APPLE_GFX_IOSFC_RAISE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 227 "../xemu/hw/display/trace-events"
            qemu_log("apple_gfx_iosfc_raise_irq " "vector=0x%x" "\n", vector);
#line 3330 "trace/trace-hw_display.h"
        }
    }
}
#endif /* TRACE_HW_DISPLAY_GENERATED_TRACERS_H */
