/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_HW_CHAR_GENERATED_TRACERS_H
#define TRACE_HW_CHAR_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_PARALLEL_IOPORT_READ_EVENT;
extern TraceEvent _TRACE_PARALLEL_IOPORT_WRITE_EVENT;
extern TraceEvent _TRACE_SERIAL_READ_EVENT;
extern TraceEvent _TRACE_SERIAL_WRITE_EVENT;
extern TraceEvent _TRACE_SERIAL_UPDATE_PARAMETERS_EVENT;
extern TraceEvent _TRACE_VIRTIO_SERIAL_SEND_CONTROL_EVENT_EVENT;
extern TraceEvent _TRACE_VIRTIO_SERIAL_THROTTLE_PORT_EVENT;
extern TraceEvent _TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_EVENT;
extern TraceEvent _TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_PORT_EVENT;
extern TraceEvent _TRACE_VIRTIO_CONSOLE_FLUSH_BUF_EVENT;
extern TraceEvent _TRACE_VIRTIO_CONSOLE_CHR_READ_EVENT;
extern TraceEvent _TRACE_VIRTIO_CONSOLE_CHR_EVENT_EVENT;
extern TraceEvent _TRACE_GOLDFISH_TTY_READ_EVENT;
extern TraceEvent _TRACE_GOLDFISH_TTY_WRITE_EVENT;
extern TraceEvent _TRACE_GOLDFISH_TTY_CAN_RECEIVE_EVENT;
extern TraceEvent _TRACE_GOLDFISH_TTY_RECEIVE_EVENT;
extern TraceEvent _TRACE_GOLDFISH_TTY_RESET_EVENT;
extern TraceEvent _TRACE_GOLDFISH_TTY_REALIZE_EVENT;
extern TraceEvent _TRACE_GOLDFISH_TTY_UNREALIZE_EVENT;
extern TraceEvent _TRACE_GOLDFISH_TTY_INSTANCE_INIT_EVENT;
extern TraceEvent _TRACE_GRLIB_APBUART_EVENT_EVENT;
extern TraceEvent _TRACE_GRLIB_APBUART_WRITEL_UNKNOWN_EVENT;
extern TraceEvent _TRACE_GRLIB_APBUART_READL_UNKNOWN_EVENT;
extern TraceEvent _TRACE_ESCC_HARD_RESET_EVENT;
extern TraceEvent _TRACE_ESCC_SOFT_RESET_CHN_EVENT;
extern TraceEvent _TRACE_ESCC_PUT_QUEUE_EVENT;
extern TraceEvent _TRACE_ESCC_GET_QUEUE_EVENT;
extern TraceEvent _TRACE_ESCC_UPDATE_IRQ_EVENT;
extern TraceEvent _TRACE_ESCC_UPDATE_PARAMETERS_EVENT;
extern TraceEvent _TRACE_ESCC_MEM_WRITEB_CTRL_EVENT;
extern TraceEvent _TRACE_ESCC_MEM_WRITEB_DATA_EVENT;
extern TraceEvent _TRACE_ESCC_MEM_READB_CTRL_EVENT;
extern TraceEvent _TRACE_ESCC_MEM_READB_DATA_EVENT;
extern TraceEvent _TRACE_ESCC_SERIAL_RECEIVE_BYTE_EVENT;
extern TraceEvent _TRACE_ESCC_SUNKBD_EVENT_IN_EVENT;
extern TraceEvent _TRACE_ESCC_SUNKBD_EVENT_OUT_EVENT;
extern TraceEvent _TRACE_ESCC_KBD_COMMAND_EVENT;
extern TraceEvent _TRACE_ESCC_SUNMOUSE_EVENT_EVENT;
extern TraceEvent _TRACE_IMX_SERIAL_READ_EVENT;
extern TraceEvent _TRACE_IMX_SERIAL_WRITE_EVENT;
extern TraceEvent _TRACE_IMX_SERIAL_PUT_DATA_EVENT;
extern TraceEvent _TRACE_PL011_IRQ_STATE_EVENT;
extern TraceEvent _TRACE_PL011_READ_EVENT;
extern TraceEvent _TRACE_PL011_READ_FIFO_EVENT;
extern TraceEvent _TRACE_PL011_WRITE_EVENT;
extern TraceEvent _TRACE_PL011_CAN_RECEIVE_EVENT;
extern TraceEvent _TRACE_PL011_FIFO_RX_PUT_EVENT;
extern TraceEvent _TRACE_PL011_FIFO_RX_FULL_EVENT;
extern TraceEvent _TRACE_PL011_BAUDRATE_CHANGE_EVENT;
extern TraceEvent _TRACE_PL011_RECEIVE_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_UART_READ_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_UART_WRITE_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_UART_RESET_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_UART_RECEIVE_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_UART_TX_PENDING_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_UART_TX_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_UART_SET_PARAMS_EVENT;
extern TraceEvent _TRACE_NRF51_UART_READ_EVENT;
extern TraceEvent _TRACE_NRF51_UART_WRITE_EVENT;
extern TraceEvent _TRACE_SHAKTI_UART_READ_EVENT;
extern TraceEvent _TRACE_SHAKTI_UART_WRITE_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_DMABUSY_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_DMAREADY_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_IRQ_RAISED_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_IRQ_LOWERED_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_UPDATE_PARAMS_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_WRITE_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_READ_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_RX_FIFO_RESET_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_TX_FIFO_RESET_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_TX_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_INTCLR_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_RO_WRITE_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_RX_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_RX_ERROR_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_WO_READ_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_RXSIZE_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_CHANNEL_ERROR_EVENT;
extern TraceEvent _TRACE_EXYNOS_UART_RX_TIMEOUT_EVENT;
extern TraceEvent _TRACE_CADENCE_UART_BAUDRATE_EVENT;
extern TraceEvent _TRACE_SH_SERIAL_READ_EVENT;
extern TraceEvent _TRACE_SH_SERIAL_WRITE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_USART_READ_EVENT;
extern TraceEvent _TRACE_STM32L4X5_USART_WRITE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_USART_RX_EVENT;
extern TraceEvent _TRACE_STM32L4X5_USART_TX_EVENT;
extern TraceEvent _TRACE_STM32L4X5_USART_TX_PENDING_EVENT;
extern TraceEvent _TRACE_STM32L4X5_USART_IRQ_RAISED_EVENT;
extern TraceEvent _TRACE_STM32L4X5_USART_IRQ_LOWERED_EVENT;
extern TraceEvent _TRACE_STM32L4X5_USART_OVERRUN_DETECTED_EVENT;
extern TraceEvent _TRACE_STM32L4X5_USART_RECEIVER_NOT_ENABLED_EVENT;
extern TraceEvent _TRACE_STM32L4X5_USART_UPDATE_PARAMS_EVENT;
extern TraceEvent _TRACE_XEN_CONSOLE_CONNECT_EVENT;
extern TraceEvent _TRACE_XEN_CONSOLE_DISCONNECT_EVENT;
extern TraceEvent _TRACE_XEN_CONSOLE_UNREALIZE_EVENT;
extern TraceEvent _TRACE_XEN_CONSOLE_REALIZE_EVENT;
extern TraceEvent _TRACE_XEN_CONSOLE_DEVICE_CREATE_EVENT;
extern TraceEvent _TRACE_XEN_CONSOLE_DEVICE_DESTROY_EVENT;
extern TraceEvent _TRACE_STM32F2XX_USART_READ_EVENT;
extern TraceEvent _TRACE_STM32F2XX_USART_WRITE_EVENT;
extern TraceEvent _TRACE_STM32F2XX_USART_DROP_EVENT;
extern TraceEvent _TRACE_STM32F2XX_USART_RECEIVE_EVENT;
extern TraceEvent _TRACE_HTIF_UART_WRITE_TO_HOST_EVENT;
extern TraceEvent _TRACE_HTIF_UART_UNKNOWN_DEVICE_COMMAND_EVENT;
extern uint16_t _TRACE_PARALLEL_IOPORT_READ_DSTATE;
extern uint16_t _TRACE_PARALLEL_IOPORT_WRITE_DSTATE;
extern uint16_t _TRACE_SERIAL_READ_DSTATE;
extern uint16_t _TRACE_SERIAL_WRITE_DSTATE;
extern uint16_t _TRACE_SERIAL_UPDATE_PARAMETERS_DSTATE;
extern uint16_t _TRACE_VIRTIO_SERIAL_SEND_CONTROL_EVENT_DSTATE;
extern uint16_t _TRACE_VIRTIO_SERIAL_THROTTLE_PORT_DSTATE;
extern uint16_t _TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_DSTATE;
extern uint16_t _TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_PORT_DSTATE;
extern uint16_t _TRACE_VIRTIO_CONSOLE_FLUSH_BUF_DSTATE;
extern uint16_t _TRACE_VIRTIO_CONSOLE_CHR_READ_DSTATE;
extern uint16_t _TRACE_VIRTIO_CONSOLE_CHR_EVENT_DSTATE;
extern uint16_t _TRACE_GOLDFISH_TTY_READ_DSTATE;
extern uint16_t _TRACE_GOLDFISH_TTY_WRITE_DSTATE;
extern uint16_t _TRACE_GOLDFISH_TTY_CAN_RECEIVE_DSTATE;
extern uint16_t _TRACE_GOLDFISH_TTY_RECEIVE_DSTATE;
extern uint16_t _TRACE_GOLDFISH_TTY_RESET_DSTATE;
extern uint16_t _TRACE_GOLDFISH_TTY_REALIZE_DSTATE;
extern uint16_t _TRACE_GOLDFISH_TTY_UNREALIZE_DSTATE;
extern uint16_t _TRACE_GOLDFISH_TTY_INSTANCE_INIT_DSTATE;
extern uint16_t _TRACE_GRLIB_APBUART_EVENT_DSTATE;
extern uint16_t _TRACE_GRLIB_APBUART_WRITEL_UNKNOWN_DSTATE;
extern uint16_t _TRACE_GRLIB_APBUART_READL_UNKNOWN_DSTATE;
extern uint16_t _TRACE_ESCC_HARD_RESET_DSTATE;
extern uint16_t _TRACE_ESCC_SOFT_RESET_CHN_DSTATE;
extern uint16_t _TRACE_ESCC_PUT_QUEUE_DSTATE;
extern uint16_t _TRACE_ESCC_GET_QUEUE_DSTATE;
extern uint16_t _TRACE_ESCC_UPDATE_IRQ_DSTATE;
extern uint16_t _TRACE_ESCC_UPDATE_PARAMETERS_DSTATE;
extern uint16_t _TRACE_ESCC_MEM_WRITEB_CTRL_DSTATE;
extern uint16_t _TRACE_ESCC_MEM_WRITEB_DATA_DSTATE;
extern uint16_t _TRACE_ESCC_MEM_READB_CTRL_DSTATE;
extern uint16_t _TRACE_ESCC_MEM_READB_DATA_DSTATE;
extern uint16_t _TRACE_ESCC_SERIAL_RECEIVE_BYTE_DSTATE;
extern uint16_t _TRACE_ESCC_SUNKBD_EVENT_IN_DSTATE;
extern uint16_t _TRACE_ESCC_SUNKBD_EVENT_OUT_DSTATE;
extern uint16_t _TRACE_ESCC_KBD_COMMAND_DSTATE;
extern uint16_t _TRACE_ESCC_SUNMOUSE_EVENT_DSTATE;
extern uint16_t _TRACE_IMX_SERIAL_READ_DSTATE;
extern uint16_t _TRACE_IMX_SERIAL_WRITE_DSTATE;
extern uint16_t _TRACE_IMX_SERIAL_PUT_DATA_DSTATE;
extern uint16_t _TRACE_PL011_IRQ_STATE_DSTATE;
extern uint16_t _TRACE_PL011_READ_DSTATE;
extern uint16_t _TRACE_PL011_READ_FIFO_DSTATE;
extern uint16_t _TRACE_PL011_WRITE_DSTATE;
extern uint16_t _TRACE_PL011_CAN_RECEIVE_DSTATE;
extern uint16_t _TRACE_PL011_FIFO_RX_PUT_DSTATE;
extern uint16_t _TRACE_PL011_FIFO_RX_FULL_DSTATE;
extern uint16_t _TRACE_PL011_BAUDRATE_CHANGE_DSTATE;
extern uint16_t _TRACE_PL011_RECEIVE_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_UART_READ_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_UART_WRITE_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_UART_RESET_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_UART_RECEIVE_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_UART_TX_PENDING_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_UART_TX_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_UART_SET_PARAMS_DSTATE;
extern uint16_t _TRACE_NRF51_UART_READ_DSTATE;
extern uint16_t _TRACE_NRF51_UART_WRITE_DSTATE;
extern uint16_t _TRACE_SHAKTI_UART_READ_DSTATE;
extern uint16_t _TRACE_SHAKTI_UART_WRITE_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_DMABUSY_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_DMAREADY_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_IRQ_RAISED_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_IRQ_LOWERED_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_UPDATE_PARAMS_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_WRITE_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_READ_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_RX_FIFO_RESET_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_TX_FIFO_RESET_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_TX_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_INTCLR_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_RO_WRITE_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_RX_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_RX_ERROR_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_WO_READ_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_RXSIZE_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_CHANNEL_ERROR_DSTATE;
extern uint16_t _TRACE_EXYNOS_UART_RX_TIMEOUT_DSTATE;
extern uint16_t _TRACE_CADENCE_UART_BAUDRATE_DSTATE;
extern uint16_t _TRACE_SH_SERIAL_READ_DSTATE;
extern uint16_t _TRACE_SH_SERIAL_WRITE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_USART_READ_DSTATE;
extern uint16_t _TRACE_STM32L4X5_USART_WRITE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_USART_RX_DSTATE;
extern uint16_t _TRACE_STM32L4X5_USART_TX_DSTATE;
extern uint16_t _TRACE_STM32L4X5_USART_TX_PENDING_DSTATE;
extern uint16_t _TRACE_STM32L4X5_USART_IRQ_RAISED_DSTATE;
extern uint16_t _TRACE_STM32L4X5_USART_IRQ_LOWERED_DSTATE;
extern uint16_t _TRACE_STM32L4X5_USART_OVERRUN_DETECTED_DSTATE;
extern uint16_t _TRACE_STM32L4X5_USART_RECEIVER_NOT_ENABLED_DSTATE;
extern uint16_t _TRACE_STM32L4X5_USART_UPDATE_PARAMS_DSTATE;
extern uint16_t _TRACE_XEN_CONSOLE_CONNECT_DSTATE;
extern uint16_t _TRACE_XEN_CONSOLE_DISCONNECT_DSTATE;
extern uint16_t _TRACE_XEN_CONSOLE_UNREALIZE_DSTATE;
extern uint16_t _TRACE_XEN_CONSOLE_REALIZE_DSTATE;
extern uint16_t _TRACE_XEN_CONSOLE_DEVICE_CREATE_DSTATE;
extern uint16_t _TRACE_XEN_CONSOLE_DEVICE_DESTROY_DSTATE;
extern uint16_t _TRACE_STM32F2XX_USART_READ_DSTATE;
extern uint16_t _TRACE_STM32F2XX_USART_WRITE_DSTATE;
extern uint16_t _TRACE_STM32F2XX_USART_DROP_DSTATE;
extern uint16_t _TRACE_STM32F2XX_USART_RECEIVE_DSTATE;
extern uint16_t _TRACE_HTIF_UART_WRITE_TO_HOST_DSTATE;
extern uint16_t _TRACE_HTIF_UART_UNKNOWN_DEVICE_COMMAND_DSTATE;
#define TRACE_PARALLEL_IOPORT_READ_ENABLED 1
#define TRACE_PARALLEL_IOPORT_WRITE_ENABLED 1
#define TRACE_SERIAL_READ_ENABLED 1
#define TRACE_SERIAL_WRITE_ENABLED 1
#define TRACE_SERIAL_UPDATE_PARAMETERS_ENABLED 1
#define TRACE_VIRTIO_SERIAL_SEND_CONTROL_EVENT_ENABLED 1
#define TRACE_VIRTIO_SERIAL_THROTTLE_PORT_ENABLED 1
#define TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_ENABLED 1
#define TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_PORT_ENABLED 1
#define TRACE_VIRTIO_CONSOLE_FLUSH_BUF_ENABLED 1
#define TRACE_VIRTIO_CONSOLE_CHR_READ_ENABLED 1
#define TRACE_VIRTIO_CONSOLE_CHR_EVENT_ENABLED 1
#define TRACE_GOLDFISH_TTY_READ_ENABLED 1
#define TRACE_GOLDFISH_TTY_WRITE_ENABLED 1
#define TRACE_GOLDFISH_TTY_CAN_RECEIVE_ENABLED 1
#define TRACE_GOLDFISH_TTY_RECEIVE_ENABLED 1
#define TRACE_GOLDFISH_TTY_RESET_ENABLED 1
#define TRACE_GOLDFISH_TTY_REALIZE_ENABLED 1
#define TRACE_GOLDFISH_TTY_UNREALIZE_ENABLED 1
#define TRACE_GOLDFISH_TTY_INSTANCE_INIT_ENABLED 1
#define TRACE_GRLIB_APBUART_EVENT_ENABLED 1
#define TRACE_GRLIB_APBUART_WRITEL_UNKNOWN_ENABLED 1
#define TRACE_GRLIB_APBUART_READL_UNKNOWN_ENABLED 1
#define TRACE_ESCC_HARD_RESET_ENABLED 1
#define TRACE_ESCC_SOFT_RESET_CHN_ENABLED 1
#define TRACE_ESCC_PUT_QUEUE_ENABLED 1
#define TRACE_ESCC_GET_QUEUE_ENABLED 1
#define TRACE_ESCC_UPDATE_IRQ_ENABLED 1
#define TRACE_ESCC_UPDATE_PARAMETERS_ENABLED 1
#define TRACE_ESCC_MEM_WRITEB_CTRL_ENABLED 1
#define TRACE_ESCC_MEM_WRITEB_DATA_ENABLED 1
#define TRACE_ESCC_MEM_READB_CTRL_ENABLED 1
#define TRACE_ESCC_MEM_READB_DATA_ENABLED 1
#define TRACE_ESCC_SERIAL_RECEIVE_BYTE_ENABLED 1
#define TRACE_ESCC_SUNKBD_EVENT_IN_ENABLED 1
#define TRACE_ESCC_SUNKBD_EVENT_OUT_ENABLED 1
#define TRACE_ESCC_KBD_COMMAND_ENABLED 1
#define TRACE_ESCC_SUNMOUSE_EVENT_ENABLED 1
#define TRACE_IMX_SERIAL_READ_ENABLED 1
#define TRACE_IMX_SERIAL_WRITE_ENABLED 1
#define TRACE_IMX_SERIAL_PUT_DATA_ENABLED 1
#define TRACE_PL011_IRQ_STATE_ENABLED 1
#define TRACE_PL011_READ_ENABLED 1
#define TRACE_PL011_READ_FIFO_ENABLED 1
#define TRACE_PL011_WRITE_ENABLED 1
#define TRACE_PL011_CAN_RECEIVE_ENABLED 1
#define TRACE_PL011_FIFO_RX_PUT_ENABLED 1
#define TRACE_PL011_FIFO_RX_FULL_ENABLED 1
#define TRACE_PL011_BAUDRATE_CHANGE_ENABLED 1
#define TRACE_PL011_RECEIVE_ENABLED 1
#define TRACE_CMSDK_APB_UART_READ_ENABLED 1
#define TRACE_CMSDK_APB_UART_WRITE_ENABLED 1
#define TRACE_CMSDK_APB_UART_RESET_ENABLED 1
#define TRACE_CMSDK_APB_UART_RECEIVE_ENABLED 1
#define TRACE_CMSDK_APB_UART_TX_PENDING_ENABLED 1
#define TRACE_CMSDK_APB_UART_TX_ENABLED 1
#define TRACE_CMSDK_APB_UART_SET_PARAMS_ENABLED 1
#define TRACE_NRF51_UART_READ_ENABLED 1
#define TRACE_NRF51_UART_WRITE_ENABLED 1
#define TRACE_SHAKTI_UART_READ_ENABLED 1
#define TRACE_SHAKTI_UART_WRITE_ENABLED 1
#define TRACE_EXYNOS_UART_DMABUSY_ENABLED 1
#define TRACE_EXYNOS_UART_DMAREADY_ENABLED 1
#define TRACE_EXYNOS_UART_IRQ_RAISED_ENABLED 1
#define TRACE_EXYNOS_UART_IRQ_LOWERED_ENABLED 1
#define TRACE_EXYNOS_UART_UPDATE_PARAMS_ENABLED 1
#define TRACE_EXYNOS_UART_WRITE_ENABLED 1
#define TRACE_EXYNOS_UART_READ_ENABLED 1
#define TRACE_EXYNOS_UART_RX_FIFO_RESET_ENABLED 1
#define TRACE_EXYNOS_UART_TX_FIFO_RESET_ENABLED 1
#define TRACE_EXYNOS_UART_TX_ENABLED 1
#define TRACE_EXYNOS_UART_INTCLR_ENABLED 1
#define TRACE_EXYNOS_UART_RO_WRITE_ENABLED 1
#define TRACE_EXYNOS_UART_RX_ENABLED 1
#define TRACE_EXYNOS_UART_RX_ERROR_ENABLED 1
#define TRACE_EXYNOS_UART_WO_READ_ENABLED 1
#define TRACE_EXYNOS_UART_RXSIZE_ENABLED 1
#define TRACE_EXYNOS_UART_CHANNEL_ERROR_ENABLED 1
#define TRACE_EXYNOS_UART_RX_TIMEOUT_ENABLED 1
#define TRACE_CADENCE_UART_BAUDRATE_ENABLED 1
#define TRACE_SH_SERIAL_READ_ENABLED 1
#define TRACE_SH_SERIAL_WRITE_ENABLED 1
#define TRACE_STM32L4X5_USART_READ_ENABLED 1
#define TRACE_STM32L4X5_USART_WRITE_ENABLED 1
#define TRACE_STM32L4X5_USART_RX_ENABLED 1
#define TRACE_STM32L4X5_USART_TX_ENABLED 1
#define TRACE_STM32L4X5_USART_TX_PENDING_ENABLED 1
#define TRACE_STM32L4X5_USART_IRQ_RAISED_ENABLED 1
#define TRACE_STM32L4X5_USART_IRQ_LOWERED_ENABLED 1
#define TRACE_STM32L4X5_USART_OVERRUN_DETECTED_ENABLED 1
#define TRACE_STM32L4X5_USART_RECEIVER_NOT_ENABLED_ENABLED 1
#define TRACE_STM32L4X5_USART_UPDATE_PARAMS_ENABLED 1
#define TRACE_XEN_CONSOLE_CONNECT_ENABLED 1
#define TRACE_XEN_CONSOLE_DISCONNECT_ENABLED 1
#define TRACE_XEN_CONSOLE_UNREALIZE_ENABLED 1
#define TRACE_XEN_CONSOLE_REALIZE_ENABLED 1
#define TRACE_XEN_CONSOLE_DEVICE_CREATE_ENABLED 1
#define TRACE_XEN_CONSOLE_DEVICE_DESTROY_ENABLED 1
#define TRACE_STM32F2XX_USART_READ_ENABLED 1
#define TRACE_STM32F2XX_USART_WRITE_ENABLED 1
#define TRACE_STM32F2XX_USART_DROP_ENABLED 1
#define TRACE_STM32F2XX_USART_RECEIVE_ENABLED 1
#define TRACE_HTIF_UART_WRITE_TO_HOST_ENABLED 1
#define TRACE_HTIF_UART_UNKNOWN_DEVICE_COMMAND_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_PARALLEL_IOPORT_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PARALLEL_IOPORT_READ) || \
    false)

static inline void trace_parallel_ioport_read(const char *desc, uint16_t addr, uint8_t value)
{
    if (trace_event_get_state(TRACE_PARALLEL_IOPORT_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 4 "../xemu/hw/char/trace-events"
            qemu_log("parallel_ioport_read " "read [%s] addr 0x%02x val 0x%02x" "\n", desc, addr, value);
#line 335 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_PARALLEL_IOPORT_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PARALLEL_IOPORT_WRITE) || \
    false)

static inline void trace_parallel_ioport_write(const char *desc, uint16_t addr, uint8_t value)
{
    if (trace_event_get_state(TRACE_PARALLEL_IOPORT_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../xemu/hw/char/trace-events"
            qemu_log("parallel_ioport_write " "write [%s] addr 0x%02x val 0x%02x" "\n", desc, addr, value);
#line 350 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_SERIAL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SERIAL_READ) || \
    false)

static inline void trace_serial_read(uint16_t addr, uint8_t value)
{
    if (trace_event_get_state(TRACE_SERIAL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 8 "../xemu/hw/char/trace-events"
            qemu_log("serial_read " "read addr 0x%02x val 0x%02x" "\n", addr, value);
#line 365 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_SERIAL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SERIAL_WRITE) || \
    false)

static inline void trace_serial_write(uint16_t addr, uint8_t value)
{
    if (trace_event_get_state(TRACE_SERIAL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 9 "../xemu/hw/char/trace-events"
            qemu_log("serial_write " "write addr 0x%02x val 0x%02x" "\n", addr, value);
#line 380 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_SERIAL_UPDATE_PARAMETERS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SERIAL_UPDATE_PARAMETERS) || \
    false)

static inline void trace_serial_update_parameters(uint64_t baudrate, char parity, int data_bits, int stop_bits)
{
    if (trace_event_get_state(TRACE_SERIAL_UPDATE_PARAMETERS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 10 "../xemu/hw/char/trace-events"
            qemu_log("serial_update_parameters " "baudrate=%"PRIu64" parity='%c' data=%d stop=%d" "\n", baudrate, parity, data_bits, stop_bits);
#line 395 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_VIRTIO_SERIAL_SEND_CONTROL_EVENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_SERIAL_SEND_CONTROL_EVENT) || \
    false)

static inline void trace_virtio_serial_send_control_event(unsigned int port, uint16_t event, uint16_t value)
{
    if (trace_event_get_state(TRACE_VIRTIO_SERIAL_SEND_CONTROL_EVENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 13 "../xemu/hw/char/trace-events"
            qemu_log("virtio_serial_send_control_event " "port %u, event %u, value %u" "\n", port, event, value);
#line 410 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_VIRTIO_SERIAL_THROTTLE_PORT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_SERIAL_THROTTLE_PORT) || \
    false)

static inline void trace_virtio_serial_throttle_port(unsigned int port, bool throttle)
{
    if (trace_event_get_state(TRACE_VIRTIO_SERIAL_THROTTLE_PORT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 14 "../xemu/hw/char/trace-events"
            qemu_log("virtio_serial_throttle_port " "port %u, throttle %d" "\n", port, throttle);
#line 425 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE) || \
    false)

static inline void trace_virtio_serial_handle_control_message(uint16_t event, uint16_t value)
{
    if (trace_event_get_state(TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../xemu/hw/char/trace-events"
            qemu_log("virtio_serial_handle_control_message " "event %u, value %u" "\n", event, value);
#line 440 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_PORT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_PORT) || \
    false)

static inline void trace_virtio_serial_handle_control_message_port(unsigned int port)
{
    if (trace_event_get_state(TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_PORT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 16 "../xemu/hw/char/trace-events"
            qemu_log("virtio_serial_handle_control_message_port " "port %u" "\n", port);
#line 455 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_VIRTIO_CONSOLE_FLUSH_BUF_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_CONSOLE_FLUSH_BUF) || \
    false)

static inline void trace_virtio_console_flush_buf(unsigned int port, size_t len, ssize_t ret)
{
    if (trace_event_get_state(TRACE_VIRTIO_CONSOLE_FLUSH_BUF)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 19 "../xemu/hw/char/trace-events"
            qemu_log("virtio_console_flush_buf " "port %u, in_len %zu, out_len %zd" "\n", port, len, ret);
#line 470 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_VIRTIO_CONSOLE_CHR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_CONSOLE_CHR_READ) || \
    false)

static inline void trace_virtio_console_chr_read(unsigned int port, int size)
{
    if (trace_event_get_state(TRACE_VIRTIO_CONSOLE_CHR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 20 "../xemu/hw/char/trace-events"
            qemu_log("virtio_console_chr_read " "port %u, size %d" "\n", port, size);
#line 485 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_VIRTIO_CONSOLE_CHR_EVENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_CONSOLE_CHR_EVENT) || \
    false)

static inline void trace_virtio_console_chr_event(unsigned int port, int event)
{
    if (trace_event_get_state(TRACE_VIRTIO_CONSOLE_CHR_EVENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 21 "../xemu/hw/char/trace-events"
            qemu_log("virtio_console_chr_event " "port %u, event %d" "\n", port, event);
#line 500 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_GOLDFISH_TTY_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_TTY_READ) || \
    false)

static inline void trace_goldfish_tty_read(void *dev, unsigned int addr, unsigned int size, uint64_t value)
{
    if (trace_event_get_state(TRACE_GOLDFISH_TTY_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 24 "../xemu/hw/char/trace-events"
            qemu_log("goldfish_tty_read " "tty: %p reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", dev, addr, size, value);
#line 515 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_GOLDFISH_TTY_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_TTY_WRITE) || \
    false)

static inline void trace_goldfish_tty_write(void *dev, unsigned int addr, unsigned int size, uint64_t value)
{
    if (trace_event_get_state(TRACE_GOLDFISH_TTY_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 25 "../xemu/hw/char/trace-events"
            qemu_log("goldfish_tty_write " "tty: %p reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", dev, addr, size, value);
#line 530 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_GOLDFISH_TTY_CAN_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_TTY_CAN_RECEIVE) || \
    false)

static inline void trace_goldfish_tty_can_receive(void *dev, unsigned int available)
{
    if (trace_event_get_state(TRACE_GOLDFISH_TTY_CAN_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 26 "../xemu/hw/char/trace-events"
            qemu_log("goldfish_tty_can_receive " "tty: %p available: %u" "\n", dev, available);
#line 545 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_GOLDFISH_TTY_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_TTY_RECEIVE) || \
    false)

static inline void trace_goldfish_tty_receive(void *dev, unsigned int size)
{
    if (trace_event_get_state(TRACE_GOLDFISH_TTY_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 27 "../xemu/hw/char/trace-events"
            qemu_log("goldfish_tty_receive " "tty: %p size: %u" "\n", dev, size);
#line 560 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_GOLDFISH_TTY_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_TTY_RESET) || \
    false)

static inline void trace_goldfish_tty_reset(void *dev)
{
    if (trace_event_get_state(TRACE_GOLDFISH_TTY_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 28 "../xemu/hw/char/trace-events"
            qemu_log("goldfish_tty_reset " "tty: %p" "\n", dev);
#line 575 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_GOLDFISH_TTY_REALIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_TTY_REALIZE) || \
    false)

static inline void trace_goldfish_tty_realize(void *dev)
{
    if (trace_event_get_state(TRACE_GOLDFISH_TTY_REALIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 29 "../xemu/hw/char/trace-events"
            qemu_log("goldfish_tty_realize " "tty: %p" "\n", dev);
#line 590 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_GOLDFISH_TTY_UNREALIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_TTY_UNREALIZE) || \
    false)

static inline void trace_goldfish_tty_unrealize(void *dev)
{
    if (trace_event_get_state(TRACE_GOLDFISH_TTY_UNREALIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 30 "../xemu/hw/char/trace-events"
            qemu_log("goldfish_tty_unrealize " "tty: %p" "\n", dev);
#line 605 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_GOLDFISH_TTY_INSTANCE_INIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_TTY_INSTANCE_INIT) || \
    false)

static inline void trace_goldfish_tty_instance_init(void *dev)
{
    if (trace_event_get_state(TRACE_GOLDFISH_TTY_INSTANCE_INIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 31 "../xemu/hw/char/trace-events"
            qemu_log("goldfish_tty_instance_init " "tty: %p" "\n", dev);
#line 620 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_GRLIB_APBUART_EVENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_APBUART_EVENT) || \
    false)

static inline void trace_grlib_apbuart_event(int event)
{
    if (trace_event_get_state(TRACE_GRLIB_APBUART_EVENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 34 "../xemu/hw/char/trace-events"
            qemu_log("grlib_apbuart_event " "event:%d" "\n", event);
#line 635 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_GRLIB_APBUART_WRITEL_UNKNOWN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_APBUART_WRITEL_UNKNOWN) || \
    false)

static inline void trace_grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_GRLIB_APBUART_WRITEL_UNKNOWN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 35 "../xemu/hw/char/trace-events"
            qemu_log("grlib_apbuart_writel_unknown " "addr 0x%"PRIx64" value 0x%x" "\n", addr, value);
#line 650 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_GRLIB_APBUART_READL_UNKNOWN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_APBUART_READL_UNKNOWN) || \
    false)

static inline void trace_grlib_apbuart_readl_unknown(uint64_t addr)
{
    if (trace_event_get_state(TRACE_GRLIB_APBUART_READL_UNKNOWN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 36 "../xemu/hw/char/trace-events"
            qemu_log("grlib_apbuart_readl_unknown " "addr 0x%"PRIx64 "\n", addr);
#line 665 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_HARD_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_HARD_RESET) || \
    false)

static inline void trace_escc_hard_reset(void)
{
    if (trace_event_get_state(TRACE_ESCC_HARD_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 39 "../xemu/hw/char/trace-events"
            qemu_log("escc_hard_reset " "hard reset" "\n");
#line 680 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_SOFT_RESET_CHN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_SOFT_RESET_CHN) || \
    false)

static inline void trace_escc_soft_reset_chn(char channel)
{
    if (trace_event_get_state(TRACE_ESCC_SOFT_RESET_CHN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 40 "../xemu/hw/char/trace-events"
            qemu_log("escc_soft_reset_chn " "soft reset channel %c" "\n", channel);
#line 695 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_PUT_QUEUE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_PUT_QUEUE) || \
    false)

static inline void trace_escc_put_queue(char channel, int b)
{
    if (trace_event_get_state(TRACE_ESCC_PUT_QUEUE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 41 "../xemu/hw/char/trace-events"
            qemu_log("escc_put_queue " "channel %c put: 0x%02x" "\n", channel, b);
#line 710 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_GET_QUEUE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_GET_QUEUE) || \
    false)

static inline void trace_escc_get_queue(char channel, int val)
{
    if (trace_event_get_state(TRACE_ESCC_GET_QUEUE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 42 "../xemu/hw/char/trace-events"
            qemu_log("escc_get_queue " "channel %c get 0x%02x" "\n", channel, val);
#line 725 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_UPDATE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_UPDATE_IRQ) || \
    false)

static inline void trace_escc_update_irq(int irq)
{
    if (trace_event_get_state(TRACE_ESCC_UPDATE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 43 "../xemu/hw/char/trace-events"
            qemu_log("escc_update_irq " "IRQ = %d" "\n", irq);
#line 740 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_UPDATE_PARAMETERS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_UPDATE_PARAMETERS) || \
    false)

static inline void trace_escc_update_parameters(char channel, int speed, int parity, int data_bits, int stop_bits)
{
    if (trace_event_get_state(TRACE_ESCC_UPDATE_PARAMETERS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 44 "../xemu/hw/char/trace-events"
            qemu_log("escc_update_parameters " "channel %c: speed=%d parity=%c data=%d stop=%d" "\n", channel, speed, parity, data_bits, stop_bits);
#line 755 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_MEM_WRITEB_CTRL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_MEM_WRITEB_CTRL) || \
    false)

static inline void trace_escc_mem_writeb_ctrl(char channel, uint32_t reg, uint32_t val)
{
    if (trace_event_get_state(TRACE_ESCC_MEM_WRITEB_CTRL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 45 "../xemu/hw/char/trace-events"
            qemu_log("escc_mem_writeb_ctrl " "Write channel %c, reg[%d] = 0x%2.2x" "\n", channel, reg, val);
#line 770 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_MEM_WRITEB_DATA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_MEM_WRITEB_DATA) || \
    false)

static inline void trace_escc_mem_writeb_data(char channel, uint32_t val)
{
    if (trace_event_get_state(TRACE_ESCC_MEM_WRITEB_DATA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 46 "../xemu/hw/char/trace-events"
            qemu_log("escc_mem_writeb_data " "Write channel %c, ch %d" "\n", channel, val);
#line 785 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_MEM_READB_CTRL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_MEM_READB_CTRL) || \
    false)

static inline void trace_escc_mem_readb_ctrl(char channel, uint32_t reg, uint8_t val)
{
    if (trace_event_get_state(TRACE_ESCC_MEM_READB_CTRL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 47 "../xemu/hw/char/trace-events"
            qemu_log("escc_mem_readb_ctrl " "Read channel %c, reg[%d] = 0x%2.2x" "\n", channel, reg, val);
#line 800 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_MEM_READB_DATA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_MEM_READB_DATA) || \
    false)

static inline void trace_escc_mem_readb_data(char channel, uint32_t ret)
{
    if (trace_event_get_state(TRACE_ESCC_MEM_READB_DATA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 48 "../xemu/hw/char/trace-events"
            qemu_log("escc_mem_readb_data " "Read channel %c, ch %d" "\n", channel, ret);
#line 815 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_SERIAL_RECEIVE_BYTE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_SERIAL_RECEIVE_BYTE) || \
    false)

static inline void trace_escc_serial_receive_byte(char channel, int ch)
{
    if (trace_event_get_state(TRACE_ESCC_SERIAL_RECEIVE_BYTE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 49 "../xemu/hw/char/trace-events"
            qemu_log("escc_serial_receive_byte " "channel %c put ch %d" "\n", channel, ch);
#line 830 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_SUNKBD_EVENT_IN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_SUNKBD_EVENT_IN) || \
    false)

static inline void trace_escc_sunkbd_event_in(int ch, const char *name, int down)
{
    if (trace_event_get_state(TRACE_ESCC_SUNKBD_EVENT_IN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 50 "../xemu/hw/char/trace-events"
            qemu_log("escc_sunkbd_event_in " "QKeyCode 0x%2.2x [%s], down %d" "\n", ch, name, down);
#line 845 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_SUNKBD_EVENT_OUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_SUNKBD_EVENT_OUT) || \
    false)

static inline void trace_escc_sunkbd_event_out(int ch)
{
    if (trace_event_get_state(TRACE_ESCC_SUNKBD_EVENT_OUT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 51 "../xemu/hw/char/trace-events"
            qemu_log("escc_sunkbd_event_out " "Translated keycode 0x%2.2x" "\n", ch);
#line 860 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_KBD_COMMAND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_KBD_COMMAND) || \
    false)

static inline void trace_escc_kbd_command(int val)
{
    if (trace_event_get_state(TRACE_ESCC_KBD_COMMAND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 52 "../xemu/hw/char/trace-events"
            qemu_log("escc_kbd_command " "Command %d" "\n", val);
#line 875 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_ESCC_SUNMOUSE_EVENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ESCC_SUNMOUSE_EVENT) || \
    false)

static inline void trace_escc_sunmouse_event(int dx, int dy, int buttons_state)
{
    if (trace_event_get_state(TRACE_ESCC_SUNMOUSE_EVENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 53 "../xemu/hw/char/trace-events"
            qemu_log("escc_sunmouse_event " "dx=%d dy=%d buttons=0x%01x" "\n", dx, dy, buttons_state);
#line 890 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_IMX_SERIAL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_SERIAL_READ) || \
    false)

static inline void trace_imx_serial_read(const char *chrname, uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_IMX_SERIAL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 56 "../xemu/hw/char/trace-events"
            qemu_log("imx_serial_read " "%s:[0x%03" PRIu64 "] -> 0x%08" PRIx64 "\n", chrname, addr, value);
#line 905 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_IMX_SERIAL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_SERIAL_WRITE) || \
    false)

static inline void trace_imx_serial_write(const char *chrname, uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_IMX_SERIAL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 57 "../xemu/hw/char/trace-events"
            qemu_log("imx_serial_write " "%s:[0x%03" PRIu64 "] <- 0x%08" PRIx64 "\n", chrname, addr, value);
#line 920 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_IMX_SERIAL_PUT_DATA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_SERIAL_PUT_DATA) || \
    false)

static inline void trace_imx_serial_put_data(const char *chrname, uint32_t value)
{
    if (trace_event_get_state(TRACE_IMX_SERIAL_PUT_DATA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 58 "../xemu/hw/char/trace-events"
            qemu_log("imx_serial_put_data " "%s: 0x%" PRIx32 "\n", chrname, value);
#line 935 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_PL011_IRQ_STATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL011_IRQ_STATE) || \
    false)

static inline void trace_pl011_irq_state(bool level)
{
    if (trace_event_get_state(TRACE_PL011_IRQ_STATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 61 "../xemu/hw/char/trace-events"
            qemu_log("pl011_irq_state " "irq state %d" "\n", level);
#line 950 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_PL011_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL011_READ) || \
    false)

static inline void trace_pl011_read(uint64_t addr, uint32_t value, const char *regname)
{
    if (trace_event_get_state(TRACE_PL011_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 62 "../xemu/hw/char/trace-events"
            qemu_log("pl011_read " "addr 0x%03" PRIx64 " value 0x%08x reg %s" "\n", addr, value, regname);
#line 965 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_PL011_READ_FIFO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL011_READ_FIFO) || \
    false)

static inline void trace_pl011_read_fifo(unsigned rx_fifo_used, unsigned rx_fifo_depth)
{
    if (trace_event_get_state(TRACE_PL011_READ_FIFO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 63 "../xemu/hw/char/trace-events"
            qemu_log("pl011_read_fifo " "RX FIFO read, used %u/%u" "\n", rx_fifo_used, rx_fifo_depth);
#line 980 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_PL011_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL011_WRITE) || \
    false)

static inline void trace_pl011_write(uint64_t addr, uint32_t value, const char *regname)
{
    if (trace_event_get_state(TRACE_PL011_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 64 "../xemu/hw/char/trace-events"
            qemu_log("pl011_write " "addr 0x%03" PRIx64 " value 0x%08x reg %s" "\n", addr, value, regname);
#line 995 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_PL011_CAN_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL011_CAN_RECEIVE) || \
    false)

static inline void trace_pl011_can_receive(uint32_t lcr, unsigned rx_fifo_used, unsigned rx_fifo_depth, unsigned rx_fifo_available)
{
    if (trace_event_get_state(TRACE_PL011_CAN_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 65 "../xemu/hw/char/trace-events"
            qemu_log("pl011_can_receive " "LCR 0x%02x, RX FIFO used %u/%u, can_receive %u chars" "\n", lcr, rx_fifo_used, rx_fifo_depth, rx_fifo_available);
#line 1010 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_PL011_FIFO_RX_PUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL011_FIFO_RX_PUT) || \
    false)

static inline void trace_pl011_fifo_rx_put(uint32_t c, unsigned read_count, unsigned rx_fifo_depth)
{
    if (trace_event_get_state(TRACE_PL011_FIFO_RX_PUT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 66 "../xemu/hw/char/trace-events"
            qemu_log("pl011_fifo_rx_put " "RX FIFO push char [0x%02x] %d/%u depth used" "\n", c, read_count, rx_fifo_depth);
#line 1025 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_PL011_FIFO_RX_FULL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL011_FIFO_RX_FULL) || \
    false)

static inline void trace_pl011_fifo_rx_full(void)
{
    if (trace_event_get_state(TRACE_PL011_FIFO_RX_FULL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 67 "../xemu/hw/char/trace-events"
            qemu_log("pl011_fifo_rx_full " "RX FIFO now full, RXFF set" "\n");
#line 1040 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_PL011_BAUDRATE_CHANGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL011_BAUDRATE_CHANGE) || \
    false)

static inline void trace_pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd)
{
    if (trace_event_get_state(TRACE_PL011_BAUDRATE_CHANGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 68 "../xemu/hw/char/trace-events"
            qemu_log("pl011_baudrate_change " "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")" "\n", baudrate, clock, ibrd, fbrd);
#line 1055 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_PL011_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL011_RECEIVE) || \
    false)

static inline void trace_pl011_receive(size_t size)
{
    if (trace_event_get_state(TRACE_PL011_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 69 "../xemu/hw/char/trace-events"
            qemu_log("pl011_receive " "recv %zd chars" "\n", size);
#line 1070 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_CMSDK_APB_UART_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_READ) || \
    false)

static inline void trace_cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_UART_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 72 "../xemu/hw/char/trace-events"
            qemu_log("cmsdk_apb_uart_read " "CMSDK APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 1085 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_CMSDK_APB_UART_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_WRITE) || \
    false)

static inline void trace_cmsdk_apb_uart_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_UART_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 73 "../xemu/hw/char/trace-events"
            qemu_log("cmsdk_apb_uart_write " "CMSDK APB UART write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 1100 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_CMSDK_APB_UART_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_RESET) || \
    false)

static inline void trace_cmsdk_apb_uart_reset(void)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_UART_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 74 "../xemu/hw/char/trace-events"
            qemu_log("cmsdk_apb_uart_reset " "CMSDK APB UART: reset" "\n");
#line 1115 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_CMSDK_APB_UART_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_RECEIVE) || \
    false)

static inline void trace_cmsdk_apb_uart_receive(uint8_t c)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_UART_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 75 "../xemu/hw/char/trace-events"
            qemu_log("cmsdk_apb_uart_receive " "CMSDK APB UART: got character 0x%x from backend" "\n", c);
#line 1130 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_CMSDK_APB_UART_TX_PENDING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_TX_PENDING) || \
    false)

static inline void trace_cmsdk_apb_uart_tx_pending(void)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_UART_TX_PENDING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 76 "../xemu/hw/char/trace-events"
            qemu_log("cmsdk_apb_uart_tx_pending " "CMSDK APB UART: character send to backend pending" "\n");
#line 1145 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_CMSDK_APB_UART_TX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_TX) || \
    false)

static inline void trace_cmsdk_apb_uart_tx(uint8_t c)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_UART_TX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 77 "../xemu/hw/char/trace-events"
            qemu_log("cmsdk_apb_uart_tx " "CMSDK APB UART: character 0x%x sent to backend" "\n", c);
#line 1160 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_CMSDK_APB_UART_SET_PARAMS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_SET_PARAMS) || \
    false)

static inline void trace_cmsdk_apb_uart_set_params(int speed)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_UART_SET_PARAMS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 78 "../xemu/hw/char/trace-events"
            qemu_log("cmsdk_apb_uart_set_params " "CMSDK APB UART: params set to %d 8N1" "\n", speed);
#line 1175 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_NRF51_UART_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NRF51_UART_READ) || \
    false)

static inline void trace_nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size)
{
    if (trace_event_get_state(TRACE_NRF51_UART_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 81 "../xemu/hw/char/trace-events"
            qemu_log("nrf51_uart_read " "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u" "\n", addr, r, size);
#line 1190 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_NRF51_UART_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NRF51_UART_WRITE) || \
    false)

static inline void trace_nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size)
{
    if (trace_event_get_state(TRACE_NRF51_UART_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 82 "../xemu/hw/char/trace-events"
            qemu_log("nrf51_uart_write " "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u" "\n", addr, value, size);
#line 1205 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_SHAKTI_UART_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SHAKTI_UART_READ) || \
    false)

static inline void trace_shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size)
{
    if (trace_event_get_state(TRACE_SHAKTI_UART_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 85 "../xemu/hw/char/trace-events"
            qemu_log("shakti_uart_read " "addr 0x%" PRIx64 " value 0x%" PRIx16 " size %u" "\n", addr, r, size);
#line 1220 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_SHAKTI_UART_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SHAKTI_UART_WRITE) || \
    false)

static inline void trace_shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size)
{
    if (trace_event_get_state(TRACE_SHAKTI_UART_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 86 "../xemu/hw/char/trace-events"
            qemu_log("shakti_uart_write " "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u" "\n", addr, value, size);
#line 1235 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_DMABUSY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_DMABUSY) || \
    false)

static inline void trace_exynos_uart_dmabusy(uint32_t channel)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_DMABUSY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 89 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_dmabusy " "UART%d: DMA busy (Rx buffer empty)" "\n", channel);
#line 1250 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_DMAREADY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_DMAREADY) || \
    false)

static inline void trace_exynos_uart_dmaready(uint32_t channel)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_DMAREADY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 90 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_dmaready " "UART%d: DMA ready" "\n", channel);
#line 1265 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_IRQ_RAISED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_IRQ_RAISED) || \
    false)

static inline void trace_exynos_uart_irq_raised(uint32_t channel, uint32_t reg)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_IRQ_RAISED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 91 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_irq_raised " "UART%d: IRQ raised: 0x%08"PRIx32 "\n", channel, reg);
#line 1280 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_IRQ_LOWERED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_IRQ_LOWERED) || \
    false)

static inline void trace_exynos_uart_irq_lowered(uint32_t channel)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_IRQ_LOWERED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 92 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_irq_lowered " "UART%d: IRQ lowered" "\n", channel);
#line 1295 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_UPDATE_PARAMS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_UPDATE_PARAMS) || \
    false)

static inline void trace_exynos_uart_update_params(uint32_t channel, int speed, uint8_t parity, int data, int stop, uint64_t wordtime)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_UPDATE_PARAMS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 93 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_update_params " "UART%d: speed: %d, parity: %c, data bits: %d, stop bits: %d wordtime: %"PRId64"ns" "\n", channel, speed, parity, data, stop, wordtime);
#line 1310 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_WRITE) || \
    false)

static inline void trace_exynos_uart_write(uint32_t channel, uint32_t offset, const char *name, uint64_t val)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 94 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_write " "UART%d: <0x%04x> %s <- 0x%" PRIx64 "\n", channel, offset, name, val);
#line 1325 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_READ) || \
    false)

static inline void trace_exynos_uart_read(uint32_t channel, uint32_t offset, const char *name, uint64_t val)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 95 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_read " "UART%d: <0x%04x> %s -> 0x%" PRIx64 "\n", channel, offset, name, val);
#line 1340 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_RX_FIFO_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_RX_FIFO_RESET) || \
    false)

static inline void trace_exynos_uart_rx_fifo_reset(uint32_t channel)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_RX_FIFO_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 96 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_rx_fifo_reset " "UART%d: Rx FIFO Reset" "\n", channel);
#line 1355 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_TX_FIFO_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_TX_FIFO_RESET) || \
    false)

static inline void trace_exynos_uart_tx_fifo_reset(uint32_t channel)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_TX_FIFO_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 97 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_tx_fifo_reset " "UART%d: Tx FIFO Reset" "\n", channel);
#line 1370 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_TX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_TX) || \
    false)

static inline void trace_exynos_uart_tx(uint32_t channel, uint8_t ch)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_TX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 98 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_tx " "UART%d: Tx 0x%02"PRIx32 "\n", channel, ch);
#line 1385 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_INTCLR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_INTCLR) || \
    false)

static inline void trace_exynos_uart_intclr(uint32_t channel, uint32_t reg)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_INTCLR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 99 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_intclr " "UART%d: interrupts cleared: 0x%08"PRIx32 "\n", channel, reg);
#line 1400 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_RO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_RO_WRITE) || \
    false)

static inline void trace_exynos_uart_ro_write(uint32_t channel, const char *name, uint32_t reg)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_RO_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 100 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_ro_write " "UART%d: Trying to write into RO register: %s [0x%04"PRIx32"]" "\n", channel, name, reg);
#line 1415 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_RX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_RX) || \
    false)

static inline void trace_exynos_uart_rx(uint32_t channel, uint8_t ch)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_RX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 101 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_rx " "UART%d: Rx 0x%02"PRIx32 "\n", channel, ch);
#line 1430 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_RX_ERROR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_RX_ERROR) || \
    false)

static inline void trace_exynos_uart_rx_error(uint32_t channel)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_RX_ERROR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 102 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_rx_error " "UART%d: Rx error" "\n", channel);
#line 1445 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_WO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_WO_READ) || \
    false)

static inline void trace_exynos_uart_wo_read(uint32_t channel, const char *name, uint32_t reg)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_WO_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 103 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_wo_read " "UART%d: Trying to read from WO register: %s [0x%04"PRIx32"]" "\n", channel, name, reg);
#line 1460 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_RXSIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_RXSIZE) || \
    false)

static inline void trace_exynos_uart_rxsize(uint32_t channel, uint32_t size)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_RXSIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 104 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_rxsize " "UART%d: Rx FIFO size: %d" "\n", channel, size);
#line 1475 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_CHANNEL_ERROR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_CHANNEL_ERROR) || \
    false)

static inline void trace_exynos_uart_channel_error(uint32_t channel)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_CHANNEL_ERROR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 105 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_channel_error " "Wrong UART channel number: %d" "\n", channel);
#line 1490 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_EXYNOS_UART_RX_TIMEOUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXYNOS_UART_RX_TIMEOUT) || \
    false)

static inline void trace_exynos_uart_rx_timeout(uint32_t channel, uint32_t stat, uint32_t intsp)
{
    if (trace_event_get_state(TRACE_EXYNOS_UART_RX_TIMEOUT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 106 "../xemu/hw/char/trace-events"
            qemu_log("exynos_uart_rx_timeout " "UART%d: Rx timeout stat=0x%x intsp=0x%x" "\n", channel, stat, intsp);
#line 1505 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_CADENCE_UART_BAUDRATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CADENCE_UART_BAUDRATE) || \
    false)

static inline void trace_cadence_uart_baudrate(unsigned baudrate)
{
    if (trace_event_get_state(TRACE_CADENCE_UART_BAUDRATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 109 "../xemu/hw/char/trace-events"
            qemu_log("cadence_uart_baudrate " "baudrate %u" "\n", baudrate);
#line 1520 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_SH_SERIAL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SH_SERIAL_READ) || \
    false)

static inline void trace_sh_serial_read(char *id, unsigned size, uint64_t offs, uint64_t val)
{
    if (trace_event_get_state(TRACE_SH_SERIAL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 112 "../xemu/hw/char/trace-events"
            qemu_log("sh_serial_read " " %s size %d offs 0x%02" PRIx64 " -> 0x%02" PRIx64 "\n", id, size, offs, val);
#line 1535 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_SH_SERIAL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SH_SERIAL_WRITE) || \
    false)

static inline void trace_sh_serial_write(char *id, unsigned size, uint64_t offs, uint64_t val)
{
    if (trace_event_get_state(TRACE_SH_SERIAL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 113 "../xemu/hw/char/trace-events"
            qemu_log("sh_serial_write " "%s size %d offs 0x%02" PRIx64 " <- 0x%02" PRIx64 "\n", id, size, offs, val);
#line 1550 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32L4X5_USART_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_USART_READ) || \
    false)

static inline void trace_stm32l4x5_usart_read(uint64_t addr, uint32_t data)
{
    if (trace_event_get_state(TRACE_STM32L4X5_USART_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 116 "../xemu/hw/char/trace-events"
            qemu_log("stm32l4x5_usart_read " "USART: Read <0x%" PRIx64 "> -> 0x%" PRIx32 "" "\n", addr, data);
#line 1565 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32L4X5_USART_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_USART_WRITE) || \
    false)

static inline void trace_stm32l4x5_usart_write(uint64_t addr, uint32_t data)
{
    if (trace_event_get_state(TRACE_STM32L4X5_USART_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 117 "../xemu/hw/char/trace-events"
            qemu_log("stm32l4x5_usart_write " "USART: Write <0x%" PRIx64 "> <- 0x%" PRIx32 "" "\n", addr, data);
#line 1580 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32L4X5_USART_RX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_USART_RX) || \
    false)

static inline void trace_stm32l4x5_usart_rx(uint8_t c)
{
    if (trace_event_get_state(TRACE_STM32L4X5_USART_RX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 118 "../xemu/hw/char/trace-events"
            qemu_log("stm32l4x5_usart_rx " "USART: got character 0x%x from backend" "\n", c);
#line 1595 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32L4X5_USART_TX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_USART_TX) || \
    false)

static inline void trace_stm32l4x5_usart_tx(uint8_t c)
{
    if (trace_event_get_state(TRACE_STM32L4X5_USART_TX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 119 "../xemu/hw/char/trace-events"
            qemu_log("stm32l4x5_usart_tx " "USART: character 0x%x sent to backend" "\n", c);
#line 1610 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32L4X5_USART_TX_PENDING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_USART_TX_PENDING) || \
    false)

static inline void trace_stm32l4x5_usart_tx_pending(void)
{
    if (trace_event_get_state(TRACE_STM32L4X5_USART_TX_PENDING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 120 "../xemu/hw/char/trace-events"
            qemu_log("stm32l4x5_usart_tx_pending " "USART: character send to backend pending" "\n");
#line 1625 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32L4X5_USART_IRQ_RAISED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_USART_IRQ_RAISED) || \
    false)

static inline void trace_stm32l4x5_usart_irq_raised(uint32_t reg)
{
    if (trace_event_get_state(TRACE_STM32L4X5_USART_IRQ_RAISED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 121 "../xemu/hw/char/trace-events"
            qemu_log("stm32l4x5_usart_irq_raised " "USART: IRQ raised: 0x%08"PRIx32 "\n", reg);
#line 1640 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32L4X5_USART_IRQ_LOWERED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_USART_IRQ_LOWERED) || \
    false)

static inline void trace_stm32l4x5_usart_irq_lowered(void)
{
    if (trace_event_get_state(TRACE_STM32L4X5_USART_IRQ_LOWERED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 122 "../xemu/hw/char/trace-events"
            qemu_log("stm32l4x5_usart_irq_lowered " "USART: IRQ lowered" "\n");
#line 1655 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32L4X5_USART_OVERRUN_DETECTED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_USART_OVERRUN_DETECTED) || \
    false)

static inline void trace_stm32l4x5_usart_overrun_detected(uint8_t current, uint8_t received)
{
    if (trace_event_get_state(TRACE_STM32L4X5_USART_OVERRUN_DETECTED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 123 "../xemu/hw/char/trace-events"
            qemu_log("stm32l4x5_usart_overrun_detected " "USART: Overrun detected, RDR='0x%x', received 0x%x" "\n", current, received);
#line 1670 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32L4X5_USART_RECEIVER_NOT_ENABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_USART_RECEIVER_NOT_ENABLED) || \
    false)

static inline void trace_stm32l4x5_usart_receiver_not_enabled(uint8_t ue_bit, uint8_t re_bit)
{
    if (trace_event_get_state(TRACE_STM32L4X5_USART_RECEIVER_NOT_ENABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 124 "../xemu/hw/char/trace-events"
            qemu_log("stm32l4x5_usart_receiver_not_enabled " "USART: Receiver not enabled, UE=0x%x, RE=0x%x" "\n", ue_bit, re_bit);
#line 1685 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32L4X5_USART_UPDATE_PARAMS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_USART_UPDATE_PARAMS) || \
    false)

static inline void trace_stm32l4x5_usart_update_params(int speed, uint8_t parity, int data, int stop)
{
    if (trace_event_get_state(TRACE_STM32L4X5_USART_UPDATE_PARAMS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 125 "../xemu/hw/char/trace-events"
            qemu_log("stm32l4x5_usart_update_params " "USART: speed: %d, parity: %c, data bits: %d, stop bits: %d" "\n", speed, parity, data, stop);
#line 1700 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_XEN_CONSOLE_CONNECT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_CONSOLE_CONNECT) || \
    false)

static inline void trace_xen_console_connect(unsigned int idx, unsigned int ring_ref, unsigned int port, unsigned int limit)
{
    if (trace_event_get_state(TRACE_XEN_CONSOLE_CONNECT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 128 "../xemu/hw/char/trace-events"
            qemu_log("xen_console_connect " "idx %u ring_ref %u port %u limit %u" "\n", idx, ring_ref, port, limit);
#line 1715 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_XEN_CONSOLE_DISCONNECT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_CONSOLE_DISCONNECT) || \
    false)

static inline void trace_xen_console_disconnect(unsigned int idx)
{
    if (trace_event_get_state(TRACE_XEN_CONSOLE_DISCONNECT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 129 "../xemu/hw/char/trace-events"
            qemu_log("xen_console_disconnect " "idx %u" "\n", idx);
#line 1730 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_XEN_CONSOLE_UNREALIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_CONSOLE_UNREALIZE) || \
    false)

static inline void trace_xen_console_unrealize(unsigned int idx)
{
    if (trace_event_get_state(TRACE_XEN_CONSOLE_UNREALIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 130 "../xemu/hw/char/trace-events"
            qemu_log("xen_console_unrealize " "idx %u" "\n", idx);
#line 1745 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_XEN_CONSOLE_REALIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_CONSOLE_REALIZE) || \
    false)

static inline void trace_xen_console_realize(unsigned int idx, const char *chrdev)
{
    if (trace_event_get_state(TRACE_XEN_CONSOLE_REALIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 131 "../xemu/hw/char/trace-events"
            qemu_log("xen_console_realize " "idx %u chrdev %s" "\n", idx, chrdev);
#line 1760 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_XEN_CONSOLE_DEVICE_CREATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_CONSOLE_DEVICE_CREATE) || \
    false)

static inline void trace_xen_console_device_create(unsigned int idx)
{
    if (trace_event_get_state(TRACE_XEN_CONSOLE_DEVICE_CREATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 132 "../xemu/hw/char/trace-events"
            qemu_log("xen_console_device_create " "idx %u" "\n", idx);
#line 1775 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_XEN_CONSOLE_DEVICE_DESTROY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_CONSOLE_DEVICE_DESTROY) || \
    false)

static inline void trace_xen_console_device_destroy(unsigned int idx)
{
    if (trace_event_get_state(TRACE_XEN_CONSOLE_DEVICE_DESTROY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 133 "../xemu/hw/char/trace-events"
            qemu_log("xen_console_device_destroy " "idx %u" "\n", idx);
#line 1790 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32F2XX_USART_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32F2XX_USART_READ) || \
    false)

static inline void trace_stm32f2xx_usart_read(char *id, unsigned size, uint64_t ofs, uint64_t val)
{
    if (trace_event_get_state(TRACE_STM32F2XX_USART_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 136 "../xemu/hw/char/trace-events"
            qemu_log("stm32f2xx_usart_read " " %s size %d ofs 0x%02" PRIx64 " -> 0x%02" PRIx64 "\n", id, size, ofs, val);
#line 1805 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32F2XX_USART_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32F2XX_USART_WRITE) || \
    false)

static inline void trace_stm32f2xx_usart_write(char *id, unsigned size, uint64_t ofs, uint64_t val)
{
    if (trace_event_get_state(TRACE_STM32F2XX_USART_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 137 "../xemu/hw/char/trace-events"
            qemu_log("stm32f2xx_usart_write " "%s size %d ofs 0x%02" PRIx64 " <- 0x%02" PRIx64 "\n", id, size, ofs, val);
#line 1820 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32F2XX_USART_DROP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32F2XX_USART_DROP) || \
    false)

static inline void trace_stm32f2xx_usart_drop(char *id)
{
    if (trace_event_get_state(TRACE_STM32F2XX_USART_DROP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 138 "../xemu/hw/char/trace-events"
            qemu_log("stm32f2xx_usart_drop " " %s dropping the chars" "\n", id);
#line 1835 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_STM32F2XX_USART_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32F2XX_USART_RECEIVE) || \
    false)

static inline void trace_stm32f2xx_usart_receive(char *id, uint8_t chr)
{
    if (trace_event_get_state(TRACE_STM32F2XX_USART_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 139 "../xemu/hw/char/trace-events"
            qemu_log("stm32f2xx_usart_receive " " %s receiving '%c'" "\n", id, chr);
#line 1850 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_HTIF_UART_WRITE_TO_HOST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HTIF_UART_WRITE_TO_HOST) || \
    false)

static inline void trace_htif_uart_write_to_host(uint8_t device, uint8_t cmd, uint64_t payload)
{
    if (trace_event_get_state(TRACE_HTIF_UART_WRITE_TO_HOST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 142 "../xemu/hw/char/trace-events"
            qemu_log("htif_uart_write_to_host " "device: %u cmd: %02u payload: %016" PRIx64 "\n", device, cmd, payload);
#line 1865 "trace/trace-hw_char.h"
        }
    }
}

#define TRACE_HTIF_UART_UNKNOWN_DEVICE_COMMAND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HTIF_UART_UNKNOWN_DEVICE_COMMAND) || \
    false)

static inline void trace_htif_uart_unknown_device_command(uint8_t device, uint8_t cmd, uint64_t payload)
{
    if (trace_event_get_state(TRACE_HTIF_UART_UNKNOWN_DEVICE_COMMAND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 143 "../xemu/hw/char/trace-events"
            qemu_log("htif_uart_unknown_device_command " "device: %u cmd: %02u payload: %016" PRIx64 "\n", device, cmd, payload);
#line 1880 "trace/trace-hw_char.h"
        }
    }
}
#endif /* TRACE_HW_CHAR_GENERATED_TRACERS_H */
