/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_HW_CORE_GENERATED_TRACERS_H
#define TRACE_HW_CORE_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_LOADER_WRITE_ROM_EVENT;
extern TraceEvent _TRACE_QDEV_UPDATE_PARENT_BUS_EVENT;
extern TraceEvent _TRACE_RESETTABLE_RESET_EVENT;
extern TraceEvent _TRACE_RESETTABLE_RESET_ASSERT_BEGIN_EVENT;
extern TraceEvent _TRACE_RESETTABLE_RESET_ASSERT_END_EVENT;
extern TraceEvent _TRACE_RESETTABLE_RESET_RELEASE_BEGIN_EVENT;
extern TraceEvent _TRACE_RESETTABLE_RESET_RELEASE_END_EVENT;
extern TraceEvent _TRACE_RESETTABLE_CHANGE_PARENT_EVENT;
extern TraceEvent _TRACE_RESETTABLE_PHASE_ENTER_BEGIN_EVENT;
extern TraceEvent _TRACE_RESETTABLE_PHASE_ENTER_EXEC_EVENT;
extern TraceEvent _TRACE_RESETTABLE_PHASE_ENTER_END_EVENT;
extern TraceEvent _TRACE_RESETTABLE_PHASE_HOLD_BEGIN_EVENT;
extern TraceEvent _TRACE_RESETTABLE_PHASE_HOLD_EXEC_EVENT;
extern TraceEvent _TRACE_RESETTABLE_PHASE_HOLD_END_EVENT;
extern TraceEvent _TRACE_RESETTABLE_PHASE_EXIT_BEGIN_EVENT;
extern TraceEvent _TRACE_RESETTABLE_PHASE_EXIT_EXEC_EVENT;
extern TraceEvent _TRACE_RESETTABLE_PHASE_EXIT_END_EVENT;
extern TraceEvent _TRACE_RESETTABLE_TRANSITIONAL_FUNCTION_EVENT;
extern TraceEvent _TRACE_CLOCK_SET_SOURCE_EVENT;
extern TraceEvent _TRACE_CLOCK_DISCONNECT_EVENT;
extern TraceEvent _TRACE_CLOCK_SET_EVENT;
extern TraceEvent _TRACE_CLOCK_PROPAGATE_EVENT;
extern TraceEvent _TRACE_CLOCK_UPDATE_EVENT;
extern TraceEvent _TRACE_CLOCK_SET_MUL_DIV_EVENT;
extern TraceEvent _TRACE_CPU_RESET_EVENT;
extern uint16_t _TRACE_LOADER_WRITE_ROM_DSTATE;
extern uint16_t _TRACE_QDEV_UPDATE_PARENT_BUS_DSTATE;
extern uint16_t _TRACE_RESETTABLE_RESET_DSTATE;
extern uint16_t _TRACE_RESETTABLE_RESET_ASSERT_BEGIN_DSTATE;
extern uint16_t _TRACE_RESETTABLE_RESET_ASSERT_END_DSTATE;
extern uint16_t _TRACE_RESETTABLE_RESET_RELEASE_BEGIN_DSTATE;
extern uint16_t _TRACE_RESETTABLE_RESET_RELEASE_END_DSTATE;
extern uint16_t _TRACE_RESETTABLE_CHANGE_PARENT_DSTATE;
extern uint16_t _TRACE_RESETTABLE_PHASE_ENTER_BEGIN_DSTATE;
extern uint16_t _TRACE_RESETTABLE_PHASE_ENTER_EXEC_DSTATE;
extern uint16_t _TRACE_RESETTABLE_PHASE_ENTER_END_DSTATE;
extern uint16_t _TRACE_RESETTABLE_PHASE_HOLD_BEGIN_DSTATE;
extern uint16_t _TRACE_RESETTABLE_PHASE_HOLD_EXEC_DSTATE;
extern uint16_t _TRACE_RESETTABLE_PHASE_HOLD_END_DSTATE;
extern uint16_t _TRACE_RESETTABLE_PHASE_EXIT_BEGIN_DSTATE;
extern uint16_t _TRACE_RESETTABLE_PHASE_EXIT_EXEC_DSTATE;
extern uint16_t _TRACE_RESETTABLE_PHASE_EXIT_END_DSTATE;
extern uint16_t _TRACE_RESETTABLE_TRANSITIONAL_FUNCTION_DSTATE;
extern uint16_t _TRACE_CLOCK_SET_SOURCE_DSTATE;
extern uint16_t _TRACE_CLOCK_DISCONNECT_DSTATE;
extern uint16_t _TRACE_CLOCK_SET_DSTATE;
extern uint16_t _TRACE_CLOCK_PROPAGATE_DSTATE;
extern uint16_t _TRACE_CLOCK_UPDATE_DSTATE;
extern uint16_t _TRACE_CLOCK_SET_MUL_DIV_DSTATE;
extern uint16_t _TRACE_CPU_RESET_DSTATE;
#define TRACE_LOADER_WRITE_ROM_ENABLED 1
#define TRACE_QDEV_UPDATE_PARENT_BUS_ENABLED 1
#define TRACE_RESETTABLE_RESET_ENABLED 1
#define TRACE_RESETTABLE_RESET_ASSERT_BEGIN_ENABLED 1
#define TRACE_RESETTABLE_RESET_ASSERT_END_ENABLED 1
#define TRACE_RESETTABLE_RESET_RELEASE_BEGIN_ENABLED 1
#define TRACE_RESETTABLE_RESET_RELEASE_END_ENABLED 1
#define TRACE_RESETTABLE_CHANGE_PARENT_ENABLED 1
#define TRACE_RESETTABLE_PHASE_ENTER_BEGIN_ENABLED 1
#define TRACE_RESETTABLE_PHASE_ENTER_EXEC_ENABLED 1
#define TRACE_RESETTABLE_PHASE_ENTER_END_ENABLED 1
#define TRACE_RESETTABLE_PHASE_HOLD_BEGIN_ENABLED 1
#define TRACE_RESETTABLE_PHASE_HOLD_EXEC_ENABLED 1
#define TRACE_RESETTABLE_PHASE_HOLD_END_ENABLED 1
#define TRACE_RESETTABLE_PHASE_EXIT_BEGIN_ENABLED 1
#define TRACE_RESETTABLE_PHASE_EXIT_EXEC_ENABLED 1
#define TRACE_RESETTABLE_PHASE_EXIT_END_ENABLED 1
#define TRACE_RESETTABLE_TRANSITIONAL_FUNCTION_ENABLED 1
#define TRACE_CLOCK_SET_SOURCE_ENABLED 1
#define TRACE_CLOCK_DISCONNECT_ENABLED 1
#define TRACE_CLOCK_SET_ENABLED 1
#define TRACE_CLOCK_PROPAGATE_ENABLED 1
#define TRACE_CLOCK_UPDATE_ENABLED 1
#define TRACE_CLOCK_SET_MUL_DIV_ENABLED 1
#define TRACE_CPU_RESET_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_LOADER_WRITE_ROM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOADER_WRITE_ROM) || \
    false)

static inline void trace_loader_write_rom(const char *name, uint64_t gpa, uint64_t size, bool isrom)
{
    if (trace_event_get_state(TRACE_LOADER_WRITE_ROM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 2 "../xemu/hw/core/trace-events"
            qemu_log("loader_write_rom " "%s: @0x%"PRIx64" size=0x%"PRIx64" ROM=%d" "\n", name, gpa, size, isrom);
#line 98 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_QDEV_UPDATE_PARENT_BUS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_QDEV_UPDATE_PARENT_BUS) || \
    false)

static inline void trace_qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype)
{
    if (trace_event_get_state(TRACE_QDEV_UPDATE_PARENT_BUS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../xemu/hw/core/trace-events"
            qemu_log("qdev_update_parent_bus " "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)" "\n", obj, objtype, oldp, oldptype, newp, newptype);
#line 113 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_RESET) || \
    false)

static inline void trace_resettable_reset(void *obj, int cold)
{
    if (trace_event_get_state(TRACE_RESETTABLE_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 8 "../xemu/hw/core/trace-events"
            qemu_log("resettable_reset " "obj=%p cold=%d" "\n", obj, cold);
#line 128 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_RESET_ASSERT_BEGIN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_RESET_ASSERT_BEGIN) || \
    false)

static inline void trace_resettable_reset_assert_begin(void *obj, int cold)
{
    if (trace_event_get_state(TRACE_RESETTABLE_RESET_ASSERT_BEGIN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 9 "../xemu/hw/core/trace-events"
            qemu_log("resettable_reset_assert_begin " "obj=%p cold=%d" "\n", obj, cold);
#line 143 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_RESET_ASSERT_END_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_RESET_ASSERT_END) || \
    false)

static inline void trace_resettable_reset_assert_end(void *obj)
{
    if (trace_event_get_state(TRACE_RESETTABLE_RESET_ASSERT_END)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 10 "../xemu/hw/core/trace-events"
            qemu_log("resettable_reset_assert_end " "obj=%p" "\n", obj);
#line 158 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_RESET_RELEASE_BEGIN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_RESET_RELEASE_BEGIN) || \
    false)

static inline void trace_resettable_reset_release_begin(void *obj, int cold)
{
    if (trace_event_get_state(TRACE_RESETTABLE_RESET_RELEASE_BEGIN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 11 "../xemu/hw/core/trace-events"
            qemu_log("resettable_reset_release_begin " "obj=%p cold=%d" "\n", obj, cold);
#line 173 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_RESET_RELEASE_END_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_RESET_RELEASE_END) || \
    false)

static inline void trace_resettable_reset_release_end(void *obj)
{
    if (trace_event_get_state(TRACE_RESETTABLE_RESET_RELEASE_END)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 12 "../xemu/hw/core/trace-events"
            qemu_log("resettable_reset_release_end " "obj=%p" "\n", obj);
#line 188 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_CHANGE_PARENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_CHANGE_PARENT) || \
    false)

static inline void trace_resettable_change_parent(void *obj, void *o, unsigned oc, void *n, unsigned nc)
{
    if (trace_event_get_state(TRACE_RESETTABLE_CHANGE_PARENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 13 "../xemu/hw/core/trace-events"
            qemu_log("resettable_change_parent " "obj=%p from=%p(%d) to=%p(%d)" "\n", obj, o, oc, n, nc);
#line 203 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_PHASE_ENTER_BEGIN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_PHASE_ENTER_BEGIN) || \
    false)

static inline void trace_resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type)
{
    if (trace_event_get_state(TRACE_RESETTABLE_PHASE_ENTER_BEGIN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 14 "../xemu/hw/core/trace-events"
            qemu_log("resettable_phase_enter_begin " "obj=%p(%s) count=%d type=%d" "\n", obj, objtype, count, type);
#line 218 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_PHASE_ENTER_EXEC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_PHASE_ENTER_EXEC) || \
    false)

static inline void trace_resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method)
{
    if (trace_event_get_state(TRACE_RESETTABLE_PHASE_ENTER_EXEC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../xemu/hw/core/trace-events"
            qemu_log("resettable_phase_enter_exec " "obj=%p(%s) type=%d method=%d" "\n", obj, objtype, type, has_method);
#line 233 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_PHASE_ENTER_END_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_PHASE_ENTER_END) || \
    false)

static inline void trace_resettable_phase_enter_end(void *obj, const char *objtype, unsigned count)
{
    if (trace_event_get_state(TRACE_RESETTABLE_PHASE_ENTER_END)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 16 "../xemu/hw/core/trace-events"
            qemu_log("resettable_phase_enter_end " "obj=%p(%s) count=%d" "\n", obj, objtype, count);
#line 248 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_PHASE_HOLD_BEGIN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_PHASE_HOLD_BEGIN) || \
    false)

static inline void trace_resettable_phase_hold_begin(void *obj, const char *objtype, unsigned count, int type)
{
    if (trace_event_get_state(TRACE_RESETTABLE_PHASE_HOLD_BEGIN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 17 "../xemu/hw/core/trace-events"
            qemu_log("resettable_phase_hold_begin " "obj=%p(%s) count=%d type=%d" "\n", obj, objtype, count, type);
#line 263 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_PHASE_HOLD_EXEC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_PHASE_HOLD_EXEC) || \
    false)

static inline void trace_resettable_phase_hold_exec(void *obj, const char *objtype, int has_method)
{
    if (trace_event_get_state(TRACE_RESETTABLE_PHASE_HOLD_EXEC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 18 "../xemu/hw/core/trace-events"
            qemu_log("resettable_phase_hold_exec " "obj=%p(%s) method=%d" "\n", obj, objtype, has_method);
#line 278 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_PHASE_HOLD_END_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_PHASE_HOLD_END) || \
    false)

static inline void trace_resettable_phase_hold_end(void *obj, const char *objtype, unsigned count)
{
    if (trace_event_get_state(TRACE_RESETTABLE_PHASE_HOLD_END)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 19 "../xemu/hw/core/trace-events"
            qemu_log("resettable_phase_hold_end " "obj=%p(%s) count=%d" "\n", obj, objtype, count);
#line 293 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_PHASE_EXIT_BEGIN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_PHASE_EXIT_BEGIN) || \
    false)

static inline void trace_resettable_phase_exit_begin(void *obj, const char *objtype, unsigned count, int type)
{
    if (trace_event_get_state(TRACE_RESETTABLE_PHASE_EXIT_BEGIN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 20 "../xemu/hw/core/trace-events"
            qemu_log("resettable_phase_exit_begin " "obj=%p(%s) count=%d type=%d" "\n", obj, objtype, count, type);
#line 308 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_PHASE_EXIT_EXEC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_PHASE_EXIT_EXEC) || \
    false)

static inline void trace_resettable_phase_exit_exec(void *obj, const char *objtype, int has_method)
{
    if (trace_event_get_state(TRACE_RESETTABLE_PHASE_EXIT_EXEC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 21 "../xemu/hw/core/trace-events"
            qemu_log("resettable_phase_exit_exec " "obj=%p(%s) method=%d" "\n", obj, objtype, has_method);
#line 323 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_PHASE_EXIT_END_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_PHASE_EXIT_END) || \
    false)

static inline void trace_resettable_phase_exit_end(void *obj, const char *objtype, unsigned count)
{
    if (trace_event_get_state(TRACE_RESETTABLE_PHASE_EXIT_END)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 22 "../xemu/hw/core/trace-events"
            qemu_log("resettable_phase_exit_end " "obj=%p(%s) count=%d" "\n", obj, objtype, count);
#line 338 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_RESETTABLE_TRANSITIONAL_FUNCTION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RESETTABLE_TRANSITIONAL_FUNCTION) || \
    false)

static inline void trace_resettable_transitional_function(void *obj, const char *objtype)
{
    if (trace_event_get_state(TRACE_RESETTABLE_TRANSITIONAL_FUNCTION)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 23 "../xemu/hw/core/trace-events"
            qemu_log("resettable_transitional_function " "obj=%p(%s)" "\n", obj, objtype);
#line 353 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_CLOCK_SET_SOURCE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CLOCK_SET_SOURCE) || \
    false)

static inline void trace_clock_set_source(const char *clk, const char *src)
{
    if (trace_event_get_state(TRACE_CLOCK_SET_SOURCE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 26 "../xemu/hw/core/trace-events"
            qemu_log("clock_set_source " "'%s', src='%s'" "\n", clk, src);
#line 368 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_CLOCK_DISCONNECT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CLOCK_DISCONNECT) || \
    false)

static inline void trace_clock_disconnect(const char *clk)
{
    if (trace_event_get_state(TRACE_CLOCK_DISCONNECT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 27 "../xemu/hw/core/trace-events"
            qemu_log("clock_disconnect " "'%s'" "\n", clk);
#line 383 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_CLOCK_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CLOCK_SET) || \
    false)

static inline void trace_clock_set(const char *clk, uint64_t old, uint64_t new)
{
    if (trace_event_get_state(TRACE_CLOCK_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 28 "../xemu/hw/core/trace-events"
            qemu_log("clock_set " "'%s', %"PRIu64"Hz->%"PRIu64"Hz" "\n", clk, old, new);
#line 398 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_CLOCK_PROPAGATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CLOCK_PROPAGATE) || \
    false)

static inline void trace_clock_propagate(const char *clk)
{
    if (trace_event_get_state(TRACE_CLOCK_PROPAGATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 29 "../xemu/hw/core/trace-events"
            qemu_log("clock_propagate " "'%s'" "\n", clk);
#line 413 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_CLOCK_UPDATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CLOCK_UPDATE) || \
    false)

static inline void trace_clock_update(const char *clk, const char *src, uint64_t hz, int cb)
{
    if (trace_event_get_state(TRACE_CLOCK_UPDATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 30 "../xemu/hw/core/trace-events"
            qemu_log("clock_update " "'%s', src='%s', val=%"PRIu64"Hz cb=%d" "\n", clk, src, hz, cb);
#line 428 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_CLOCK_SET_MUL_DIV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CLOCK_SET_MUL_DIV) || \
    false)

static inline void trace_clock_set_mul_div(const char *clk, uint32_t oldmul, uint32_t mul, uint32_t olddiv, uint32_t div)
{
    if (trace_event_get_state(TRACE_CLOCK_SET_MUL_DIV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 31 "../xemu/hw/core/trace-events"
            qemu_log("clock_set_mul_div " "'%s', mul: %u -> %u, div: %u -> %u" "\n", clk, oldmul, mul, olddiv, div);
#line 443 "trace/trace-hw_core.h"
        }
    }
}

#define TRACE_CPU_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CPU_RESET) || \
    false)

static inline void trace_cpu_reset(int cpu_index)
{
    if (trace_event_get_state(TRACE_CPU_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 34 "../xemu/hw/core/trace-events"
            qemu_log("cpu_reset " "%d" "\n", cpu_index);
#line 458 "trace/trace-hw_core.h"
        }
    }
}
#endif /* TRACE_HW_CORE_GENERATED_TRACERS_H */
