/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_ACCEL_TCG_GENERATED_TRACERS_H
#define TRACE_ACCEL_TCG_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_EXEC_TB_EVENT;
extern TraceEvent _TRACE_EXEC_TB_NOCACHE_EVENT;
extern TraceEvent _TRACE_EXEC_TB_EXIT_EVENT;
extern TraceEvent _TRACE_MEMORY_NOTDIRTY_WRITE_ACCESS_EVENT;
extern TraceEvent _TRACE_MEMORY_NOTDIRTY_SET_DIRTY_EVENT;
extern TraceEvent _TRACE_TRANSLATE_BLOCK_EVENT;
extern TraceEvent _TRACE_TB_GEN_CODE_BUFFER_OVERFLOW_EVENT;
extern TraceEvent _TRACE_LOAD_ATOM2_FALLBACK_EVENT;
extern TraceEvent _TRACE_LOAD_ATOM4_FALLBACK_EVENT;
extern TraceEvent _TRACE_LOAD_ATOM8_OR_EXIT_FALLBACK_EVENT;
extern TraceEvent _TRACE_LOAD_ATOM8_FALLBACK_EVENT;
extern TraceEvent _TRACE_LOAD_ATOM16_FALLBACK_EVENT;
extern TraceEvent _TRACE_LOAD_ATOM16_OR_EXIT_FALLBACK_EVENT;
extern TraceEvent _TRACE_STORE_ATOM2_FALLBACK_EVENT;
extern TraceEvent _TRACE_STORE_ATOM4_FALLBACK_EVENT;
extern TraceEvent _TRACE_STORE_ATOM8_FALLBACK_EVENT;
extern TraceEvent _TRACE_STORE_ATOM16_FALLBACK_EVENT;
extern TraceEvent _TRACE_TB_FLUSH_EVENT;
extern uint16_t _TRACE_EXEC_TB_DSTATE;
extern uint16_t _TRACE_EXEC_TB_NOCACHE_DSTATE;
extern uint16_t _TRACE_EXEC_TB_EXIT_DSTATE;
extern uint16_t _TRACE_MEMORY_NOTDIRTY_WRITE_ACCESS_DSTATE;
extern uint16_t _TRACE_MEMORY_NOTDIRTY_SET_DIRTY_DSTATE;
extern uint16_t _TRACE_TRANSLATE_BLOCK_DSTATE;
extern uint16_t _TRACE_TB_GEN_CODE_BUFFER_OVERFLOW_DSTATE;
extern uint16_t _TRACE_LOAD_ATOM2_FALLBACK_DSTATE;
extern uint16_t _TRACE_LOAD_ATOM4_FALLBACK_DSTATE;
extern uint16_t _TRACE_LOAD_ATOM8_OR_EXIT_FALLBACK_DSTATE;
extern uint16_t _TRACE_LOAD_ATOM8_FALLBACK_DSTATE;
extern uint16_t _TRACE_LOAD_ATOM16_FALLBACK_DSTATE;
extern uint16_t _TRACE_LOAD_ATOM16_OR_EXIT_FALLBACK_DSTATE;
extern uint16_t _TRACE_STORE_ATOM2_FALLBACK_DSTATE;
extern uint16_t _TRACE_STORE_ATOM4_FALLBACK_DSTATE;
extern uint16_t _TRACE_STORE_ATOM8_FALLBACK_DSTATE;
extern uint16_t _TRACE_STORE_ATOM16_FALLBACK_DSTATE;
extern uint16_t _TRACE_TB_FLUSH_DSTATE;
#define TRACE_EXEC_TB_ENABLED 1
#define TRACE_EXEC_TB_NOCACHE_ENABLED 1
#define TRACE_EXEC_TB_EXIT_ENABLED 1
#define TRACE_MEMORY_NOTDIRTY_WRITE_ACCESS_ENABLED 1
#define TRACE_MEMORY_NOTDIRTY_SET_DIRTY_ENABLED 1
#define TRACE_TRANSLATE_BLOCK_ENABLED 1
#define TRACE_TB_GEN_CODE_BUFFER_OVERFLOW_ENABLED 1
#define TRACE_LOAD_ATOM2_FALLBACK_ENABLED 1
#define TRACE_LOAD_ATOM4_FALLBACK_ENABLED 1
#define TRACE_LOAD_ATOM8_OR_EXIT_FALLBACK_ENABLED 1
#define TRACE_LOAD_ATOM8_FALLBACK_ENABLED 1
#define TRACE_LOAD_ATOM16_FALLBACK_ENABLED 1
#define TRACE_LOAD_ATOM16_OR_EXIT_FALLBACK_ENABLED 1
#define TRACE_STORE_ATOM2_FALLBACK_ENABLED 1
#define TRACE_STORE_ATOM4_FALLBACK_ENABLED 1
#define TRACE_STORE_ATOM8_FALLBACK_ENABLED 1
#define TRACE_STORE_ATOM16_FALLBACK_ENABLED 1
#define TRACE_TB_FLUSH_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_EXEC_TB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXEC_TB) || \
    false)

static inline void trace_exec_tb(void *tb, uintptr_t pc)
{
    if (trace_event_get_state(TRACE_EXEC_TB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../xemu/accel/tcg/trace-events"
            qemu_log("exec_tb " "tb:%p pc=0x%"PRIxPTR "\n", tb, pc);
#line 77 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_EXEC_TB_NOCACHE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXEC_TB_NOCACHE) || \
    false)

static inline void trace_exec_tb_nocache(void *tb, uintptr_t pc)
{
    if (trace_event_get_state(TRACE_EXEC_TB_NOCACHE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 6 "../xemu/accel/tcg/trace-events"
            qemu_log("exec_tb_nocache " "tb:%p pc=0x%"PRIxPTR "\n", tb, pc);
#line 92 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_EXEC_TB_EXIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EXEC_TB_EXIT) || \
    false)

static inline void trace_exec_tb_exit(void *last_tb, unsigned int flags)
{
    if (trace_event_get_state(TRACE_EXEC_TB_EXIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 7 "../xemu/accel/tcg/trace-events"
            qemu_log("exec_tb_exit " "tb:%p flags=0x%x" "\n", last_tb, flags);
#line 107 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_MEMORY_NOTDIRTY_WRITE_ACCESS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MEMORY_NOTDIRTY_WRITE_ACCESS) || \
    false)

static inline void trace_memory_notdirty_write_access(uint64_t vaddr, uint64_t ram_addr, unsigned size)
{
    if (trace_event_get_state(TRACE_MEMORY_NOTDIRTY_WRITE_ACCESS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 10 "../xemu/accel/tcg/trace-events"
            qemu_log("memory_notdirty_write_access " "0x%" PRIx64 " ram_addr 0x%" PRIx64 " size %u" "\n", vaddr, ram_addr, size);
#line 122 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_MEMORY_NOTDIRTY_SET_DIRTY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MEMORY_NOTDIRTY_SET_DIRTY) || \
    false)

static inline void trace_memory_notdirty_set_dirty(uint64_t vaddr)
{
    if (trace_event_get_state(TRACE_MEMORY_NOTDIRTY_SET_DIRTY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 11 "../xemu/accel/tcg/trace-events"
            qemu_log("memory_notdirty_set_dirty " "0x%" PRIx64 "\n", vaddr);
#line 137 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_TRANSLATE_BLOCK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TRANSLATE_BLOCK) || \
    false)

static inline void trace_translate_block(void *tb, uintptr_t pc, const void *tb_code)
{
    if (trace_event_get_state(TRACE_TRANSLATE_BLOCK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 14 "../xemu/accel/tcg/trace-events"
            qemu_log("translate_block " "tb:%p, pc:0x%"PRIxPTR", tb_code:%p" "\n", tb, pc, tb_code);
#line 152 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_TB_GEN_CODE_BUFFER_OVERFLOW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TB_GEN_CODE_BUFFER_OVERFLOW) || \
    false)

static inline void trace_tb_gen_code_buffer_overflow(const char *reason)
{
    if (trace_event_get_state(TRACE_TB_GEN_CODE_BUFFER_OVERFLOW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../xemu/accel/tcg/trace-events"
            qemu_log("tb_gen_code_buffer_overflow " "reason: %s" "\n", reason);
#line 167 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_LOAD_ATOM2_FALLBACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOAD_ATOM2_FALLBACK) || \
    false)

static inline void trace_load_atom2_fallback(uint32_t memop, uintptr_t ra)
{
    if (trace_event_get_state(TRACE_LOAD_ATOM2_FALLBACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 18 "../xemu/accel/tcg/trace-events"
            qemu_log("load_atom2_fallback " "mop:0x%"PRIx32", ra:0x%"PRIxPTR"" "\n", memop, ra);
#line 182 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_LOAD_ATOM4_FALLBACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOAD_ATOM4_FALLBACK) || \
    false)

static inline void trace_load_atom4_fallback(uint32_t memop, uintptr_t ra)
{
    if (trace_event_get_state(TRACE_LOAD_ATOM4_FALLBACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 19 "../xemu/accel/tcg/trace-events"
            qemu_log("load_atom4_fallback " "mop:0x%"PRIx32", ra:0x%"PRIxPTR"" "\n", memop, ra);
#line 197 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_LOAD_ATOM8_OR_EXIT_FALLBACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOAD_ATOM8_OR_EXIT_FALLBACK) || \
    false)

static inline void trace_load_atom8_or_exit_fallback(uintptr_t ra)
{
    if (trace_event_get_state(TRACE_LOAD_ATOM8_OR_EXIT_FALLBACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 20 "../xemu/accel/tcg/trace-events"
            qemu_log("load_atom8_or_exit_fallback " "ra:0x%"PRIxPTR"" "\n", ra);
#line 212 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_LOAD_ATOM8_FALLBACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOAD_ATOM8_FALLBACK) || \
    false)

static inline void trace_load_atom8_fallback(uint32_t memop, uintptr_t ra)
{
    if (trace_event_get_state(TRACE_LOAD_ATOM8_FALLBACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 21 "../xemu/accel/tcg/trace-events"
            qemu_log("load_atom8_fallback " "mop:0x%"PRIx32", ra:0x%"PRIxPTR"" "\n", memop, ra);
#line 227 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_LOAD_ATOM16_FALLBACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOAD_ATOM16_FALLBACK) || \
    false)

static inline void trace_load_atom16_fallback(uint32_t memop, uintptr_t ra)
{
    if (trace_event_get_state(TRACE_LOAD_ATOM16_FALLBACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 22 "../xemu/accel/tcg/trace-events"
            qemu_log("load_atom16_fallback " "mop:0x%"PRIx32", ra:0x%"PRIxPTR"" "\n", memop, ra);
#line 242 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_LOAD_ATOM16_OR_EXIT_FALLBACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LOAD_ATOM16_OR_EXIT_FALLBACK) || \
    false)

static inline void trace_load_atom16_or_exit_fallback(uintptr_t ra)
{
    if (trace_event_get_state(TRACE_LOAD_ATOM16_OR_EXIT_FALLBACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 23 "../xemu/accel/tcg/trace-events"
            qemu_log("load_atom16_or_exit_fallback " "ra:0x%"PRIxPTR"" "\n", ra);
#line 257 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_STORE_ATOM2_FALLBACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STORE_ATOM2_FALLBACK) || \
    false)

static inline void trace_store_atom2_fallback(uint32_t memop, uintptr_t ra)
{
    if (trace_event_get_state(TRACE_STORE_ATOM2_FALLBACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 24 "../xemu/accel/tcg/trace-events"
            qemu_log("store_atom2_fallback " "mop:0x%"PRIx32", ra:0x%"PRIxPTR"" "\n", memop, ra);
#line 272 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_STORE_ATOM4_FALLBACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STORE_ATOM4_FALLBACK) || \
    false)

static inline void trace_store_atom4_fallback(uint32_t memop, uintptr_t ra)
{
    if (trace_event_get_state(TRACE_STORE_ATOM4_FALLBACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 25 "../xemu/accel/tcg/trace-events"
            qemu_log("store_atom4_fallback " "mop:0x%"PRIx32", ra:0x%"PRIxPTR"" "\n", memop, ra);
#line 287 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_STORE_ATOM8_FALLBACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STORE_ATOM8_FALLBACK) || \
    false)

static inline void trace_store_atom8_fallback(uint32_t memop, uintptr_t ra)
{
    if (trace_event_get_state(TRACE_STORE_ATOM8_FALLBACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 26 "../xemu/accel/tcg/trace-events"
            qemu_log("store_atom8_fallback " "mop:0x%"PRIx32", ra:0x%"PRIxPTR"" "\n", memop, ra);
#line 302 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_STORE_ATOM16_FALLBACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STORE_ATOM16_FALLBACK) || \
    false)

static inline void trace_store_atom16_fallback(uint32_t memop, uintptr_t ra)
{
    if (trace_event_get_state(TRACE_STORE_ATOM16_FALLBACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 27 "../xemu/accel/tcg/trace-events"
            qemu_log("store_atom16_fallback " "mop:0x%"PRIx32", ra:0x%"PRIxPTR"" "\n", memop, ra);
#line 317 "trace/trace-accel_tcg.h"
        }
    }
}

#define TRACE_TB_FLUSH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TB_FLUSH) || \
    false)

static inline void trace_tb_flush(void)
{
    if (trace_event_get_state(TRACE_TB_FLUSH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 30 "../xemu/accel/tcg/trace-events"
            qemu_log("tb_flush " "" "\n");
#line 332 "trace/trace-accel_tcg.h"
        }
    }
}
#endif /* TRACE_ACCEL_TCG_GENERATED_TRACERS_H */
