/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_HW_RTC_GENERATED_TRACERS_H
#define TRACE_HW_RTC_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_ALLWINNER_RTC_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_RTC_WRITE_EVENT;
extern TraceEvent _TRACE_SUN4V_RTC_READ_EVENT;
extern TraceEvent _TRACE_SUN4V_RTC_WRITE_EVENT;
extern TraceEvent _TRACE_XLNX_ZYNQMP_RTC_GETTIME_EVENT;
extern TraceEvent _TRACE_PL031_IRQ_STATE_EVENT;
extern TraceEvent _TRACE_PL031_READ_EVENT;
extern TraceEvent _TRACE_PL031_WRITE_EVENT;
extern TraceEvent _TRACE_PL031_ALARM_RAISED_EVENT;
extern TraceEvent _TRACE_PL031_SET_ALARM_EVENT;
extern TraceEvent _TRACE_ASPEED_RTC_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_RTC_WRITE_EVENT;
extern TraceEvent _TRACE_DS1338_RECV_EVENT;
extern TraceEvent _TRACE_DS1338_SEND_EVENT;
extern TraceEvent _TRACE_M48TXX_NVRAM_IO_READ_EVENT;
extern TraceEvent _TRACE_M48TXX_NVRAM_IO_WRITE_EVENT;
extern TraceEvent _TRACE_M48TXX_NVRAM_MEM_READ_EVENT;
extern TraceEvent _TRACE_M48TXX_NVRAM_MEM_WRITE_EVENT;
extern TraceEvent _TRACE_MC146818_RTC_IOPORT_READ_EVENT;
extern TraceEvent _TRACE_MC146818_RTC_IOPORT_WRITE_EVENT;
extern TraceEvent _TRACE_GOLDFISH_RTC_READ_EVENT;
extern TraceEvent _TRACE_GOLDFISH_RTC_WRITE_EVENT;
extern TraceEvent _TRACE_RS5C372_RECV_EVENT;
extern TraceEvent _TRACE_RS5C372_SEND_EVENT;
extern uint16_t _TRACE_ALLWINNER_RTC_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_RTC_WRITE_DSTATE;
extern uint16_t _TRACE_SUN4V_RTC_READ_DSTATE;
extern uint16_t _TRACE_SUN4V_RTC_WRITE_DSTATE;
extern uint16_t _TRACE_XLNX_ZYNQMP_RTC_GETTIME_DSTATE;
extern uint16_t _TRACE_PL031_IRQ_STATE_DSTATE;
extern uint16_t _TRACE_PL031_READ_DSTATE;
extern uint16_t _TRACE_PL031_WRITE_DSTATE;
extern uint16_t _TRACE_PL031_ALARM_RAISED_DSTATE;
extern uint16_t _TRACE_PL031_SET_ALARM_DSTATE;
extern uint16_t _TRACE_ASPEED_RTC_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_RTC_WRITE_DSTATE;
extern uint16_t _TRACE_DS1338_RECV_DSTATE;
extern uint16_t _TRACE_DS1338_SEND_DSTATE;
extern uint16_t _TRACE_M48TXX_NVRAM_IO_READ_DSTATE;
extern uint16_t _TRACE_M48TXX_NVRAM_IO_WRITE_DSTATE;
extern uint16_t _TRACE_M48TXX_NVRAM_MEM_READ_DSTATE;
extern uint16_t _TRACE_M48TXX_NVRAM_MEM_WRITE_DSTATE;
extern uint16_t _TRACE_MC146818_RTC_IOPORT_READ_DSTATE;
extern uint16_t _TRACE_MC146818_RTC_IOPORT_WRITE_DSTATE;
extern uint16_t _TRACE_GOLDFISH_RTC_READ_DSTATE;
extern uint16_t _TRACE_GOLDFISH_RTC_WRITE_DSTATE;
extern uint16_t _TRACE_RS5C372_RECV_DSTATE;
extern uint16_t _TRACE_RS5C372_SEND_DSTATE;
#define TRACE_ALLWINNER_RTC_READ_ENABLED 1
#define TRACE_ALLWINNER_RTC_WRITE_ENABLED 1
#define TRACE_SUN4V_RTC_READ_ENABLED 1
#define TRACE_SUN4V_RTC_WRITE_ENABLED 1
#define TRACE_XLNX_ZYNQMP_RTC_GETTIME_ENABLED 1
#define TRACE_PL031_IRQ_STATE_ENABLED 1
#define TRACE_PL031_READ_ENABLED 1
#define TRACE_PL031_WRITE_ENABLED 1
#define TRACE_PL031_ALARM_RAISED_ENABLED 1
#define TRACE_PL031_SET_ALARM_ENABLED 1
#define TRACE_ASPEED_RTC_READ_ENABLED 1
#define TRACE_ASPEED_RTC_WRITE_ENABLED 1
#define TRACE_DS1338_RECV_ENABLED 1
#define TRACE_DS1338_SEND_ENABLED 1
#define TRACE_M48TXX_NVRAM_IO_READ_ENABLED 1
#define TRACE_M48TXX_NVRAM_IO_WRITE_ENABLED 1
#define TRACE_M48TXX_NVRAM_MEM_READ_ENABLED 1
#define TRACE_M48TXX_NVRAM_MEM_WRITE_ENABLED 1
#define TRACE_MC146818_RTC_IOPORT_READ_ENABLED 1
#define TRACE_MC146818_RTC_IOPORT_WRITE_ENABLED 1
#define TRACE_GOLDFISH_RTC_READ_ENABLED 1
#define TRACE_GOLDFISH_RTC_WRITE_ENABLED 1
#define TRACE_RS5C372_RECV_ENABLED 1
#define TRACE_RS5C372_SEND_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_ALLWINNER_RTC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_RTC_READ) || \
    false)

static inline void trace_allwinner_rtc_read(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_ALLWINNER_RTC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 4 "../xemu/hw/rtc/trace-events"
            qemu_log("allwinner_rtc_read " "addr 0x%" PRIx64 " value 0x%" PRIx64 "\n", addr, value);
#line 95 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_ALLWINNER_RTC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_RTC_WRITE) || \
    false)

static inline void trace_allwinner_rtc_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_ALLWINNER_RTC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../xemu/hw/rtc/trace-events"
            qemu_log("allwinner_rtc_write " "addr 0x%" PRIx64 " value 0x%" PRIx64 "\n", addr, value);
#line 110 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_SUN4V_RTC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUN4V_RTC_READ) || \
    false)

static inline void trace_sun4v_rtc_read(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_SUN4V_RTC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 8 "../xemu/hw/rtc/trace-events"
            qemu_log("sun4v_rtc_read " "read: addr 0x%" PRIx64 " value 0x%" PRIx64 "\n", addr, value);
#line 125 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_SUN4V_RTC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUN4V_RTC_WRITE) || \
    false)

static inline void trace_sun4v_rtc_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_SUN4V_RTC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 9 "../xemu/hw/rtc/trace-events"
            qemu_log("sun4v_rtc_write " "write: addr 0x%" PRIx64 " value 0x%" PRIx64 "\n", addr, value);
#line 140 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_XLNX_ZYNQMP_RTC_GETTIME_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XLNX_ZYNQMP_RTC_GETTIME) || \
    false)

static inline void trace_xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec)
{
    if (trace_event_get_state(TRACE_XLNX_ZYNQMP_RTC_GETTIME)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 12 "../xemu/hw/rtc/trace-events"
            qemu_log("xlnx_zynqmp_rtc_gettime " "Get time from host: %d-%d-%d %2d:%02d:%02d" "\n", year, month, day, hour, min, sec);
#line 155 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_PL031_IRQ_STATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL031_IRQ_STATE) || \
    false)

static inline void trace_pl031_irq_state(int level)
{
    if (trace_event_get_state(TRACE_PL031_IRQ_STATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../xemu/hw/rtc/trace-events"
            qemu_log("pl031_irq_state " "irq state %d" "\n", level);
#line 170 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_PL031_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL031_READ) || \
    false)

static inline void trace_pl031_read(uint32_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_PL031_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 16 "../xemu/hw/rtc/trace-events"
            qemu_log("pl031_read " "addr 0x%08x value 0x%08x" "\n", addr, value);
#line 185 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_PL031_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL031_WRITE) || \
    false)

static inline void trace_pl031_write(uint32_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_PL031_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 17 "../xemu/hw/rtc/trace-events"
            qemu_log("pl031_write " "addr 0x%08x value 0x%08x" "\n", addr, value);
#line 200 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_PL031_ALARM_RAISED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL031_ALARM_RAISED) || \
    false)

static inline void trace_pl031_alarm_raised(void)
{
    if (trace_event_get_state(TRACE_PL031_ALARM_RAISED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 18 "../xemu/hw/rtc/trace-events"
            qemu_log("pl031_alarm_raised " "alarm raised" "\n");
#line 215 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_PL031_SET_ALARM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL031_SET_ALARM) || \
    false)

static inline void trace_pl031_set_alarm(uint32_t ticks)
{
    if (trace_event_get_state(TRACE_PL031_SET_ALARM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 19 "../xemu/hw/rtc/trace-events"
            qemu_log("pl031_set_alarm " "alarm set for %u ticks" "\n", ticks);
#line 230 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_ASPEED_RTC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_RTC_READ) || \
    false)

static inline void trace_aspeed_rtc_read(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_RTC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 22 "../xemu/hw/rtc/trace-events"
            qemu_log("aspeed_rtc_read " "addr 0x%02" PRIx64 " value 0x%08" PRIx64 "\n", addr, value);
#line 245 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_ASPEED_RTC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_RTC_WRITE) || \
    false)

static inline void trace_aspeed_rtc_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_RTC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 23 "../xemu/hw/rtc/trace-events"
            qemu_log("aspeed_rtc_write " "addr 0x%02" PRIx64 " value 0x%08" PRIx64 "\n", addr, value);
#line 260 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_DS1338_RECV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DS1338_RECV) || \
    false)

static inline void trace_ds1338_recv(uint32_t addr, uint8_t value)
{
    if (trace_event_get_state(TRACE_DS1338_RECV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 26 "../xemu/hw/rtc/trace-events"
            qemu_log("ds1338_recv " "[0x%" PRIx32 "] -> 0x%02" PRIx8 "\n", addr, value);
#line 275 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_DS1338_SEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DS1338_SEND) || \
    false)

static inline void trace_ds1338_send(uint32_t addr, uint8_t value)
{
    if (trace_event_get_state(TRACE_DS1338_SEND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 27 "../xemu/hw/rtc/trace-events"
            qemu_log("ds1338_send " "[0x%" PRIx32 "] <- 0x%02" PRIx8 "\n", addr, value);
#line 290 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_M48TXX_NVRAM_IO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_M48TXX_NVRAM_IO_READ) || \
    false)

static inline void trace_m48txx_nvram_io_read(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_M48TXX_NVRAM_IO_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 30 "../xemu/hw/rtc/trace-events"
            qemu_log("m48txx_nvram_io_read " "io read addr:0x%04" PRIx64 " value:0x%02" PRIx64 "\n", addr, value);
#line 305 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_M48TXX_NVRAM_IO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_M48TXX_NVRAM_IO_WRITE) || \
    false)

static inline void trace_m48txx_nvram_io_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_M48TXX_NVRAM_IO_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 31 "../xemu/hw/rtc/trace-events"
            qemu_log("m48txx_nvram_io_write " "io write addr:0x%04" PRIx64 " value:0x%02" PRIx64 "\n", addr, value);
#line 320 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_M48TXX_NVRAM_MEM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_M48TXX_NVRAM_MEM_READ) || \
    false)

static inline void trace_m48txx_nvram_mem_read(uint32_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_M48TXX_NVRAM_MEM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 32 "../xemu/hw/rtc/trace-events"
            qemu_log("m48txx_nvram_mem_read " "mem read addr:0x%04x value:0x%02x" "\n", addr, value);
#line 335 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_M48TXX_NVRAM_MEM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_M48TXX_NVRAM_MEM_WRITE) || \
    false)

static inline void trace_m48txx_nvram_mem_write(uint32_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_M48TXX_NVRAM_MEM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 33 "../xemu/hw/rtc/trace-events"
            qemu_log("m48txx_nvram_mem_write " "mem write addr:0x%04x value:0x%02x" "\n", addr, value);
#line 350 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_MC146818_RTC_IOPORT_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MC146818_RTC_IOPORT_READ) || \
    false)

static inline void trace_mc146818_rtc_ioport_read(uint8_t addr, uint8_t value)
{
    if (trace_event_get_state(TRACE_MC146818_RTC_IOPORT_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 36 "../xemu/hw/rtc/trace-events"
            qemu_log("mc146818_rtc_ioport_read " "[0x%02" PRIx8 "] -> 0x%02" PRIx8 "\n", addr, value);
#line 365 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_MC146818_RTC_IOPORT_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MC146818_RTC_IOPORT_WRITE) || \
    false)

static inline void trace_mc146818_rtc_ioport_write(uint8_t addr, uint8_t value)
{
    if (trace_event_get_state(TRACE_MC146818_RTC_IOPORT_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 37 "../xemu/hw/rtc/trace-events"
            qemu_log("mc146818_rtc_ioport_write " "[0x%02" PRIx8 "] <- 0x%02" PRIx8 "\n", addr, value);
#line 380 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_GOLDFISH_RTC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_RTC_READ) || \
    false)

static inline void trace_goldfish_rtc_read(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_GOLDFISH_RTC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 40 "../xemu/hw/rtc/trace-events"
            qemu_log("goldfish_rtc_read " "addr 0x%02" PRIx64 " value 0x%08" PRIx64 "\n", addr, value);
#line 395 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_GOLDFISH_RTC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_RTC_WRITE) || \
    false)

static inline void trace_goldfish_rtc_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_GOLDFISH_RTC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 41 "../xemu/hw/rtc/trace-events"
            qemu_log("goldfish_rtc_write " "addr 0x%02" PRIx64 " value 0x%08" PRIx64 "\n", addr, value);
#line 410 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_RS5C372_RECV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RS5C372_RECV) || \
    false)

static inline void trace_rs5c372_recv(uint32_t addr, uint8_t value)
{
    if (trace_event_get_state(TRACE_RS5C372_RECV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 44 "../xemu/hw/rtc/trace-events"
            qemu_log("rs5c372_recv " "[0x%" PRIx32 "] -> 0x%02" PRIx8 "\n", addr, value);
#line 425 "trace/trace-hw_rtc.h"
        }
    }
}

#define TRACE_RS5C372_SEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RS5C372_SEND) || \
    false)

static inline void trace_rs5c372_send(uint32_t addr, uint8_t value)
{
    if (trace_event_get_state(TRACE_RS5C372_SEND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 45 "../xemu/hw/rtc/trace-events"
            qemu_log("rs5c372_send " "[0x%" PRIx32 "] <- 0x%02" PRIx8 "\n", addr, value);
#line 440 "trace/trace-hw_rtc.h"
        }
    }
}
#endif /* TRACE_HW_RTC_GENERATED_TRACERS_H */
