/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_HW_TIMER_GENERATED_TRACERS_H
#define TRACE_HW_TIMER_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_SLAVIO_TIMER_GET_OUT_EVENT;
extern TraceEvent _TRACE_SLAVIO_TIMER_IRQ_EVENT;
extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_READL_INVALID_EVENT;
extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_READL_EVENT;
extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_EVENT;
extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_EVENT;
extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_EVENT;
extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_EVENT;
extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_EVENT;
extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_EVENT;
extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_EVENT;
extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_EVENT;
extern TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_EVENT;
extern TraceEvent _TRACE_GRLIB_GPTIMER_ENABLE_EVENT;
extern TraceEvent _TRACE_GRLIB_GPTIMER_DISABLED_EVENT;
extern TraceEvent _TRACE_GRLIB_GPTIMER_RESTART_EVENT;
extern TraceEvent _TRACE_GRLIB_GPTIMER_SET_SCALER_EVENT;
extern TraceEvent _TRACE_GRLIB_GPTIMER_HIT_EVENT;
extern TraceEvent _TRACE_GRLIB_GPTIMER_READL_EVENT;
extern TraceEvent _TRACE_GRLIB_GPTIMER_WRITEL_EVENT;
extern TraceEvent _TRACE_ASPEED_TIMER_CTRL_ENABLE_EVENT;
extern TraceEvent _TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_EVENT;
extern TraceEvent _TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_EVENT;
extern TraceEvent _TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_EVENT;
extern TraceEvent _TRACE_ASPEED_TIMER_SET_CTRL2_EVENT;
extern TraceEvent _TRACE_ASPEED_TIMER_SET_VALUE_EVENT;
extern TraceEvent _TRACE_ASPEED_TIMER_READ_EVENT;
extern TraceEvent _TRACE_SYSTICK_RELOAD_EVENT;
extern TraceEvent _TRACE_SYSTICK_TIMER_TICK_EVENT;
extern TraceEvent _TRACE_SYSTICK_READ_EVENT;
extern TraceEvent _TRACE_SYSTICK_WRITE_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_TIMER_READ_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_TIMER_WRITE_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_TIMER_RESET_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_DUALTIMER_READ_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_DUALTIMER_WRITE_EVENT;
extern TraceEvent _TRACE_CMSDK_APB_DUALTIMER_RESET_EVENT;
extern TraceEvent _TRACE_PIT_IOPORT_READ_EVENT;
extern TraceEvent _TRACE_PIT_IOPORT_WRITE_EVENT;
extern TraceEvent _TRACE_IMX_GPT_SET_FREQ_EVENT;
extern TraceEvent _TRACE_IMX_GPT_READ_EVENT;
extern TraceEvent _TRACE_IMX_GPT_WRITE_EVENT;
extern TraceEvent _TRACE_IMX_GPT_TIMEOUT_EVENT;
extern TraceEvent _TRACE_NPCM7XX_TIMER_READ_EVENT;
extern TraceEvent _TRACE_NPCM7XX_TIMER_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_TIMER_IRQ_EVENT;
extern TraceEvent _TRACE_NRF51_TIMER_READ_EVENT;
extern TraceEvent _TRACE_NRF51_TIMER_WRITE_EVENT;
extern TraceEvent _TRACE_NRF51_TIMER_SET_COUNT_EVENT;
extern TraceEvent _TRACE_BCM2835_SYSTMR_TIMER_EXPIRED_EVENT;
extern TraceEvent _TRACE_BCM2835_SYSTMR_IRQ_ACK_EVENT;
extern TraceEvent _TRACE_BCM2835_SYSTMR_READ_EVENT;
extern TraceEvent _TRACE_BCM2835_SYSTMR_WRITE_EVENT;
extern TraceEvent _TRACE_BCM2835_SYSTMR_RUN_EVENT;
extern TraceEvent _TRACE_AVR_TIMER16_READ_EVENT;
extern TraceEvent _TRACE_AVR_TIMER16_READ_IFR_EVENT;
extern TraceEvent _TRACE_AVR_TIMER16_READ_IMSK_EVENT;
extern TraceEvent _TRACE_AVR_TIMER16_WRITE_EVENT;
extern TraceEvent _TRACE_AVR_TIMER16_WRITE_IMSK_EVENT;
extern TraceEvent _TRACE_AVR_TIMER16_INTERRUPT_COUNT_EVENT;
extern TraceEvent _TRACE_AVR_TIMER16_INTERRUPT_OVERFLOW_EVENT;
extern TraceEvent _TRACE_AVR_TIMER16_NEXT_ALARM_EVENT;
extern TraceEvent _TRACE_AVR_TIMER16_CLKSRC_UPDATE_EVENT;
extern TraceEvent _TRACE_SSE_COUNTER_CONTROL_READ_EVENT;
extern TraceEvent _TRACE_SSE_COUNTER_CONTROL_WRITE_EVENT;
extern TraceEvent _TRACE_SSE_COUNTER_STATUS_READ_EVENT;
extern TraceEvent _TRACE_SSE_COUNTER_STATUS_WRITE_EVENT;
extern TraceEvent _TRACE_SSE_COUNTER_RESET_EVENT;
extern TraceEvent _TRACE_SSE_TIMER_READ_EVENT;
extern TraceEvent _TRACE_SSE_TIMER_WRITE_EVENT;
extern TraceEvent _TRACE_SSE_TIMER_RESET_EVENT;
extern TraceEvent _TRACE_SIFIVE_PWM_SET_ALARM_EVENT;
extern TraceEvent _TRACE_SIFIVE_PWM_INTERRUPT_EVENT;
extern TraceEvent _TRACE_SIFIVE_PWM_READ_EVENT;
extern TraceEvent _TRACE_SIFIVE_PWM_WRITE_EVENT;
extern TraceEvent _TRACE_SH_TIMER_START_STOP_EVENT;
extern TraceEvent _TRACE_SH_TIMER_READ_EVENT;
extern TraceEvent _TRACE_SH_TIMER_WRITE_EVENT;
extern TraceEvent _TRACE_HPET_TIMER_ID_OUT_OF_RANGE_EVENT;
extern TraceEvent _TRACE_HPET_INVALID_HPET_CFG_EVENT;
extern TraceEvent _TRACE_HPET_RAM_READ_EVENT;
extern TraceEvent _TRACE_HPET_RAM_READ_READING_COUNTER_EVENT;
extern TraceEvent _TRACE_HPET_RAM_READ_INVALID_EVENT;
extern TraceEvent _TRACE_HPET_RAM_WRITE_EVENT;
extern TraceEvent _TRACE_HPET_RAM_WRITE_TIMER_ID_EVENT;
extern TraceEvent _TRACE_HPET_RAM_WRITE_TN_CFG_EVENT;
extern TraceEvent _TRACE_HPET_RAM_WRITE_TN_CMP_EVENT;
extern TraceEvent _TRACE_HPET_RAM_WRITE_INVALID_TN_CMP_EVENT;
extern TraceEvent _TRACE_HPET_RAM_WRITE_INVALID_EVENT;
extern TraceEvent _TRACE_HPET_RAM_WRITE_COUNTER_WRITE_WHILE_ENABLED_EVENT;
extern TraceEvent _TRACE_HPET_RAM_WRITE_COUNTER_WRITTEN_EVENT;
extern uint16_t _TRACE_SLAVIO_TIMER_GET_OUT_DSTATE;
extern uint16_t _TRACE_SLAVIO_TIMER_IRQ_DSTATE;
extern uint16_t _TRACE_SLAVIO_TIMER_MEM_READL_INVALID_DSTATE;
extern uint16_t _TRACE_SLAVIO_TIMER_MEM_READL_DSTATE;
extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_DSTATE;
extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_DSTATE;
extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_DSTATE;
extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_DSTATE;
extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_DSTATE;
extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_DSTATE;
extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_DSTATE;
extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_DSTATE;
extern uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_DSTATE;
extern uint16_t _TRACE_GRLIB_GPTIMER_ENABLE_DSTATE;
extern uint16_t _TRACE_GRLIB_GPTIMER_DISABLED_DSTATE;
extern uint16_t _TRACE_GRLIB_GPTIMER_RESTART_DSTATE;
extern uint16_t _TRACE_GRLIB_GPTIMER_SET_SCALER_DSTATE;
extern uint16_t _TRACE_GRLIB_GPTIMER_HIT_DSTATE;
extern uint16_t _TRACE_GRLIB_GPTIMER_READL_DSTATE;
extern uint16_t _TRACE_GRLIB_GPTIMER_WRITEL_DSTATE;
extern uint16_t _TRACE_ASPEED_TIMER_CTRL_ENABLE_DSTATE;
extern uint16_t _TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_DSTATE;
extern uint16_t _TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_DSTATE;
extern uint16_t _TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_DSTATE;
extern uint16_t _TRACE_ASPEED_TIMER_SET_CTRL2_DSTATE;
extern uint16_t _TRACE_ASPEED_TIMER_SET_VALUE_DSTATE;
extern uint16_t _TRACE_ASPEED_TIMER_READ_DSTATE;
extern uint16_t _TRACE_SYSTICK_RELOAD_DSTATE;
extern uint16_t _TRACE_SYSTICK_TIMER_TICK_DSTATE;
extern uint16_t _TRACE_SYSTICK_READ_DSTATE;
extern uint16_t _TRACE_SYSTICK_WRITE_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_TIMER_READ_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_TIMER_WRITE_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_TIMER_RESET_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_DUALTIMER_READ_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_DUALTIMER_WRITE_DSTATE;
extern uint16_t _TRACE_CMSDK_APB_DUALTIMER_RESET_DSTATE;
extern uint16_t _TRACE_PIT_IOPORT_READ_DSTATE;
extern uint16_t _TRACE_PIT_IOPORT_WRITE_DSTATE;
extern uint16_t _TRACE_IMX_GPT_SET_FREQ_DSTATE;
extern uint16_t _TRACE_IMX_GPT_READ_DSTATE;
extern uint16_t _TRACE_IMX_GPT_WRITE_DSTATE;
extern uint16_t _TRACE_IMX_GPT_TIMEOUT_DSTATE;
extern uint16_t _TRACE_NPCM7XX_TIMER_READ_DSTATE;
extern uint16_t _TRACE_NPCM7XX_TIMER_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_TIMER_IRQ_DSTATE;
extern uint16_t _TRACE_NRF51_TIMER_READ_DSTATE;
extern uint16_t _TRACE_NRF51_TIMER_WRITE_DSTATE;
extern uint16_t _TRACE_NRF51_TIMER_SET_COUNT_DSTATE;
extern uint16_t _TRACE_BCM2835_SYSTMR_TIMER_EXPIRED_DSTATE;
extern uint16_t _TRACE_BCM2835_SYSTMR_IRQ_ACK_DSTATE;
extern uint16_t _TRACE_BCM2835_SYSTMR_READ_DSTATE;
extern uint16_t _TRACE_BCM2835_SYSTMR_WRITE_DSTATE;
extern uint16_t _TRACE_BCM2835_SYSTMR_RUN_DSTATE;
extern uint16_t _TRACE_AVR_TIMER16_READ_DSTATE;
extern uint16_t _TRACE_AVR_TIMER16_READ_IFR_DSTATE;
extern uint16_t _TRACE_AVR_TIMER16_READ_IMSK_DSTATE;
extern uint16_t _TRACE_AVR_TIMER16_WRITE_DSTATE;
extern uint16_t _TRACE_AVR_TIMER16_WRITE_IMSK_DSTATE;
extern uint16_t _TRACE_AVR_TIMER16_INTERRUPT_COUNT_DSTATE;
extern uint16_t _TRACE_AVR_TIMER16_INTERRUPT_OVERFLOW_DSTATE;
extern uint16_t _TRACE_AVR_TIMER16_NEXT_ALARM_DSTATE;
extern uint16_t _TRACE_AVR_TIMER16_CLKSRC_UPDATE_DSTATE;
extern uint16_t _TRACE_SSE_COUNTER_CONTROL_READ_DSTATE;
extern uint16_t _TRACE_SSE_COUNTER_CONTROL_WRITE_DSTATE;
extern uint16_t _TRACE_SSE_COUNTER_STATUS_READ_DSTATE;
extern uint16_t _TRACE_SSE_COUNTER_STATUS_WRITE_DSTATE;
extern uint16_t _TRACE_SSE_COUNTER_RESET_DSTATE;
extern uint16_t _TRACE_SSE_TIMER_READ_DSTATE;
extern uint16_t _TRACE_SSE_TIMER_WRITE_DSTATE;
extern uint16_t _TRACE_SSE_TIMER_RESET_DSTATE;
extern uint16_t _TRACE_SIFIVE_PWM_SET_ALARM_DSTATE;
extern uint16_t _TRACE_SIFIVE_PWM_INTERRUPT_DSTATE;
extern uint16_t _TRACE_SIFIVE_PWM_READ_DSTATE;
extern uint16_t _TRACE_SIFIVE_PWM_WRITE_DSTATE;
extern uint16_t _TRACE_SH_TIMER_START_STOP_DSTATE;
extern uint16_t _TRACE_SH_TIMER_READ_DSTATE;
extern uint16_t _TRACE_SH_TIMER_WRITE_DSTATE;
extern uint16_t _TRACE_HPET_TIMER_ID_OUT_OF_RANGE_DSTATE;
extern uint16_t _TRACE_HPET_INVALID_HPET_CFG_DSTATE;
extern uint16_t _TRACE_HPET_RAM_READ_DSTATE;
extern uint16_t _TRACE_HPET_RAM_READ_READING_COUNTER_DSTATE;
extern uint16_t _TRACE_HPET_RAM_READ_INVALID_DSTATE;
extern uint16_t _TRACE_HPET_RAM_WRITE_DSTATE;
extern uint16_t _TRACE_HPET_RAM_WRITE_TIMER_ID_DSTATE;
extern uint16_t _TRACE_HPET_RAM_WRITE_TN_CFG_DSTATE;
extern uint16_t _TRACE_HPET_RAM_WRITE_TN_CMP_DSTATE;
extern uint16_t _TRACE_HPET_RAM_WRITE_INVALID_TN_CMP_DSTATE;
extern uint16_t _TRACE_HPET_RAM_WRITE_INVALID_DSTATE;
extern uint16_t _TRACE_HPET_RAM_WRITE_COUNTER_WRITE_WHILE_ENABLED_DSTATE;
extern uint16_t _TRACE_HPET_RAM_WRITE_COUNTER_WRITTEN_DSTATE;
#define TRACE_SLAVIO_TIMER_GET_OUT_ENABLED 1
#define TRACE_SLAVIO_TIMER_IRQ_ENABLED 1
#define TRACE_SLAVIO_TIMER_MEM_READL_INVALID_ENABLED 1
#define TRACE_SLAVIO_TIMER_MEM_READL_ENABLED 1
#define TRACE_SLAVIO_TIMER_MEM_WRITEL_ENABLED 1
#define TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_ENABLED 1
#define TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_ENABLED 1
#define TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_ENABLED 1
#define TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_ENABLED 1
#define TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_ENABLED 1
#define TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_ENABLED 1
#define TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_ENABLED 1
#define TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_ENABLED 1
#define TRACE_GRLIB_GPTIMER_ENABLE_ENABLED 1
#define TRACE_GRLIB_GPTIMER_DISABLED_ENABLED 1
#define TRACE_GRLIB_GPTIMER_RESTART_ENABLED 1
#define TRACE_GRLIB_GPTIMER_SET_SCALER_ENABLED 1
#define TRACE_GRLIB_GPTIMER_HIT_ENABLED 1
#define TRACE_GRLIB_GPTIMER_READL_ENABLED 1
#define TRACE_GRLIB_GPTIMER_WRITEL_ENABLED 1
#define TRACE_ASPEED_TIMER_CTRL_ENABLE_ENABLED 1
#define TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_ENABLED 1
#define TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_ENABLED 1
#define TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_ENABLED 1
#define TRACE_ASPEED_TIMER_SET_CTRL2_ENABLED 1
#define TRACE_ASPEED_TIMER_SET_VALUE_ENABLED 1
#define TRACE_ASPEED_TIMER_READ_ENABLED 1
#define TRACE_SYSTICK_RELOAD_ENABLED 1
#define TRACE_SYSTICK_TIMER_TICK_ENABLED 1
#define TRACE_SYSTICK_READ_ENABLED 1
#define TRACE_SYSTICK_WRITE_ENABLED 1
#define TRACE_CMSDK_APB_TIMER_READ_ENABLED 1
#define TRACE_CMSDK_APB_TIMER_WRITE_ENABLED 1
#define TRACE_CMSDK_APB_TIMER_RESET_ENABLED 1
#define TRACE_CMSDK_APB_DUALTIMER_READ_ENABLED 1
#define TRACE_CMSDK_APB_DUALTIMER_WRITE_ENABLED 1
#define TRACE_CMSDK_APB_DUALTIMER_RESET_ENABLED 1
#define TRACE_PIT_IOPORT_READ_ENABLED 1
#define TRACE_PIT_IOPORT_WRITE_ENABLED 1
#define TRACE_IMX_GPT_SET_FREQ_ENABLED 1
#define TRACE_IMX_GPT_READ_ENABLED 1
#define TRACE_IMX_GPT_WRITE_ENABLED 1
#define TRACE_IMX_GPT_TIMEOUT_ENABLED 1
#define TRACE_NPCM7XX_TIMER_READ_ENABLED 1
#define TRACE_NPCM7XX_TIMER_WRITE_ENABLED 1
#define TRACE_NPCM7XX_TIMER_IRQ_ENABLED 1
#define TRACE_NRF51_TIMER_READ_ENABLED 1
#define TRACE_NRF51_TIMER_WRITE_ENABLED 1
#define TRACE_NRF51_TIMER_SET_COUNT_ENABLED 1
#define TRACE_BCM2835_SYSTMR_TIMER_EXPIRED_ENABLED 1
#define TRACE_BCM2835_SYSTMR_IRQ_ACK_ENABLED 1
#define TRACE_BCM2835_SYSTMR_READ_ENABLED 1
#define TRACE_BCM2835_SYSTMR_WRITE_ENABLED 1
#define TRACE_BCM2835_SYSTMR_RUN_ENABLED 1
#define TRACE_AVR_TIMER16_READ_ENABLED 1
#define TRACE_AVR_TIMER16_READ_IFR_ENABLED 1
#define TRACE_AVR_TIMER16_READ_IMSK_ENABLED 1
#define TRACE_AVR_TIMER16_WRITE_ENABLED 1
#define TRACE_AVR_TIMER16_WRITE_IMSK_ENABLED 1
#define TRACE_AVR_TIMER16_INTERRUPT_COUNT_ENABLED 1
#define TRACE_AVR_TIMER16_INTERRUPT_OVERFLOW_ENABLED 1
#define TRACE_AVR_TIMER16_NEXT_ALARM_ENABLED 1
#define TRACE_AVR_TIMER16_CLKSRC_UPDATE_ENABLED 1
#define TRACE_SSE_COUNTER_CONTROL_READ_ENABLED 1
#define TRACE_SSE_COUNTER_CONTROL_WRITE_ENABLED 1
#define TRACE_SSE_COUNTER_STATUS_READ_ENABLED 1
#define TRACE_SSE_COUNTER_STATUS_WRITE_ENABLED 1
#define TRACE_SSE_COUNTER_RESET_ENABLED 1
#define TRACE_SSE_TIMER_READ_ENABLED 1
#define TRACE_SSE_TIMER_WRITE_ENABLED 1
#define TRACE_SSE_TIMER_RESET_ENABLED 1
#define TRACE_SIFIVE_PWM_SET_ALARM_ENABLED 1
#define TRACE_SIFIVE_PWM_INTERRUPT_ENABLED 1
#define TRACE_SIFIVE_PWM_READ_ENABLED 1
#define TRACE_SIFIVE_PWM_WRITE_ENABLED 1
#define TRACE_SH_TIMER_START_STOP_ENABLED 1
#define TRACE_SH_TIMER_READ_ENABLED 1
#define TRACE_SH_TIMER_WRITE_ENABLED 1
#define TRACE_HPET_TIMER_ID_OUT_OF_RANGE_ENABLED 1
#define TRACE_HPET_INVALID_HPET_CFG_ENABLED 1
#define TRACE_HPET_RAM_READ_ENABLED 1
#define TRACE_HPET_RAM_READ_READING_COUNTER_ENABLED 1
#define TRACE_HPET_RAM_READ_INVALID_ENABLED 1
#define TRACE_HPET_RAM_WRITE_ENABLED 1
#define TRACE_HPET_RAM_WRITE_TIMER_ID_ENABLED 1
#define TRACE_HPET_RAM_WRITE_TN_CFG_ENABLED 1
#define TRACE_HPET_RAM_WRITE_TN_CMP_ENABLED 1
#define TRACE_HPET_RAM_WRITE_INVALID_TN_CMP_ENABLED 1
#define TRACE_HPET_RAM_WRITE_INVALID_ENABLED 1
#define TRACE_HPET_RAM_WRITE_COUNTER_WRITE_WHILE_ENABLED_ENABLED 1
#define TRACE_HPET_RAM_WRITE_COUNTER_WRITTEN_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_SLAVIO_TIMER_GET_OUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_GET_OUT) || \
    false)

static inline void trace_slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_GET_OUT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 4 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_get_out " "limit 0x%"PRIx64" count 0x%x0x%08x" "\n", limit, counthigh, count);
#line 296 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SLAVIO_TIMER_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_IRQ) || \
    false)

static inline void trace_slavio_timer_irq(uint32_t counthigh, uint32_t count)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_irq " "callback: count 0x%x0x%08x" "\n", counthigh, count);
#line 311 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SLAVIO_TIMER_MEM_READL_INVALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_READL_INVALID) || \
    false)

static inline void trace_slavio_timer_mem_readl_invalid(uint64_t addr)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_READL_INVALID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 6 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_mem_readl_invalid " "invalid read address 0x%"PRIx64 "\n", addr);
#line 326 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SLAVIO_TIMER_MEM_READL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_READL) || \
    false)

static inline void trace_slavio_timer_mem_readl(uint64_t addr, uint32_t ret)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_READL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 7 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_mem_readl " "read 0x%"PRIx64" = 0x%08x" "\n", addr, ret);
#line 341 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SLAVIO_TIMER_MEM_WRITEL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL) || \
    false)

static inline void trace_slavio_timer_mem_writel(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 8 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_mem_writel " "write 0x%"PRIx64" = 0x%08x" "\n", addr, val);
#line 356 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT) || \
    false)

static inline void trace_slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 9 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_mem_writel_limit " "processor %d user timer set to 0x%016"PRIx64 "\n", timer_index, count);
#line 371 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID) || \
    false)

static inline void trace_slavio_timer_mem_writel_counter_invalid(void)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 10 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_mem_writel_counter_invalid " "not user timer" "\n");
#line 386 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START) || \
    false)

static inline void trace_slavio_timer_mem_writel_status_start(unsigned int timer_index)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 11 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_mem_writel_status_start " "processor %d user timer started" "\n", timer_index);
#line 401 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP) || \
    false)

static inline void trace_slavio_timer_mem_writel_status_stop(unsigned int timer_index)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 12 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_mem_writel_status_stop " "processor %d user timer stopped" "\n", timer_index);
#line 416 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER) || \
    false)

static inline void trace_slavio_timer_mem_writel_mode_user(unsigned int timer_index)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 13 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_mem_writel_mode_user " "processor %d changed from counter to user timer" "\n", timer_index);
#line 431 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER) || \
    false)

static inline void trace_slavio_timer_mem_writel_mode_counter(unsigned int timer_index)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 14 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_mem_writel_mode_counter " "processor %d changed from user timer to counter" "\n", timer_index);
#line 446 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID) || \
    false)

static inline void trace_slavio_timer_mem_writel_mode_invalid(void)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_mem_writel_mode_invalid " "not system timer" "\n");
#line 461 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID) || \
    false)

static inline void trace_slavio_timer_mem_writel_invalid(uint64_t addr)
{
    if (trace_event_get_state(TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 16 "../xemu/hw/timer/trace-events"
            qemu_log("slavio_timer_mem_writel_invalid " "invalid write address 0x%"PRIx64 "\n", addr);
#line 476 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_GRLIB_GPTIMER_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_ENABLE) || \
    false)

static inline void trace_grlib_gptimer_enable(int id, uint32_t count)
{
    if (trace_event_get_state(TRACE_GRLIB_GPTIMER_ENABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 19 "../xemu/hw/timer/trace-events"
            qemu_log("grlib_gptimer_enable " "timer:%d set count 0x%x and run" "\n", id, count);
#line 491 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_GRLIB_GPTIMER_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_DISABLED) || \
    false)

static inline void trace_grlib_gptimer_disabled(int id, uint32_t config)
{
    if (trace_event_get_state(TRACE_GRLIB_GPTIMER_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 20 "../xemu/hw/timer/trace-events"
            qemu_log("grlib_gptimer_disabled " "timer:%d Timer disable config 0x%x" "\n", id, config);
#line 506 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_GRLIB_GPTIMER_RESTART_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_RESTART) || \
    false)

static inline void trace_grlib_gptimer_restart(int id, uint32_t reload)
{
    if (trace_event_get_state(TRACE_GRLIB_GPTIMER_RESTART)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 21 "../xemu/hw/timer/trace-events"
            qemu_log("grlib_gptimer_restart " "timer:%d reload val: 0x%x" "\n", id, reload);
#line 521 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_GRLIB_GPTIMER_SET_SCALER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_SET_SCALER) || \
    false)

static inline void trace_grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq)
{
    if (trace_event_get_state(TRACE_GRLIB_GPTIMER_SET_SCALER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 22 "../xemu/hw/timer/trace-events"
            qemu_log("grlib_gptimer_set_scaler " "scaler:0x%x freq:%uHz" "\n", scaler, freq);
#line 536 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_GRLIB_GPTIMER_HIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_HIT) || \
    false)

static inline void trace_grlib_gptimer_hit(int id)
{
    if (trace_event_get_state(TRACE_GRLIB_GPTIMER_HIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 23 "../xemu/hw/timer/trace-events"
            qemu_log("grlib_gptimer_hit " "timer:%d HIT" "\n", id);
#line 551 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_GRLIB_GPTIMER_READL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_READL) || \
    false)

static inline void trace_grlib_gptimer_readl(int id, uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_GRLIB_GPTIMER_READL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 24 "../xemu/hw/timer/trace-events"
            qemu_log("grlib_gptimer_readl " "timer:%d addr 0x%"PRIx64" 0x%x" "\n", id, addr, val);
#line 566 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_GRLIB_GPTIMER_WRITEL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_GPTIMER_WRITEL) || \
    false)

static inline void trace_grlib_gptimer_writel(int id, uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_GRLIB_GPTIMER_WRITEL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 25 "../xemu/hw/timer/trace-events"
            qemu_log("grlib_gptimer_writel " "timer:%d addr 0x%"PRIx64" 0x%x" "\n", id, addr, val);
#line 581 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_ASPEED_TIMER_CTRL_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_CTRL_ENABLE) || \
    false)

static inline void trace_aspeed_timer_ctrl_enable(uint8_t i, bool enable)
{
    if (trace_event_get_state(TRACE_ASPEED_TIMER_CTRL_ENABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 28 "../xemu/hw/timer/trace-events"
            qemu_log("aspeed_timer_ctrl_enable " "Timer %" PRIu8 ": %d" "\n", i, enable);
#line 596 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK) || \
    false)

static inline void trace_aspeed_timer_ctrl_external_clock(uint8_t i, bool enable)
{
    if (trace_event_get_state(TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 29 "../xemu/hw/timer/trace-events"
            qemu_log("aspeed_timer_ctrl_external_clock " "Timer %" PRIu8 ": %d" "\n", i, enable);
#line 611 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT) || \
    false)

static inline void trace_aspeed_timer_ctrl_overflow_interrupt(uint8_t i, bool enable)
{
    if (trace_event_get_state(TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 30 "../xemu/hw/timer/trace-events"
            qemu_log("aspeed_timer_ctrl_overflow_interrupt " "Timer %" PRIu8 ": %d" "\n", i, enable);
#line 626 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE) || \
    false)

static inline void trace_aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable)
{
    if (trace_event_get_state(TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 31 "../xemu/hw/timer/trace-events"
            qemu_log("aspeed_timer_ctrl_pulse_enable " "Timer %" PRIu8 ": %d" "\n", i, enable);
#line 641 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_ASPEED_TIMER_SET_CTRL2_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_SET_CTRL2) || \
    false)

static inline void trace_aspeed_timer_set_ctrl2(uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_TIMER_SET_CTRL2)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 32 "../xemu/hw/timer/trace-events"
            qemu_log("aspeed_timer_set_ctrl2 " "Value: 0x%" PRIx32 "\n", value);
#line 656 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_ASPEED_TIMER_SET_VALUE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_SET_VALUE) || \
    false)

static inline void trace_aspeed_timer_set_value(int timer, int reg, uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_TIMER_SET_VALUE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 33 "../xemu/hw/timer/trace-events"
            qemu_log("aspeed_timer_set_value " "Timer %d register %d: 0x%" PRIx32 "\n", timer, reg, value);
#line 671 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_ASPEED_TIMER_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_TIMER_READ) || \
    false)

static inline void trace_aspeed_timer_read(uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_TIMER_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 34 "../xemu/hw/timer/trace-events"
            qemu_log("aspeed_timer_read " "From 0x%" PRIx64 ": 0x%" PRIx64 "\n", offset, value);
#line 686 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SYSTICK_RELOAD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SYSTICK_RELOAD) || \
    false)

static inline void trace_systick_reload(void)
{
    if (trace_event_get_state(TRACE_SYSTICK_RELOAD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 37 "../xemu/hw/timer/trace-events"
            qemu_log("systick_reload " "systick reload" "\n");
#line 701 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SYSTICK_TIMER_TICK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SYSTICK_TIMER_TICK) || \
    false)

static inline void trace_systick_timer_tick(void)
{
    if (trace_event_get_state(TRACE_SYSTICK_TIMER_TICK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 38 "../xemu/hw/timer/trace-events"
            qemu_log("systick_timer_tick " "systick tick" "\n");
#line 716 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SYSTICK_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SYSTICK_READ) || \
    false)

static inline void trace_systick_read(uint64_t addr, uint32_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_SYSTICK_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 39 "../xemu/hw/timer/trace-events"
            qemu_log("systick_read " "systick read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n", addr, value, size);
#line 731 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SYSTICK_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SYSTICK_WRITE) || \
    false)

static inline void trace_systick_write(uint64_t addr, uint32_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_SYSTICK_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 40 "../xemu/hw/timer/trace-events"
            qemu_log("systick_write " "systick write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n", addr, value, size);
#line 746 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_CMSDK_APB_TIMER_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_TIMER_READ) || \
    false)

static inline void trace_cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_TIMER_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 43 "../xemu/hw/timer/trace-events"
            qemu_log("cmsdk_apb_timer_read " "CMSDK APB timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 761 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_CMSDK_APB_TIMER_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_TIMER_WRITE) || \
    false)

static inline void trace_cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_TIMER_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 44 "../xemu/hw/timer/trace-events"
            qemu_log("cmsdk_apb_timer_write " "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 776 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_CMSDK_APB_TIMER_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_TIMER_RESET) || \
    false)

static inline void trace_cmsdk_apb_timer_reset(void)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_TIMER_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 45 "../xemu/hw/timer/trace-events"
            qemu_log("cmsdk_apb_timer_reset " "CMSDK APB timer: reset" "\n");
#line 791 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_CMSDK_APB_DUALTIMER_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_DUALTIMER_READ) || \
    false)

static inline void trace_cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_DUALTIMER_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 48 "../xemu/hw/timer/trace-events"
            qemu_log("cmsdk_apb_dualtimer_read " "CMSDK APB dualtimer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 806 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_CMSDK_APB_DUALTIMER_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_DUALTIMER_WRITE) || \
    false)

static inline void trace_cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_DUALTIMER_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 49 "../xemu/hw/timer/trace-events"
            qemu_log("cmsdk_apb_dualtimer_write " "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 821 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_CMSDK_APB_DUALTIMER_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_DUALTIMER_RESET) || \
    false)

static inline void trace_cmsdk_apb_dualtimer_reset(void)
{
    if (trace_event_get_state(TRACE_CMSDK_APB_DUALTIMER_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 50 "../xemu/hw/timer/trace-events"
            qemu_log("cmsdk_apb_dualtimer_reset " "CMSDK APB dualtimer: reset" "\n");
#line 836 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_PIT_IOPORT_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PIT_IOPORT_READ) || \
    false)

static inline void trace_pit_ioport_read(uint8_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_PIT_IOPORT_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 53 "../xemu/hw/timer/trace-events"
            qemu_log("pit_ioport_read " "[0x%" PRIx8 "] -> 0x%" PRIx32 "\n", addr, value);
#line 851 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_PIT_IOPORT_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PIT_IOPORT_WRITE) || \
    false)

static inline void trace_pit_ioport_write(uint8_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_PIT_IOPORT_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 54 "../xemu/hw/timer/trace-events"
            qemu_log("pit_ioport_write " "[0x%" PRIx8 "] <- 0x%" PRIx32 "\n", addr, value);
#line 866 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_IMX_GPT_SET_FREQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_GPT_SET_FREQ) || \
    false)

static inline void trace_imx_gpt_set_freq(uint32_t clksrc, uint32_t freq)
{
    if (trace_event_get_state(TRACE_IMX_GPT_SET_FREQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 57 "../xemu/hw/timer/trace-events"
            qemu_log("imx_gpt_set_freq " "Setting clksrc %u to %u Hz" "\n", clksrc, freq);
#line 881 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_IMX_GPT_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_GPT_READ) || \
    false)

static inline void trace_imx_gpt_read(const char *name, uint64_t value)
{
    if (trace_event_get_state(TRACE_IMX_GPT_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 58 "../xemu/hw/timer/trace-events"
            qemu_log("imx_gpt_read " "%s -> 0x%08" PRIx64 "\n", name, value);
#line 896 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_IMX_GPT_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_GPT_WRITE) || \
    false)

static inline void trace_imx_gpt_write(const char *name, uint64_t value)
{
    if (trace_event_get_state(TRACE_IMX_GPT_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 59 "../xemu/hw/timer/trace-events"
            qemu_log("imx_gpt_write " "%s <- 0x%08" PRIx64 "\n", name, value);
#line 911 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_IMX_GPT_TIMEOUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_GPT_TIMEOUT) || \
    false)

static inline void trace_imx_gpt_timeout(void)
{
    if (trace_event_get_state(TRACE_IMX_GPT_TIMEOUT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 60 "../xemu/hw/timer/trace-events"
            qemu_log("imx_gpt_timeout " "" "\n");
#line 926 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_NPCM7XX_TIMER_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_TIMER_READ) || \
    false)

static inline void trace_npcm7xx_timer_read(const char *id, uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_TIMER_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 63 "../xemu/hw/timer/trace-events"
            qemu_log("npcm7xx_timer_read " " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 "\n", id, offset, value);
#line 941 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_NPCM7XX_TIMER_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_TIMER_WRITE) || \
    false)

static inline void trace_npcm7xx_timer_write(const char *id, uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_TIMER_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 64 "../xemu/hw/timer/trace-events"
            qemu_log("npcm7xx_timer_write " "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 "\n", id, offset, value);
#line 956 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_NPCM7XX_TIMER_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_TIMER_IRQ) || \
    false)

static inline void trace_npcm7xx_timer_irq(const char *id, int timer, int state)
{
    if (trace_event_get_state(TRACE_NPCM7XX_TIMER_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 65 "../xemu/hw/timer/trace-events"
            qemu_log("npcm7xx_timer_irq " "%s timer %d state %d" "\n", id, timer, state);
#line 971 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_NRF51_TIMER_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NRF51_TIMER_READ) || \
    false)

static inline void trace_nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_NRF51_TIMER_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 68 "../xemu/hw/timer/trace-events"
            qemu_log("nrf51_timer_read " "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n", timer_id, addr, value, size);
#line 986 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_NRF51_TIMER_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NRF51_TIMER_WRITE) || \
    false)

static inline void trace_nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_NRF51_TIMER_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 69 "../xemu/hw/timer/trace-events"
            qemu_log("nrf51_timer_write " "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n", timer_id, addr, value, size);
#line 1001 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_NRF51_TIMER_SET_COUNT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NRF51_TIMER_SET_COUNT) || \
    false)

static inline void trace_nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value)
{
    if (trace_event_get_state(TRACE_NRF51_TIMER_SET_COUNT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 70 "../xemu/hw/timer/trace-events"
            qemu_log("nrf51_timer_set_count " "timer %u counter %u count 0x%" PRIx32 "\n", timer_id, counter_id, value);
#line 1016 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_BCM2835_SYSTMR_TIMER_EXPIRED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_SYSTMR_TIMER_EXPIRED) || \
    false)

static inline void trace_bcm2835_systmr_timer_expired(unsigned id)
{
    if (trace_event_get_state(TRACE_BCM2835_SYSTMR_TIMER_EXPIRED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 73 "../xemu/hw/timer/trace-events"
            qemu_log("bcm2835_systmr_timer_expired " "timer #%u expired" "\n", id);
#line 1031 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_BCM2835_SYSTMR_IRQ_ACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_SYSTMR_IRQ_ACK) || \
    false)

static inline void trace_bcm2835_systmr_irq_ack(unsigned id)
{
    if (trace_event_get_state(TRACE_BCM2835_SYSTMR_IRQ_ACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 74 "../xemu/hw/timer/trace-events"
            qemu_log("bcm2835_systmr_irq_ack " "timer #%u acked" "\n", id);
#line 1046 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_BCM2835_SYSTMR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_SYSTMR_READ) || \
    false)

static inline void trace_bcm2835_systmr_read(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_BCM2835_SYSTMR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 75 "../xemu/hw/timer/trace-events"
            qemu_log("bcm2835_systmr_read " "timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data);
#line 1061 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_BCM2835_SYSTMR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_SYSTMR_WRITE) || \
    false)

static inline void trace_bcm2835_systmr_write(uint64_t offset, uint32_t data)
{
    if (trace_event_get_state(TRACE_BCM2835_SYSTMR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 76 "../xemu/hw/timer/trace-events"
            qemu_log("bcm2835_systmr_write " "timer write: offset 0x%" PRIx64 " data 0x%" PRIx32 "\n", offset, data);
#line 1076 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_BCM2835_SYSTMR_RUN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_SYSTMR_RUN) || \
    false)

static inline void trace_bcm2835_systmr_run(unsigned id, uint64_t delay_us)
{
    if (trace_event_get_state(TRACE_BCM2835_SYSTMR_RUN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 77 "../xemu/hw/timer/trace-events"
            qemu_log("bcm2835_systmr_run " "timer #%u expiring in %"PRIu64" us" "\n", id, delay_us);
#line 1091 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_AVR_TIMER16_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AVR_TIMER16_READ) || \
    false)

static inline void trace_avr_timer16_read(uint8_t addr, uint8_t value)
{
    if (trace_event_get_state(TRACE_AVR_TIMER16_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 80 "../xemu/hw/timer/trace-events"
            qemu_log("avr_timer16_read " "timer16 read addr:%u value:%u" "\n", addr, value);
#line 1106 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_AVR_TIMER16_READ_IFR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AVR_TIMER16_READ_IFR) || \
    false)

static inline void trace_avr_timer16_read_ifr(uint8_t value)
{
    if (trace_event_get_state(TRACE_AVR_TIMER16_READ_IFR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 81 "../xemu/hw/timer/trace-events"
            qemu_log("avr_timer16_read_ifr " "timer16 read addr:ifr value:%u" "\n", value);
#line 1121 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_AVR_TIMER16_READ_IMSK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AVR_TIMER16_READ_IMSK) || \
    false)

static inline void trace_avr_timer16_read_imsk(uint8_t value)
{
    if (trace_event_get_state(TRACE_AVR_TIMER16_READ_IMSK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 82 "../xemu/hw/timer/trace-events"
            qemu_log("avr_timer16_read_imsk " "timer16 read addr:imsk value:%u" "\n", value);
#line 1136 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_AVR_TIMER16_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AVR_TIMER16_WRITE) || \
    false)

static inline void trace_avr_timer16_write(uint8_t addr, uint8_t value)
{
    if (trace_event_get_state(TRACE_AVR_TIMER16_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 83 "../xemu/hw/timer/trace-events"
            qemu_log("avr_timer16_write " "timer16 write addr:%u value:%u" "\n", addr, value);
#line 1151 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_AVR_TIMER16_WRITE_IMSK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AVR_TIMER16_WRITE_IMSK) || \
    false)

static inline void trace_avr_timer16_write_imsk(uint8_t value)
{
    if (trace_event_get_state(TRACE_AVR_TIMER16_WRITE_IMSK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 84 "../xemu/hw/timer/trace-events"
            qemu_log("avr_timer16_write_imsk " "timer16 write addr:imsk value:%u" "\n", value);
#line 1166 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_AVR_TIMER16_INTERRUPT_COUNT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AVR_TIMER16_INTERRUPT_COUNT) || \
    false)

static inline void trace_avr_timer16_interrupt_count(uint8_t cnt)
{
    if (trace_event_get_state(TRACE_AVR_TIMER16_INTERRUPT_COUNT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 85 "../xemu/hw/timer/trace-events"
            qemu_log("avr_timer16_interrupt_count " "count: %u" "\n", cnt);
#line 1181 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_AVR_TIMER16_INTERRUPT_OVERFLOW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AVR_TIMER16_INTERRUPT_OVERFLOW) || \
    false)

static inline void trace_avr_timer16_interrupt_overflow(const char *reason)
{
    if (trace_event_get_state(TRACE_AVR_TIMER16_INTERRUPT_OVERFLOW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 86 "../xemu/hw/timer/trace-events"
            qemu_log("avr_timer16_interrupt_overflow " "overflow: %s" "\n", reason);
#line 1196 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_AVR_TIMER16_NEXT_ALARM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AVR_TIMER16_NEXT_ALARM) || \
    false)

static inline void trace_avr_timer16_next_alarm(uint64_t delay_ns)
{
    if (trace_event_get_state(TRACE_AVR_TIMER16_NEXT_ALARM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 87 "../xemu/hw/timer/trace-events"
            qemu_log("avr_timer16_next_alarm " "next alarm: %" PRIu64 " ns from now" "\n", delay_ns);
#line 1211 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_AVR_TIMER16_CLKSRC_UPDATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AVR_TIMER16_CLKSRC_UPDATE) || \
    false)

static inline void trace_avr_timer16_clksrc_update(uint64_t freq_hz, uint64_t period_ns, uint64_t delay_s)
{
    if (trace_event_get_state(TRACE_AVR_TIMER16_CLKSRC_UPDATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 88 "../xemu/hw/timer/trace-events"
            qemu_log("avr_timer16_clksrc_update " "timer frequency: %" PRIu64 " Hz, period: %" PRIu64 " ns (%" PRId64 " us)" "\n", freq_hz, period_ns, delay_s);
#line 1226 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SSE_COUNTER_CONTROL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SSE_COUNTER_CONTROL_READ) || \
    false)

static inline void trace_sse_counter_control_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_SSE_COUNTER_CONTROL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 91 "../xemu/hw/timer/trace-events"
            qemu_log("sse_counter_control_read " "SSE system counter control frame read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 1241 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SSE_COUNTER_CONTROL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SSE_COUNTER_CONTROL_WRITE) || \
    false)

static inline void trace_sse_counter_control_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_SSE_COUNTER_CONTROL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 92 "../xemu/hw/timer/trace-events"
            qemu_log("sse_counter_control_write " "SSE system counter control framen write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 1256 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SSE_COUNTER_STATUS_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SSE_COUNTER_STATUS_READ) || \
    false)

static inline void trace_sse_counter_status_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_SSE_COUNTER_STATUS_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 93 "../xemu/hw/timer/trace-events"
            qemu_log("sse_counter_status_read " "SSE system counter status frame read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 1271 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SSE_COUNTER_STATUS_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SSE_COUNTER_STATUS_WRITE) || \
    false)

static inline void trace_sse_counter_status_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_SSE_COUNTER_STATUS_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 94 "../xemu/hw/timer/trace-events"
            qemu_log("sse_counter_status_write " "SSE system counter status frame write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 1286 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SSE_COUNTER_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SSE_COUNTER_RESET) || \
    false)

static inline void trace_sse_counter_reset(void)
{
    if (trace_event_get_state(TRACE_SSE_COUNTER_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 95 "../xemu/hw/timer/trace-events"
            qemu_log("sse_counter_reset " "SSE system counter: reset" "\n");
#line 1301 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SSE_TIMER_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SSE_TIMER_READ) || \
    false)

static inline void trace_sse_timer_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_SSE_TIMER_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 98 "../xemu/hw/timer/trace-events"
            qemu_log("sse_timer_read " "SSE system timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 1316 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SSE_TIMER_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SSE_TIMER_WRITE) || \
    false)

static inline void trace_sse_timer_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_SSE_TIMER_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 99 "../xemu/hw/timer/trace-events"
            qemu_log("sse_timer_write " "SSE system timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 1331 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SSE_TIMER_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SSE_TIMER_RESET) || \
    false)

static inline void trace_sse_timer_reset(void)
{
    if (trace_event_get_state(TRACE_SSE_TIMER_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 100 "../xemu/hw/timer/trace-events"
            qemu_log("sse_timer_reset " "SSE system timer: reset" "\n");
#line 1346 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SIFIVE_PWM_SET_ALARM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SIFIVE_PWM_SET_ALARM) || \
    false)

static inline void trace_sifive_pwm_set_alarm(uint64_t alarm, uint64_t now)
{
    if (trace_event_get_state(TRACE_SIFIVE_PWM_SET_ALARM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 103 "../xemu/hw/timer/trace-events"
            qemu_log("sifive_pwm_set_alarm " "Setting alarm to: 0x%" PRIx64 ", now: 0x%" PRIx64 "\n", alarm, now);
#line 1361 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SIFIVE_PWM_INTERRUPT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SIFIVE_PWM_INTERRUPT) || \
    false)

static inline void trace_sifive_pwm_interrupt(int num)
{
    if (trace_event_get_state(TRACE_SIFIVE_PWM_INTERRUPT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 104 "../xemu/hw/timer/trace-events"
            qemu_log("sifive_pwm_interrupt " "Interrupt %d" "\n", num);
#line 1376 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SIFIVE_PWM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SIFIVE_PWM_READ) || \
    false)

static inline void trace_sifive_pwm_read(uint64_t offset)
{
    if (trace_event_get_state(TRACE_SIFIVE_PWM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 105 "../xemu/hw/timer/trace-events"
            qemu_log("sifive_pwm_read " "Read at address: 0x%" PRIx64 "\n", offset);
#line 1391 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SIFIVE_PWM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SIFIVE_PWM_WRITE) || \
    false)

static inline void trace_sifive_pwm_write(uint64_t data, uint64_t offset)
{
    if (trace_event_get_state(TRACE_SIFIVE_PWM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 106 "../xemu/hw/timer/trace-events"
            qemu_log("sifive_pwm_write " "Write 0x%" PRIx64 " at address: 0x%" PRIx64 "\n", data, offset);
#line 1406 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SH_TIMER_START_STOP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SH_TIMER_START_STOP) || \
    false)

static inline void trace_sh_timer_start_stop(int enable, int current)
{
    if (trace_event_get_state(TRACE_SH_TIMER_START_STOP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 109 "../xemu/hw/timer/trace-events"
            qemu_log("sh_timer_start_stop " "%d (%d)" "\n", enable, current);
#line 1421 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SH_TIMER_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SH_TIMER_READ) || \
    false)

static inline void trace_sh_timer_read(uint64_t offset)
{
    if (trace_event_get_state(TRACE_SH_TIMER_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 110 "../xemu/hw/timer/trace-events"
            qemu_log("sh_timer_read " "tmu012_read 0x%" PRIx64 "\n", offset);
#line 1436 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_SH_TIMER_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SH_TIMER_WRITE) || \
    false)

static inline void trace_sh_timer_write(uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_SH_TIMER_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 111 "../xemu/hw/timer/trace-events"
            qemu_log("sh_timer_write " "tmu012_write 0x%" PRIx64 " 0x%08" PRIx64 "\n", offset, value);
#line 1451 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_TIMER_ID_OUT_OF_RANGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_TIMER_ID_OUT_OF_RANGE) || \
    false)

static inline void trace_hpet_timer_id_out_of_range(uint8_t timer_id)
{
    if (trace_event_get_state(TRACE_HPET_TIMER_ID_OUT_OF_RANGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 114 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_timer_id_out_of_range " "timer id out of range: 0x%" PRIx8 "\n", timer_id);
#line 1466 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_INVALID_HPET_CFG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_INVALID_HPET_CFG) || \
    false)

static inline void trace_hpet_invalid_hpet_cfg(uint8_t reg_off)
{
    if (trace_event_get_state(TRACE_HPET_INVALID_HPET_CFG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 115 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_invalid_hpet_cfg " "invalid HPET_CFG + %u" PRIx8 "\n", reg_off);
#line 1481 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_RAM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_RAM_READ) || \
    false)

static inline void trace_hpet_ram_read(uint64_t addr)
{
    if (trace_event_get_state(TRACE_HPET_RAM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 116 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_ram_read " "enter hpet_ram_readl at 0x%" PRIx64 "\n", addr);
#line 1496 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_RAM_READ_READING_COUNTER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_RAM_READ_READING_COUNTER) || \
    false)

static inline void trace_hpet_ram_read_reading_counter(uint8_t reg_off, uint64_t cur_tick)
{
    if (trace_event_get_state(TRACE_HPET_RAM_READ_READING_COUNTER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 117 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_ram_read_reading_counter " "reading counter + %" PRIu8 " = 0x%" PRIx64 "\n", reg_off, cur_tick);
#line 1511 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_RAM_READ_INVALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_RAM_READ_INVALID) || \
    false)

static inline void trace_hpet_ram_read_invalid(void)
{
    if (trace_event_get_state(TRACE_HPET_RAM_READ_INVALID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 118 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_ram_read_invalid " "invalid hpet_ram_readl" "\n");
#line 1526 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_RAM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_RAM_WRITE) || \
    false)

static inline void trace_hpet_ram_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_HPET_RAM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 119 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_ram_write " "enter hpet_ram_writel at 0x%" PRIx64 " = 0x%" PRIx64 "\n", addr, value);
#line 1541 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_RAM_WRITE_TIMER_ID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_RAM_WRITE_TIMER_ID) || \
    false)

static inline void trace_hpet_ram_write_timer_id(uint64_t timer_id)
{
    if (trace_event_get_state(TRACE_HPET_RAM_WRITE_TIMER_ID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 120 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_ram_write_timer_id " "hpet_ram_writel timer_id = 0x%" PRIx64 "\n", timer_id);
#line 1556 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_RAM_WRITE_TN_CFG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_RAM_WRITE_TN_CFG) || \
    false)

static inline void trace_hpet_ram_write_tn_cfg(uint8_t reg_off)
{
    if (trace_event_get_state(TRACE_HPET_RAM_WRITE_TN_CFG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 121 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_ram_write_tn_cfg " "hpet_ram_writel HPET_TN_CFG + %" PRIu8 "\n", reg_off);
#line 1571 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_RAM_WRITE_TN_CMP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_RAM_WRITE_TN_CMP) || \
    false)

static inline void trace_hpet_ram_write_tn_cmp(uint8_t reg_off)
{
    if (trace_event_get_state(TRACE_HPET_RAM_WRITE_TN_CMP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 122 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_ram_write_tn_cmp " "hpet_ram_writel HPET_TN_CMP + %" PRIu8 "\n", reg_off);
#line 1586 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_RAM_WRITE_INVALID_TN_CMP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_RAM_WRITE_INVALID_TN_CMP) || \
    false)

static inline void trace_hpet_ram_write_invalid_tn_cmp(void)
{
    if (trace_event_get_state(TRACE_HPET_RAM_WRITE_INVALID_TN_CMP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 123 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_ram_write_invalid_tn_cmp " "invalid HPET_TN_CMP + 4 write" "\n");
#line 1601 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_RAM_WRITE_INVALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_RAM_WRITE_INVALID) || \
    false)

static inline void trace_hpet_ram_write_invalid(void)
{
    if (trace_event_get_state(TRACE_HPET_RAM_WRITE_INVALID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 124 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_ram_write_invalid " "invalid hpet_ram_writel" "\n");
#line 1616 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_RAM_WRITE_COUNTER_WRITE_WHILE_ENABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_RAM_WRITE_COUNTER_WRITE_WHILE_ENABLED) || \
    false)

static inline void trace_hpet_ram_write_counter_write_while_enabled(void)
{
    if (trace_event_get_state(TRACE_HPET_RAM_WRITE_COUNTER_WRITE_WHILE_ENABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 125 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_ram_write_counter_write_while_enabled " "Writing counter while HPET enabled!" "\n");
#line 1631 "trace/trace-hw_timer.h"
        }
    }
}

#define TRACE_HPET_RAM_WRITE_COUNTER_WRITTEN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_HPET_RAM_WRITE_COUNTER_WRITTEN) || \
    false)

static inline void trace_hpet_ram_write_counter_written(uint8_t reg_off, uint64_t value, uint64_t counter)
{
    if (trace_event_get_state(TRACE_HPET_RAM_WRITE_COUNTER_WRITTEN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 126 "../xemu/hw/timer/trace-events"
            qemu_log("hpet_ram_write_counter_written " "HPET counter + %" PRIu8 "written. crt = 0x%" PRIx64 " -> 0x%" PRIx64 "\n", reg_off, value, counter);
#line 1646 "trace/trace-hw_timer.h"
        }
    }
}
#endif /* TRACE_HW_TIMER_GENERATED_TRACERS_H */
