/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_HW_MISC_GENERATED_TRACERS_H
#define TRACE_HW_MISC_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_ALLWINNER_CPUCFG_CPU_RESET_EVENT;
extern TraceEvent _TRACE_ALLWINNER_CPUCFG_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_CPUCFG_WRITE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_H3_DRAMCOM_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_H3_DRAMCOM_WRITE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_H3_DRAMCTL_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_H3_DRAMCTL_WRITE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_H3_DRAMPHY_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_H3_DRAMPHY_WRITE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_EVENT;
extern TraceEvent _TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_EVENT;
extern TraceEvent _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_R40_DRAMCOM_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_R40_DRAMCOM_WRITE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_R40_DRAMCTL_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_R40_DRAMCTL_WRITE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_R40_DRAMPHY_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_R40_DRAMPHY_WRITE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_SID_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_SID_WRITE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_SRAMC_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_SRAMC_WRITE_EVENT;
extern TraceEvent _TRACE_AVR_POWER_READ_EVENT;
extern TraceEvent _TRACE_AVR_POWER_WRITE_EVENT;
extern TraceEvent _TRACE_AXP2XX_RX_EVENT;
extern TraceEvent _TRACE_AXP2XX_SELECT_EVENT;
extern TraceEvent _TRACE_AXP2XX_TX_EVENT;
extern TraceEvent _TRACE_ECC_MEM_WRITEL_MER_EVENT;
extern TraceEvent _TRACE_ECC_MEM_WRITEL_MDR_EVENT;
extern TraceEvent _TRACE_ECC_MEM_WRITEL_MFSR_EVENT;
extern TraceEvent _TRACE_ECC_MEM_WRITEL_VCR_EVENT;
extern TraceEvent _TRACE_ECC_MEM_WRITEL_DR_EVENT;
extern TraceEvent _TRACE_ECC_MEM_WRITEL_ECR0_EVENT;
extern TraceEvent _TRACE_ECC_MEM_WRITEL_ECR1_EVENT;
extern TraceEvent _TRACE_ECC_MEM_READL_MER_EVENT;
extern TraceEvent _TRACE_ECC_MEM_READL_MDR_EVENT;
extern TraceEvent _TRACE_ECC_MEM_READL_MFSR_EVENT;
extern TraceEvent _TRACE_ECC_MEM_READL_VCR_EVENT;
extern TraceEvent _TRACE_ECC_MEM_READL_MFAR0_EVENT;
extern TraceEvent _TRACE_ECC_MEM_READL_MFAR1_EVENT;
extern TraceEvent _TRACE_ECC_MEM_READL_DR_EVENT;
extern TraceEvent _TRACE_ECC_MEM_READL_ECR0_EVENT;
extern TraceEvent _TRACE_ECC_MEM_READL_ECR1_EVENT;
extern TraceEvent _TRACE_ECC_DIAG_MEM_WRITEB_EVENT;
extern TraceEvent _TRACE_ECC_DIAG_MEM_READB_EVENT;
extern TraceEvent _TRACE_EMPTY_SLOT_WRITE_EVENT;
extern TraceEvent _TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_EVENT;
extern TraceEvent _TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_EVENT;
extern TraceEvent _TRACE_SLAVIO_SET_POWER_FAIL_EVENT;
extern TraceEvent _TRACE_SLAVIO_CFG_MEM_WRITEB_EVENT;
extern TraceEvent _TRACE_SLAVIO_CFG_MEM_READB_EVENT;
extern TraceEvent _TRACE_SLAVIO_DIAG_MEM_WRITEB_EVENT;
extern TraceEvent _TRACE_SLAVIO_DIAG_MEM_READB_EVENT;
extern TraceEvent _TRACE_SLAVIO_MDM_MEM_WRITEB_EVENT;
extern TraceEvent _TRACE_SLAVIO_MDM_MEM_READB_EVENT;
extern TraceEvent _TRACE_SLAVIO_AUX1_MEM_WRITEB_EVENT;
extern TraceEvent _TRACE_SLAVIO_AUX1_MEM_READB_EVENT;
extern TraceEvent _TRACE_SLAVIO_AUX2_MEM_WRITEB_EVENT;
extern TraceEvent _TRACE_SLAVIO_AUX2_MEM_READB_EVENT;
extern TraceEvent _TRACE_APC_MEM_WRITEB_EVENT;
extern TraceEvent _TRACE_APC_MEM_READB_EVENT;
extern TraceEvent _TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_EVENT;
extern TraceEvent _TRACE_SLAVIO_SYSCTRL_MEM_READL_EVENT;
extern TraceEvent _TRACE_SLAVIO_LED_MEM_WRITEW_EVENT;
extern TraceEvent _TRACE_SLAVIO_LED_MEM_READW_EVENT;
extern TraceEvent _TRACE_ASPEED_SBC_IGNORE_CMD_EVENT;
extern TraceEvent _TRACE_ASPEED_SBC_HANDLE_CMD_EVENT;
extern TraceEvent _TRACE_ASPEED_SBC_OTP_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_SBC_OTP_PROG_EVENT;
extern TraceEvent _TRACE_ASPEED_SCU_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_SCU_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_AST2700_SCU_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_AST2700_SCU_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_AST2700_SCUIO_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_AST2700_SCUIO_READ_EVENT;
extern TraceEvent _TRACE_MPS2_SCC_READ_EVENT;
extern TraceEvent _TRACE_MPS2_SCC_WRITE_EVENT;
extern TraceEvent _TRACE_MPS2_SCC_RESET_EVENT;
extern TraceEvent _TRACE_MPS2_SCC_CFG_WRITE_EVENT;
extern TraceEvent _TRACE_MPS2_SCC_CFG_READ_EVENT;
extern TraceEvent _TRACE_MPS2_FPGAIO_READ_EVENT;
extern TraceEvent _TRACE_MPS2_FPGAIO_WRITE_EVENT;
extern TraceEvent _TRACE_MPS2_FPGAIO_RESET_EVENT;
extern TraceEvent _TRACE_MSF2_SYSREG_WRITE_EVENT;
extern TraceEvent _TRACE_MSF2_SYSREG_READ_EVENT;
extern TraceEvent _TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_EVENT;
extern TraceEvent _TRACE_IMX7_GPR_READ_EVENT;
extern TraceEvent _TRACE_IMX7_GPR_WRITE_EVENT;
extern TraceEvent _TRACE_IMX7_SNVS_READ_EVENT;
extern TraceEvent _TRACE_IMX7_SNVS_WRITE_EVENT;
extern TraceEvent _TRACE_MOS6522_SET_COUNTER_EVENT;
extern TraceEvent _TRACE_MOS6522_GET_NEXT_IRQ_TIME_EVENT;
extern TraceEvent _TRACE_MOS6522_SET_SR_INT_EVENT;
extern TraceEvent _TRACE_MOS6522_WRITE_EVENT;
extern TraceEvent _TRACE_MOS6522_READ_EVENT;
extern TraceEvent _TRACE_NPCM_CLK_READ_EVENT;
extern TraceEvent _TRACE_NPCM_CLK_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM_GCR_READ_EVENT;
extern TraceEvent _TRACE_NPCM_GCR_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_MFT_READ_EVENT;
extern TraceEvent _TRACE_NPCM7XX_MFT_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_MFT_RPM_EVENT;
extern TraceEvent _TRACE_NPCM7XX_MFT_CAPTURE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_MFT_UPDATE_CLOCK_EVENT;
extern TraceEvent _TRACE_NPCM7XX_MFT_SET_DUTY_EVENT;
extern TraceEvent _TRACE_NPCM7XX_RNG_READ_EVENT;
extern TraceEvent _TRACE_NPCM7XX_RNG_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_PWM_READ_EVENT;
extern TraceEvent _TRACE_NPCM7XX_PWM_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_PWM_UPDATE_FREQ_EVENT;
extern TraceEvent _TRACE_NPCM7XX_PWM_UPDATE_DUTY_EVENT;
extern TraceEvent _TRACE_STM32_RCC_READ_EVENT;
extern TraceEvent _TRACE_STM32_RCC_WRITE_EVENT;
extern TraceEvent _TRACE_STM32_RCC_PULSE_ENABLE_EVENT;
extern TraceEvent _TRACE_STM32_RCC_PULSE_RESET_EVENT;
extern TraceEvent _TRACE_STM32F4XX_SYSCFG_SET_IRQ_EVENT;
extern TraceEvent _TRACE_STM32F4XX_PULSE_EXTI_EVENT;
extern TraceEvent _TRACE_STM32F4XX_SYSCFG_READ_EVENT;
extern TraceEvent _TRACE_STM32F4XX_SYSCFG_WRITE_EVENT;
extern TraceEvent _TRACE_STM32F4XX_EXTI_SET_IRQ_EVENT;
extern TraceEvent _TRACE_STM32F4XX_EXTI_READ_EVENT;
extern TraceEvent _TRACE_STM32F4XX_EXTI_WRITE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_SYSCFG_SET_IRQ_EVENT;
extern TraceEvent _TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_EVENT;
extern TraceEvent _TRACE_STM32L4X5_SYSCFG_READ_EVENT;
extern TraceEvent _TRACE_STM32L4X5_SYSCFG_WRITE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_EXTI_SET_IRQ_EVENT;
extern TraceEvent _TRACE_STM32L4X5_EXTI_READ_EVENT;
extern TraceEvent _TRACE_STM32L4X5_EXTI_WRITE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_RCC_READ_EVENT;
extern TraceEvent _TRACE_STM32L4X5_RCC_WRITE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_RCC_MUX_ENABLE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_RCC_MUX_DISABLE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_EVENT;
extern TraceEvent _TRACE_STM32L4X5_RCC_MUX_SET_SRC_EVENT;
extern TraceEvent _TRACE_STM32L4X5_RCC_MUX_UPDATE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_EVENT;
extern TraceEvent _TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_EVENT;
extern TraceEvent _TRACE_STM32L4X5_RCC_PLL_UPDATE_EVENT;
extern TraceEvent _TRACE_TZ_MPC_REG_READ_EVENT;
extern TraceEvent _TRACE_TZ_MPC_REG_WRITE_EVENT;
extern TraceEvent _TRACE_TZ_MPC_MEM_BLOCKED_READ_EVENT;
extern TraceEvent _TRACE_TZ_MPC_MEM_BLOCKED_WRITE_EVENT;
extern TraceEvent _TRACE_TZ_MPC_TRANSLATE_EVENT;
extern TraceEvent _TRACE_TZ_MPC_IOMMU_NOTIFY_EVENT;
extern TraceEvent _TRACE_TZ_MSC_RESET_EVENT;
extern TraceEvent _TRACE_TZ_MSC_CFG_NONSEC_EVENT;
extern TraceEvent _TRACE_TZ_MSC_CFG_SEC_RESP_EVENT;
extern TraceEvent _TRACE_TZ_MSC_IRQ_CLEAR_EVENT;
extern TraceEvent _TRACE_TZ_MSC_UPDATE_IRQ_EVENT;
extern TraceEvent _TRACE_TZ_MSC_ACCESS_BLOCKED_EVENT;
extern TraceEvent _TRACE_TZ_PPC_RESET_EVENT;
extern TraceEvent _TRACE_TZ_PPC_CFG_NONSEC_EVENT;
extern TraceEvent _TRACE_TZ_PPC_CFG_AP_EVENT;
extern TraceEvent _TRACE_TZ_PPC_CFG_SEC_RESP_EVENT;
extern TraceEvent _TRACE_TZ_PPC_IRQ_ENABLE_EVENT;
extern TraceEvent _TRACE_TZ_PPC_IRQ_CLEAR_EVENT;
extern TraceEvent _TRACE_TZ_PPC_UPDATE_IRQ_EVENT;
extern TraceEvent _TRACE_TZ_PPC_READ_BLOCKED_EVENT;
extern TraceEvent _TRACE_TZ_PPC_WRITE_BLOCKED_EVENT;
extern TraceEvent _TRACE_IOTKIT_SECCTL_S_READ_EVENT;
extern TraceEvent _TRACE_IOTKIT_SECCTL_S_WRITE_EVENT;
extern TraceEvent _TRACE_IOTKIT_SECCTL_NS_READ_EVENT;
extern TraceEvent _TRACE_IOTKIT_SECCTL_NS_WRITE_EVENT;
extern TraceEvent _TRACE_IMX6_ANALOG_GET_PERIPH_CLK_EVENT;
extern TraceEvent _TRACE_IMX6_ANALOG_GET_PLL2_CLK_EVENT;
extern TraceEvent _TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_EVENT;
extern TraceEvent _TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_EVENT;
extern TraceEvent _TRACE_IMX6_ANALOG_READ_EVENT;
extern TraceEvent _TRACE_IMX6_ANALOG_WRITE_EVENT;
extern TraceEvent _TRACE_IMX6_CCM_GET_AHB_CLK_EVENT;
extern TraceEvent _TRACE_IMX6_CCM_GET_IPG_CLK_EVENT;
extern TraceEvent _TRACE_IMX6_CCM_GET_PER_CLK_EVENT;
extern TraceEvent _TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_EVENT;
extern TraceEvent _TRACE_IMX6_CCM_READ_EVENT;
extern TraceEvent _TRACE_IMX6_CCM_RESET_EVENT;
extern TraceEvent _TRACE_IMX6_CCM_WRITE_EVENT;
extern TraceEvent _TRACE_CCM_ENTRY_EVENT;
extern TraceEvent _TRACE_CCM_FREQ_EVENT;
extern TraceEvent _TRACE_CCM_CLOCK_FREQ_EVENT;
extern TraceEvent _TRACE_CCM_READ_REG_EVENT;
extern TraceEvent _TRACE_CCM_WRITE_REG_EVENT;
extern TraceEvent _TRACE_IMX6_SRC_READ_EVENT;
extern TraceEvent _TRACE_IMX6_SRC_WRITE_EVENT;
extern TraceEvent _TRACE_IMX6_CLEAR_RESET_BIT_EVENT;
extern TraceEvent _TRACE_IMX6_SRC_RESET_EVENT;
extern TraceEvent _TRACE_IMX7_SRC_READ_EVENT;
extern TraceEvent _TRACE_IMX7_SRC_WRITE_EVENT;
extern TraceEvent _TRACE_IOTKIT_SYSINFO_READ_EVENT;
extern TraceEvent _TRACE_IOTKIT_SYSINFO_WRITE_EVENT;
extern TraceEvent _TRACE_IOTKIT_SYSCTL_READ_EVENT;
extern TraceEvent _TRACE_IOTKIT_SYSCTL_WRITE_EVENT;
extern TraceEvent _TRACE_IOTKIT_SYSCTL_RESET_EVENT;
extern TraceEvent _TRACE_ARMSSE_CPU_PWRCTRL_READ_EVENT;
extern TraceEvent _TRACE_ARMSSE_CPU_PWRCTRL_WRITE_EVENT;
extern TraceEvent _TRACE_ARMSSE_CPUID_READ_EVENT;
extern TraceEvent _TRACE_ARMSSE_CPUID_WRITE_EVENT;
extern TraceEvent _TRACE_ARMSSE_MHU_READ_EVENT;
extern TraceEvent _TRACE_ARMSSE_MHU_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_XDMA_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_I3C_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_I3C_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_I3C_DEVICE_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_I3C_DEVICE_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_SDMC_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_SDMC_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_PECI_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_PECI_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_PECI_RAISE_INTERRUPT_EVENT;
extern TraceEvent _TRACE_ASPEED_HACE_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_HACE_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_HACE_HASH_SG_EVENT;
extern TraceEvent _TRACE_ASPEED_HACE_HASH_ADDR_EVENT;
extern TraceEvent _TRACE_ASPEED_HACE_HASH_EXECUTE_ACC_MODE_EVENT;
extern TraceEvent _TRACE_ASPEED_HACE_HEXDUMP_EVENT;
extern TraceEvent _TRACE_BCM2835_MBOX_PROPERTY_EVENT;
extern TraceEvent _TRACE_BCM2835_MBOX_WRITE_EVENT;
extern TraceEvent _TRACE_BCM2835_MBOX_READ_EVENT;
extern TraceEvent _TRACE_BCM2835_MBOX_IRQ_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_UPDATE_DATA_OUT_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_UPDATE_DATA_IN_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_INTERNAL_STATUS_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_INTERNAL_CMD_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_CMD_INVALID_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_INTERNAL_TIME_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_INTERNAL_SET_CMD_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_INTERNAL_SET_ALT_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_CMD_SECONDS_READ_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_CMD_SECONDS_WRITE_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_CMD_TEST_WRITE_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_CMD_PRAM_READ_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_CMD_PRAM_WRITE_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_EVENT;
extern TraceEvent _TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_EVENT;
extern TraceEvent _TRACE_VIA1_ADB_SEND_EVENT;
extern TraceEvent _TRACE_VIA1_ADB_RECEIVE_EVENT;
extern TraceEvent _TRACE_VIA1_ADB_POLL_EVENT;
extern TraceEvent _TRACE_VIA1_ADB_NETBSD_ENUM_HACK_EVENT;
extern TraceEvent _TRACE_VIA1_AUXMODE_EVENT;
extern TraceEvent _TRACE_VIA1_TIMER_HACK_STATE_EVENT;
extern TraceEvent _TRACE_GRLIB_AHB_PNP_READ_EVENT;
extern TraceEvent _TRACE_GRLIB_APB_PNP_READ_EVENT;
extern TraceEvent _TRACE_LED_SET_INTENSITY_EVENT;
extern TraceEvent _TRACE_LED_CHANGE_INTENSITY_EVENT;
extern TraceEvent _TRACE_BCM2835_CPRMAN_READ_EVENT;
extern TraceEvent _TRACE_BCM2835_CPRMAN_WRITE_EVENT;
extern TraceEvent _TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_EVENT;
extern TraceEvent _TRACE_VIRT_CTRL_READ_EVENT;
extern TraceEvent _TRACE_VIRT_CTRL_WRITE_EVENT;
extern TraceEvent _TRACE_VIRT_CTRL_RESET_EVENT;
extern TraceEvent _TRACE_VIRT_CTRL_REALIZE_EVENT;
extern TraceEvent _TRACE_VIRT_CTRL_INSTANCE_INIT_EVENT;
extern TraceEvent _TRACE_LASI_CHIP_MEM_VALID_EVENT;
extern TraceEvent _TRACE_LASI_CHIP_READ_EVENT;
extern TraceEvent _TRACE_LASI_CHIP_WRITE_EVENT;
extern TraceEvent _TRACE_DJMEMC_READ_EVENT;
extern TraceEvent _TRACE_DJMEMC_WRITE_EVENT;
extern TraceEvent _TRACE_IOSB_READ_EVENT;
extern TraceEvent _TRACE_IOSB_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_SLI_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_SLI_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_SLIIO_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_SLIIO_READ_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_IRQ_HANDLER_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_NEW_PEER_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_ADD_VECTOR_FAILURE_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_ADD_VECTOR_SUCCESS_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_IRQ_RESOLVED_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_PROTO_VER_OWN_ID_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_SHMEM_SIZE_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_SHMEM_MAP_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_MMIO_MAP_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_READ_MMR_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_READ_MMR_DOORBELL_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_READ_WRITE_MMR_INVALID_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_INTERRUPT_INVALID_PEER_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_WRITE_MMR_EVENT;
extern TraceEvent _TRACE_IVSHMEM_FLAT_INTERRUPT_PEER_EVENT;
extern TraceEvent _TRACE_I2C_ECHO_EVENT_EVENT;
extern TraceEvent _TRACE_I2C_ECHO_RECV_EVENT;
extern TraceEvent _TRACE_I2C_ECHO_SEND_EVENT;
extern uint16_t _TRACE_ALLWINNER_CPUCFG_CPU_RESET_DSTATE;
extern uint16_t _TRACE_ALLWINNER_CPUCFG_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_CPUCFG_WRITE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_H3_DRAMCOM_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_H3_DRAMCOM_WRITE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_H3_DRAMCTL_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_H3_DRAMCTL_WRITE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_H3_DRAMPHY_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_H3_DRAMPHY_WRITE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_DSTATE;
extern uint16_t _TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_DSTATE;
extern uint16_t _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_R40_DRAMCOM_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_R40_DRAMCOM_WRITE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_R40_DRAMCTL_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_R40_DRAMCTL_WRITE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_R40_DRAMPHY_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_R40_DRAMPHY_WRITE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_SID_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_SID_WRITE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_SRAMC_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_SRAMC_WRITE_DSTATE;
extern uint16_t _TRACE_AVR_POWER_READ_DSTATE;
extern uint16_t _TRACE_AVR_POWER_WRITE_DSTATE;
extern uint16_t _TRACE_AXP2XX_RX_DSTATE;
extern uint16_t _TRACE_AXP2XX_SELECT_DSTATE;
extern uint16_t _TRACE_AXP2XX_TX_DSTATE;
extern uint16_t _TRACE_ECC_MEM_WRITEL_MER_DSTATE;
extern uint16_t _TRACE_ECC_MEM_WRITEL_MDR_DSTATE;
extern uint16_t _TRACE_ECC_MEM_WRITEL_MFSR_DSTATE;
extern uint16_t _TRACE_ECC_MEM_WRITEL_VCR_DSTATE;
extern uint16_t _TRACE_ECC_MEM_WRITEL_DR_DSTATE;
extern uint16_t _TRACE_ECC_MEM_WRITEL_ECR0_DSTATE;
extern uint16_t _TRACE_ECC_MEM_WRITEL_ECR1_DSTATE;
extern uint16_t _TRACE_ECC_MEM_READL_MER_DSTATE;
extern uint16_t _TRACE_ECC_MEM_READL_MDR_DSTATE;
extern uint16_t _TRACE_ECC_MEM_READL_MFSR_DSTATE;
extern uint16_t _TRACE_ECC_MEM_READL_VCR_DSTATE;
extern uint16_t _TRACE_ECC_MEM_READL_MFAR0_DSTATE;
extern uint16_t _TRACE_ECC_MEM_READL_MFAR1_DSTATE;
extern uint16_t _TRACE_ECC_MEM_READL_DR_DSTATE;
extern uint16_t _TRACE_ECC_MEM_READL_ECR0_DSTATE;
extern uint16_t _TRACE_ECC_MEM_READL_ECR1_DSTATE;
extern uint16_t _TRACE_ECC_DIAG_MEM_WRITEB_DSTATE;
extern uint16_t _TRACE_ECC_DIAG_MEM_READB_DSTATE;
extern uint16_t _TRACE_EMPTY_SLOT_WRITE_DSTATE;
extern uint16_t _TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_DSTATE;
extern uint16_t _TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_DSTATE;
extern uint16_t _TRACE_SLAVIO_SET_POWER_FAIL_DSTATE;
extern uint16_t _TRACE_SLAVIO_CFG_MEM_WRITEB_DSTATE;
extern uint16_t _TRACE_SLAVIO_CFG_MEM_READB_DSTATE;
extern uint16_t _TRACE_SLAVIO_DIAG_MEM_WRITEB_DSTATE;
extern uint16_t _TRACE_SLAVIO_DIAG_MEM_READB_DSTATE;
extern uint16_t _TRACE_SLAVIO_MDM_MEM_WRITEB_DSTATE;
extern uint16_t _TRACE_SLAVIO_MDM_MEM_READB_DSTATE;
extern uint16_t _TRACE_SLAVIO_AUX1_MEM_WRITEB_DSTATE;
extern uint16_t _TRACE_SLAVIO_AUX1_MEM_READB_DSTATE;
extern uint16_t _TRACE_SLAVIO_AUX2_MEM_WRITEB_DSTATE;
extern uint16_t _TRACE_SLAVIO_AUX2_MEM_READB_DSTATE;
extern uint16_t _TRACE_APC_MEM_WRITEB_DSTATE;
extern uint16_t _TRACE_APC_MEM_READB_DSTATE;
extern uint16_t _TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_DSTATE;
extern uint16_t _TRACE_SLAVIO_SYSCTRL_MEM_READL_DSTATE;
extern uint16_t _TRACE_SLAVIO_LED_MEM_WRITEW_DSTATE;
extern uint16_t _TRACE_SLAVIO_LED_MEM_READW_DSTATE;
extern uint16_t _TRACE_ASPEED_SBC_IGNORE_CMD_DSTATE;
extern uint16_t _TRACE_ASPEED_SBC_HANDLE_CMD_DSTATE;
extern uint16_t _TRACE_ASPEED_SBC_OTP_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_SBC_OTP_PROG_DSTATE;
extern uint16_t _TRACE_ASPEED_SCU_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_SCU_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_AST2700_SCU_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_AST2700_SCU_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_AST2700_SCUIO_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_AST2700_SCUIO_READ_DSTATE;
extern uint16_t _TRACE_MPS2_SCC_READ_DSTATE;
extern uint16_t _TRACE_MPS2_SCC_WRITE_DSTATE;
extern uint16_t _TRACE_MPS2_SCC_RESET_DSTATE;
extern uint16_t _TRACE_MPS2_SCC_CFG_WRITE_DSTATE;
extern uint16_t _TRACE_MPS2_SCC_CFG_READ_DSTATE;
extern uint16_t _TRACE_MPS2_FPGAIO_READ_DSTATE;
extern uint16_t _TRACE_MPS2_FPGAIO_WRITE_DSTATE;
extern uint16_t _TRACE_MPS2_FPGAIO_RESET_DSTATE;
extern uint16_t _TRACE_MSF2_SYSREG_WRITE_DSTATE;
extern uint16_t _TRACE_MSF2_SYSREG_READ_DSTATE;
extern uint16_t _TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_DSTATE;
extern uint16_t _TRACE_IMX7_GPR_READ_DSTATE;
extern uint16_t _TRACE_IMX7_GPR_WRITE_DSTATE;
extern uint16_t _TRACE_IMX7_SNVS_READ_DSTATE;
extern uint16_t _TRACE_IMX7_SNVS_WRITE_DSTATE;
extern uint16_t _TRACE_MOS6522_SET_COUNTER_DSTATE;
extern uint16_t _TRACE_MOS6522_GET_NEXT_IRQ_TIME_DSTATE;
extern uint16_t _TRACE_MOS6522_SET_SR_INT_DSTATE;
extern uint16_t _TRACE_MOS6522_WRITE_DSTATE;
extern uint16_t _TRACE_MOS6522_READ_DSTATE;
extern uint16_t _TRACE_NPCM_CLK_READ_DSTATE;
extern uint16_t _TRACE_NPCM_CLK_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM_GCR_READ_DSTATE;
extern uint16_t _TRACE_NPCM_GCR_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_MFT_READ_DSTATE;
extern uint16_t _TRACE_NPCM7XX_MFT_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_MFT_RPM_DSTATE;
extern uint16_t _TRACE_NPCM7XX_MFT_CAPTURE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_MFT_UPDATE_CLOCK_DSTATE;
extern uint16_t _TRACE_NPCM7XX_MFT_SET_DUTY_DSTATE;
extern uint16_t _TRACE_NPCM7XX_RNG_READ_DSTATE;
extern uint16_t _TRACE_NPCM7XX_RNG_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_PWM_READ_DSTATE;
extern uint16_t _TRACE_NPCM7XX_PWM_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_PWM_UPDATE_FREQ_DSTATE;
extern uint16_t _TRACE_NPCM7XX_PWM_UPDATE_DUTY_DSTATE;
extern uint16_t _TRACE_STM32_RCC_READ_DSTATE;
extern uint16_t _TRACE_STM32_RCC_WRITE_DSTATE;
extern uint16_t _TRACE_STM32_RCC_PULSE_ENABLE_DSTATE;
extern uint16_t _TRACE_STM32_RCC_PULSE_RESET_DSTATE;
extern uint16_t _TRACE_STM32F4XX_SYSCFG_SET_IRQ_DSTATE;
extern uint16_t _TRACE_STM32F4XX_PULSE_EXTI_DSTATE;
extern uint16_t _TRACE_STM32F4XX_SYSCFG_READ_DSTATE;
extern uint16_t _TRACE_STM32F4XX_SYSCFG_WRITE_DSTATE;
extern uint16_t _TRACE_STM32F4XX_EXTI_SET_IRQ_DSTATE;
extern uint16_t _TRACE_STM32F4XX_EXTI_READ_DSTATE;
extern uint16_t _TRACE_STM32F4XX_EXTI_WRITE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_SYSCFG_SET_IRQ_DSTATE;
extern uint16_t _TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_DSTATE;
extern uint16_t _TRACE_STM32L4X5_SYSCFG_READ_DSTATE;
extern uint16_t _TRACE_STM32L4X5_SYSCFG_WRITE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_EXTI_SET_IRQ_DSTATE;
extern uint16_t _TRACE_STM32L4X5_EXTI_READ_DSTATE;
extern uint16_t _TRACE_STM32L4X5_EXTI_WRITE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_RCC_READ_DSTATE;
extern uint16_t _TRACE_STM32L4X5_RCC_WRITE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_RCC_MUX_ENABLE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_RCC_MUX_DISABLE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_DSTATE;
extern uint16_t _TRACE_STM32L4X5_RCC_MUX_SET_SRC_DSTATE;
extern uint16_t _TRACE_STM32L4X5_RCC_MUX_UPDATE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_DSTATE;
extern uint16_t _TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_DSTATE;
extern uint16_t _TRACE_STM32L4X5_RCC_PLL_UPDATE_DSTATE;
extern uint16_t _TRACE_TZ_MPC_REG_READ_DSTATE;
extern uint16_t _TRACE_TZ_MPC_REG_WRITE_DSTATE;
extern uint16_t _TRACE_TZ_MPC_MEM_BLOCKED_READ_DSTATE;
extern uint16_t _TRACE_TZ_MPC_MEM_BLOCKED_WRITE_DSTATE;
extern uint16_t _TRACE_TZ_MPC_TRANSLATE_DSTATE;
extern uint16_t _TRACE_TZ_MPC_IOMMU_NOTIFY_DSTATE;
extern uint16_t _TRACE_TZ_MSC_RESET_DSTATE;
extern uint16_t _TRACE_TZ_MSC_CFG_NONSEC_DSTATE;
extern uint16_t _TRACE_TZ_MSC_CFG_SEC_RESP_DSTATE;
extern uint16_t _TRACE_TZ_MSC_IRQ_CLEAR_DSTATE;
extern uint16_t _TRACE_TZ_MSC_UPDATE_IRQ_DSTATE;
extern uint16_t _TRACE_TZ_MSC_ACCESS_BLOCKED_DSTATE;
extern uint16_t _TRACE_TZ_PPC_RESET_DSTATE;
extern uint16_t _TRACE_TZ_PPC_CFG_NONSEC_DSTATE;
extern uint16_t _TRACE_TZ_PPC_CFG_AP_DSTATE;
extern uint16_t _TRACE_TZ_PPC_CFG_SEC_RESP_DSTATE;
extern uint16_t _TRACE_TZ_PPC_IRQ_ENABLE_DSTATE;
extern uint16_t _TRACE_TZ_PPC_IRQ_CLEAR_DSTATE;
extern uint16_t _TRACE_TZ_PPC_UPDATE_IRQ_DSTATE;
extern uint16_t _TRACE_TZ_PPC_READ_BLOCKED_DSTATE;
extern uint16_t _TRACE_TZ_PPC_WRITE_BLOCKED_DSTATE;
extern uint16_t _TRACE_IOTKIT_SECCTL_S_READ_DSTATE;
extern uint16_t _TRACE_IOTKIT_SECCTL_S_WRITE_DSTATE;
extern uint16_t _TRACE_IOTKIT_SECCTL_NS_READ_DSTATE;
extern uint16_t _TRACE_IOTKIT_SECCTL_NS_WRITE_DSTATE;
extern uint16_t _TRACE_IMX6_ANALOG_GET_PERIPH_CLK_DSTATE;
extern uint16_t _TRACE_IMX6_ANALOG_GET_PLL2_CLK_DSTATE;
extern uint16_t _TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_DSTATE;
extern uint16_t _TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_DSTATE;
extern uint16_t _TRACE_IMX6_ANALOG_READ_DSTATE;
extern uint16_t _TRACE_IMX6_ANALOG_WRITE_DSTATE;
extern uint16_t _TRACE_IMX6_CCM_GET_AHB_CLK_DSTATE;
extern uint16_t _TRACE_IMX6_CCM_GET_IPG_CLK_DSTATE;
extern uint16_t _TRACE_IMX6_CCM_GET_PER_CLK_DSTATE;
extern uint16_t _TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_DSTATE;
extern uint16_t _TRACE_IMX6_CCM_READ_DSTATE;
extern uint16_t _TRACE_IMX6_CCM_RESET_DSTATE;
extern uint16_t _TRACE_IMX6_CCM_WRITE_DSTATE;
extern uint16_t _TRACE_CCM_ENTRY_DSTATE;
extern uint16_t _TRACE_CCM_FREQ_DSTATE;
extern uint16_t _TRACE_CCM_CLOCK_FREQ_DSTATE;
extern uint16_t _TRACE_CCM_READ_REG_DSTATE;
extern uint16_t _TRACE_CCM_WRITE_REG_DSTATE;
extern uint16_t _TRACE_IMX6_SRC_READ_DSTATE;
extern uint16_t _TRACE_IMX6_SRC_WRITE_DSTATE;
extern uint16_t _TRACE_IMX6_CLEAR_RESET_BIT_DSTATE;
extern uint16_t _TRACE_IMX6_SRC_RESET_DSTATE;
extern uint16_t _TRACE_IMX7_SRC_READ_DSTATE;
extern uint16_t _TRACE_IMX7_SRC_WRITE_DSTATE;
extern uint16_t _TRACE_IOTKIT_SYSINFO_READ_DSTATE;
extern uint16_t _TRACE_IOTKIT_SYSINFO_WRITE_DSTATE;
extern uint16_t _TRACE_IOTKIT_SYSCTL_READ_DSTATE;
extern uint16_t _TRACE_IOTKIT_SYSCTL_WRITE_DSTATE;
extern uint16_t _TRACE_IOTKIT_SYSCTL_RESET_DSTATE;
extern uint16_t _TRACE_ARMSSE_CPU_PWRCTRL_READ_DSTATE;
extern uint16_t _TRACE_ARMSSE_CPU_PWRCTRL_WRITE_DSTATE;
extern uint16_t _TRACE_ARMSSE_CPUID_READ_DSTATE;
extern uint16_t _TRACE_ARMSSE_CPUID_WRITE_DSTATE;
extern uint16_t _TRACE_ARMSSE_MHU_READ_DSTATE;
extern uint16_t _TRACE_ARMSSE_MHU_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_XDMA_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_I3C_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_I3C_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_I3C_DEVICE_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_I3C_DEVICE_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_SDMC_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_SDMC_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_PECI_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_PECI_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_PECI_RAISE_INTERRUPT_DSTATE;
extern uint16_t _TRACE_ASPEED_HACE_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_HACE_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_HACE_HASH_SG_DSTATE;
extern uint16_t _TRACE_ASPEED_HACE_HASH_ADDR_DSTATE;
extern uint16_t _TRACE_ASPEED_HACE_HASH_EXECUTE_ACC_MODE_DSTATE;
extern uint16_t _TRACE_ASPEED_HACE_HEXDUMP_DSTATE;
extern uint16_t _TRACE_BCM2835_MBOX_PROPERTY_DSTATE;
extern uint16_t _TRACE_BCM2835_MBOX_WRITE_DSTATE;
extern uint16_t _TRACE_BCM2835_MBOX_READ_DSTATE;
extern uint16_t _TRACE_BCM2835_MBOX_IRQ_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_UPDATE_DATA_OUT_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_UPDATE_DATA_IN_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_INTERNAL_STATUS_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_INTERNAL_CMD_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_CMD_INVALID_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_INTERNAL_TIME_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_INTERNAL_SET_CMD_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_INTERNAL_SET_ALT_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_CMD_SECONDS_READ_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_CMD_SECONDS_WRITE_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_CMD_TEST_WRITE_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_CMD_PRAM_READ_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_CMD_PRAM_WRITE_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_DSTATE;
extern uint16_t _TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_DSTATE;
extern uint16_t _TRACE_VIA1_ADB_SEND_DSTATE;
extern uint16_t _TRACE_VIA1_ADB_RECEIVE_DSTATE;
extern uint16_t _TRACE_VIA1_ADB_POLL_DSTATE;
extern uint16_t _TRACE_VIA1_ADB_NETBSD_ENUM_HACK_DSTATE;
extern uint16_t _TRACE_VIA1_AUXMODE_DSTATE;
extern uint16_t _TRACE_VIA1_TIMER_HACK_STATE_DSTATE;
extern uint16_t _TRACE_GRLIB_AHB_PNP_READ_DSTATE;
extern uint16_t _TRACE_GRLIB_APB_PNP_READ_DSTATE;
extern uint16_t _TRACE_LED_SET_INTENSITY_DSTATE;
extern uint16_t _TRACE_LED_CHANGE_INTENSITY_DSTATE;
extern uint16_t _TRACE_BCM2835_CPRMAN_READ_DSTATE;
extern uint16_t _TRACE_BCM2835_CPRMAN_WRITE_DSTATE;
extern uint16_t _TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_DSTATE;
extern uint16_t _TRACE_VIRT_CTRL_READ_DSTATE;
extern uint16_t _TRACE_VIRT_CTRL_WRITE_DSTATE;
extern uint16_t _TRACE_VIRT_CTRL_RESET_DSTATE;
extern uint16_t _TRACE_VIRT_CTRL_REALIZE_DSTATE;
extern uint16_t _TRACE_VIRT_CTRL_INSTANCE_INIT_DSTATE;
extern uint16_t _TRACE_LASI_CHIP_MEM_VALID_DSTATE;
extern uint16_t _TRACE_LASI_CHIP_READ_DSTATE;
extern uint16_t _TRACE_LASI_CHIP_WRITE_DSTATE;
extern uint16_t _TRACE_DJMEMC_READ_DSTATE;
extern uint16_t _TRACE_DJMEMC_WRITE_DSTATE;
extern uint16_t _TRACE_IOSB_READ_DSTATE;
extern uint16_t _TRACE_IOSB_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_SLI_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_SLI_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_SLIIO_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_SLIIO_READ_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_IRQ_HANDLER_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_NEW_PEER_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_ADD_VECTOR_FAILURE_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_ADD_VECTOR_SUCCESS_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_IRQ_RESOLVED_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_PROTO_VER_OWN_ID_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_SHMEM_SIZE_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_SHMEM_MAP_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_MMIO_MAP_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_READ_MMR_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_READ_MMR_DOORBELL_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_READ_WRITE_MMR_INVALID_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_INTERRUPT_INVALID_PEER_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_WRITE_MMR_DSTATE;
extern uint16_t _TRACE_IVSHMEM_FLAT_INTERRUPT_PEER_DSTATE;
extern uint16_t _TRACE_I2C_ECHO_EVENT_DSTATE;
extern uint16_t _TRACE_I2C_ECHO_RECV_DSTATE;
extern uint16_t _TRACE_I2C_ECHO_SEND_DSTATE;
#define TRACE_ALLWINNER_CPUCFG_CPU_RESET_ENABLED 1
#define TRACE_ALLWINNER_CPUCFG_READ_ENABLED 1
#define TRACE_ALLWINNER_CPUCFG_WRITE_ENABLED 1
#define TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_ENABLED 1
#define TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_ENABLED 1
#define TRACE_ALLWINNER_H3_DRAMCOM_READ_ENABLED 1
#define TRACE_ALLWINNER_H3_DRAMCOM_WRITE_ENABLED 1
#define TRACE_ALLWINNER_H3_DRAMCTL_READ_ENABLED 1
#define TRACE_ALLWINNER_H3_DRAMCTL_WRITE_ENABLED 1
#define TRACE_ALLWINNER_H3_DRAMPHY_READ_ENABLED 1
#define TRACE_ALLWINNER_H3_DRAMPHY_WRITE_ENABLED 1
#define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_ENABLED 1
#define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_ENABLED 1
#define TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_ENABLED 1
#define TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_ENABLED 1
#define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_ENABLED 1
#define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_ENABLED 1
#define TRACE_ALLWINNER_R40_DRAMCOM_READ_ENABLED 1
#define TRACE_ALLWINNER_R40_DRAMCOM_WRITE_ENABLED 1
#define TRACE_ALLWINNER_R40_DRAMCTL_READ_ENABLED 1
#define TRACE_ALLWINNER_R40_DRAMCTL_WRITE_ENABLED 1
#define TRACE_ALLWINNER_R40_DRAMPHY_READ_ENABLED 1
#define TRACE_ALLWINNER_R40_DRAMPHY_WRITE_ENABLED 1
#define TRACE_ALLWINNER_SID_READ_ENABLED 1
#define TRACE_ALLWINNER_SID_WRITE_ENABLED 1
#define TRACE_ALLWINNER_SRAMC_READ_ENABLED 1
#define TRACE_ALLWINNER_SRAMC_WRITE_ENABLED 1
#define TRACE_AVR_POWER_READ_ENABLED 1
#define TRACE_AVR_POWER_WRITE_ENABLED 1
#define TRACE_AXP2XX_RX_ENABLED 1
#define TRACE_AXP2XX_SELECT_ENABLED 1
#define TRACE_AXP2XX_TX_ENABLED 1
#define TRACE_ECC_MEM_WRITEL_MER_ENABLED 1
#define TRACE_ECC_MEM_WRITEL_MDR_ENABLED 1
#define TRACE_ECC_MEM_WRITEL_MFSR_ENABLED 1
#define TRACE_ECC_MEM_WRITEL_VCR_ENABLED 1
#define TRACE_ECC_MEM_WRITEL_DR_ENABLED 1
#define TRACE_ECC_MEM_WRITEL_ECR0_ENABLED 1
#define TRACE_ECC_MEM_WRITEL_ECR1_ENABLED 1
#define TRACE_ECC_MEM_READL_MER_ENABLED 1
#define TRACE_ECC_MEM_READL_MDR_ENABLED 1
#define TRACE_ECC_MEM_READL_MFSR_ENABLED 1
#define TRACE_ECC_MEM_READL_VCR_ENABLED 1
#define TRACE_ECC_MEM_READL_MFAR0_ENABLED 1
#define TRACE_ECC_MEM_READL_MFAR1_ENABLED 1
#define TRACE_ECC_MEM_READL_DR_ENABLED 1
#define TRACE_ECC_MEM_READL_ECR0_ENABLED 1
#define TRACE_ECC_MEM_READL_ECR1_ENABLED 1
#define TRACE_ECC_DIAG_MEM_WRITEB_ENABLED 1
#define TRACE_ECC_DIAG_MEM_READB_ENABLED 1
#define TRACE_EMPTY_SLOT_WRITE_ENABLED 1
#define TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_ENABLED 1
#define TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_ENABLED 1
#define TRACE_SLAVIO_SET_POWER_FAIL_ENABLED 1
#define TRACE_SLAVIO_CFG_MEM_WRITEB_ENABLED 1
#define TRACE_SLAVIO_CFG_MEM_READB_ENABLED 1
#define TRACE_SLAVIO_DIAG_MEM_WRITEB_ENABLED 1
#define TRACE_SLAVIO_DIAG_MEM_READB_ENABLED 1
#define TRACE_SLAVIO_MDM_MEM_WRITEB_ENABLED 1
#define TRACE_SLAVIO_MDM_MEM_READB_ENABLED 1
#define TRACE_SLAVIO_AUX1_MEM_WRITEB_ENABLED 1
#define TRACE_SLAVIO_AUX1_MEM_READB_ENABLED 1
#define TRACE_SLAVIO_AUX2_MEM_WRITEB_ENABLED 1
#define TRACE_SLAVIO_AUX2_MEM_READB_ENABLED 1
#define TRACE_APC_MEM_WRITEB_ENABLED 1
#define TRACE_APC_MEM_READB_ENABLED 1
#define TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_ENABLED 1
#define TRACE_SLAVIO_SYSCTRL_MEM_READL_ENABLED 1
#define TRACE_SLAVIO_LED_MEM_WRITEW_ENABLED 1
#define TRACE_SLAVIO_LED_MEM_READW_ENABLED 1
#define TRACE_ASPEED_SBC_IGNORE_CMD_ENABLED 1
#define TRACE_ASPEED_SBC_HANDLE_CMD_ENABLED 1
#define TRACE_ASPEED_SBC_OTP_READ_ENABLED 1
#define TRACE_ASPEED_SBC_OTP_PROG_ENABLED 1
#define TRACE_ASPEED_SCU_WRITE_ENABLED 1
#define TRACE_ASPEED_SCU_READ_ENABLED 1
#define TRACE_ASPEED_AST2700_SCU_WRITE_ENABLED 1
#define TRACE_ASPEED_AST2700_SCU_READ_ENABLED 1
#define TRACE_ASPEED_AST2700_SCUIO_WRITE_ENABLED 1
#define TRACE_ASPEED_AST2700_SCUIO_READ_ENABLED 1
#define TRACE_MPS2_SCC_READ_ENABLED 1
#define TRACE_MPS2_SCC_WRITE_ENABLED 1
#define TRACE_MPS2_SCC_RESET_ENABLED 1
#define TRACE_MPS2_SCC_CFG_WRITE_ENABLED 1
#define TRACE_MPS2_SCC_CFG_READ_ENABLED 1
#define TRACE_MPS2_FPGAIO_READ_ENABLED 1
#define TRACE_MPS2_FPGAIO_WRITE_ENABLED 1
#define TRACE_MPS2_FPGAIO_RESET_ENABLED 1
#define TRACE_MSF2_SYSREG_WRITE_ENABLED 1
#define TRACE_MSF2_SYSREG_READ_ENABLED 1
#define TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_ENABLED 1
#define TRACE_IMX7_GPR_READ_ENABLED 1
#define TRACE_IMX7_GPR_WRITE_ENABLED 1
#define TRACE_IMX7_SNVS_READ_ENABLED 1
#define TRACE_IMX7_SNVS_WRITE_ENABLED 1
#define TRACE_MOS6522_SET_COUNTER_ENABLED 1
#define TRACE_MOS6522_GET_NEXT_IRQ_TIME_ENABLED 1
#define TRACE_MOS6522_SET_SR_INT_ENABLED 1
#define TRACE_MOS6522_WRITE_ENABLED 1
#define TRACE_MOS6522_READ_ENABLED 1
#define TRACE_NPCM_CLK_READ_ENABLED 1
#define TRACE_NPCM_CLK_WRITE_ENABLED 1
#define TRACE_NPCM_GCR_READ_ENABLED 1
#define TRACE_NPCM_GCR_WRITE_ENABLED 1
#define TRACE_NPCM7XX_MFT_READ_ENABLED 1
#define TRACE_NPCM7XX_MFT_WRITE_ENABLED 1
#define TRACE_NPCM7XX_MFT_RPM_ENABLED 1
#define TRACE_NPCM7XX_MFT_CAPTURE_ENABLED 1
#define TRACE_NPCM7XX_MFT_UPDATE_CLOCK_ENABLED 1
#define TRACE_NPCM7XX_MFT_SET_DUTY_ENABLED 1
#define TRACE_NPCM7XX_RNG_READ_ENABLED 1
#define TRACE_NPCM7XX_RNG_WRITE_ENABLED 1
#define TRACE_NPCM7XX_PWM_READ_ENABLED 1
#define TRACE_NPCM7XX_PWM_WRITE_ENABLED 1
#define TRACE_NPCM7XX_PWM_UPDATE_FREQ_ENABLED 1
#define TRACE_NPCM7XX_PWM_UPDATE_DUTY_ENABLED 1
#define TRACE_STM32_RCC_READ_ENABLED 1
#define TRACE_STM32_RCC_WRITE_ENABLED 1
#define TRACE_STM32_RCC_PULSE_ENABLE_ENABLED 1
#define TRACE_STM32_RCC_PULSE_RESET_ENABLED 1
#define TRACE_STM32F4XX_SYSCFG_SET_IRQ_ENABLED 1
#define TRACE_STM32F4XX_PULSE_EXTI_ENABLED 1
#define TRACE_STM32F4XX_SYSCFG_READ_ENABLED 1
#define TRACE_STM32F4XX_SYSCFG_WRITE_ENABLED 1
#define TRACE_STM32F4XX_EXTI_SET_IRQ_ENABLED 1
#define TRACE_STM32F4XX_EXTI_READ_ENABLED 1
#define TRACE_STM32F4XX_EXTI_WRITE_ENABLED 1
#define TRACE_STM32L4X5_SYSCFG_SET_IRQ_ENABLED 1
#define TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_ENABLED 1
#define TRACE_STM32L4X5_SYSCFG_READ_ENABLED 1
#define TRACE_STM32L4X5_SYSCFG_WRITE_ENABLED 1
#define TRACE_STM32L4X5_EXTI_SET_IRQ_ENABLED 1
#define TRACE_STM32L4X5_EXTI_READ_ENABLED 1
#define TRACE_STM32L4X5_EXTI_WRITE_ENABLED 1
#define TRACE_STM32L4X5_RCC_READ_ENABLED 1
#define TRACE_STM32L4X5_RCC_WRITE_ENABLED 1
#define TRACE_STM32L4X5_RCC_MUX_ENABLE_ENABLED 1
#define TRACE_STM32L4X5_RCC_MUX_DISABLE_ENABLED 1
#define TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_ENABLED 1
#define TRACE_STM32L4X5_RCC_MUX_SET_SRC_ENABLED 1
#define TRACE_STM32L4X5_RCC_MUX_UPDATE_ENABLED 1
#define TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_ENABLED 1
#define TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_ENABLED 1
#define TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_ENABLED 1
#define TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_ENABLED 1
#define TRACE_STM32L4X5_RCC_PLL_UPDATE_ENABLED 1
#define TRACE_TZ_MPC_REG_READ_ENABLED 1
#define TRACE_TZ_MPC_REG_WRITE_ENABLED 1
#define TRACE_TZ_MPC_MEM_BLOCKED_READ_ENABLED 1
#define TRACE_TZ_MPC_MEM_BLOCKED_WRITE_ENABLED 1
#define TRACE_TZ_MPC_TRANSLATE_ENABLED 1
#define TRACE_TZ_MPC_IOMMU_NOTIFY_ENABLED 1
#define TRACE_TZ_MSC_RESET_ENABLED 1
#define TRACE_TZ_MSC_CFG_NONSEC_ENABLED 1
#define TRACE_TZ_MSC_CFG_SEC_RESP_ENABLED 1
#define TRACE_TZ_MSC_IRQ_CLEAR_ENABLED 1
#define TRACE_TZ_MSC_UPDATE_IRQ_ENABLED 1
#define TRACE_TZ_MSC_ACCESS_BLOCKED_ENABLED 1
#define TRACE_TZ_PPC_RESET_ENABLED 1
#define TRACE_TZ_PPC_CFG_NONSEC_ENABLED 1
#define TRACE_TZ_PPC_CFG_AP_ENABLED 1
#define TRACE_TZ_PPC_CFG_SEC_RESP_ENABLED 1
#define TRACE_TZ_PPC_IRQ_ENABLE_ENABLED 1
#define TRACE_TZ_PPC_IRQ_CLEAR_ENABLED 1
#define TRACE_TZ_PPC_UPDATE_IRQ_ENABLED 1
#define TRACE_TZ_PPC_READ_BLOCKED_ENABLED 1
#define TRACE_TZ_PPC_WRITE_BLOCKED_ENABLED 1
#define TRACE_IOTKIT_SECCTL_S_READ_ENABLED 1
#define TRACE_IOTKIT_SECCTL_S_WRITE_ENABLED 1
#define TRACE_IOTKIT_SECCTL_NS_READ_ENABLED 1
#define TRACE_IOTKIT_SECCTL_NS_WRITE_ENABLED 1
#define TRACE_IMX6_ANALOG_GET_PERIPH_CLK_ENABLED 1
#define TRACE_IMX6_ANALOG_GET_PLL2_CLK_ENABLED 1
#define TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_ENABLED 1
#define TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_ENABLED 1
#define TRACE_IMX6_ANALOG_READ_ENABLED 1
#define TRACE_IMX6_ANALOG_WRITE_ENABLED 1
#define TRACE_IMX6_CCM_GET_AHB_CLK_ENABLED 1
#define TRACE_IMX6_CCM_GET_IPG_CLK_ENABLED 1
#define TRACE_IMX6_CCM_GET_PER_CLK_ENABLED 1
#define TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_ENABLED 1
#define TRACE_IMX6_CCM_READ_ENABLED 1
#define TRACE_IMX6_CCM_RESET_ENABLED 1
#define TRACE_IMX6_CCM_WRITE_ENABLED 1
#define TRACE_CCM_ENTRY_ENABLED 1
#define TRACE_CCM_FREQ_ENABLED 1
#define TRACE_CCM_CLOCK_FREQ_ENABLED 1
#define TRACE_CCM_READ_REG_ENABLED 1
#define TRACE_CCM_WRITE_REG_ENABLED 1
#define TRACE_IMX6_SRC_READ_ENABLED 1
#define TRACE_IMX6_SRC_WRITE_ENABLED 1
#define TRACE_IMX6_CLEAR_RESET_BIT_ENABLED 1
#define TRACE_IMX6_SRC_RESET_ENABLED 1
#define TRACE_IMX7_SRC_READ_ENABLED 1
#define TRACE_IMX7_SRC_WRITE_ENABLED 1
#define TRACE_IOTKIT_SYSINFO_READ_ENABLED 1
#define TRACE_IOTKIT_SYSINFO_WRITE_ENABLED 1
#define TRACE_IOTKIT_SYSCTL_READ_ENABLED 1
#define TRACE_IOTKIT_SYSCTL_WRITE_ENABLED 1
#define TRACE_IOTKIT_SYSCTL_RESET_ENABLED 1
#define TRACE_ARMSSE_CPU_PWRCTRL_READ_ENABLED 1
#define TRACE_ARMSSE_CPU_PWRCTRL_WRITE_ENABLED 1
#define TRACE_ARMSSE_CPUID_READ_ENABLED 1
#define TRACE_ARMSSE_CPUID_WRITE_ENABLED 1
#define TRACE_ARMSSE_MHU_READ_ENABLED 1
#define TRACE_ARMSSE_MHU_WRITE_ENABLED 1
#define TRACE_ASPEED_XDMA_WRITE_ENABLED 1
#define TRACE_ASPEED_I3C_READ_ENABLED 1
#define TRACE_ASPEED_I3C_WRITE_ENABLED 1
#define TRACE_ASPEED_I3C_DEVICE_READ_ENABLED 1
#define TRACE_ASPEED_I3C_DEVICE_WRITE_ENABLED 1
#define TRACE_ASPEED_SDMC_WRITE_ENABLED 1
#define TRACE_ASPEED_SDMC_READ_ENABLED 1
#define TRACE_ASPEED_PECI_READ_ENABLED 1
#define TRACE_ASPEED_PECI_WRITE_ENABLED 1
#define TRACE_ASPEED_PECI_RAISE_INTERRUPT_ENABLED 1
#define TRACE_ASPEED_HACE_READ_ENABLED 1
#define TRACE_ASPEED_HACE_WRITE_ENABLED 1
#define TRACE_ASPEED_HACE_HASH_SG_ENABLED 1
#define TRACE_ASPEED_HACE_HASH_ADDR_ENABLED 1
#define TRACE_ASPEED_HACE_HASH_EXECUTE_ACC_MODE_ENABLED 1
#define TRACE_ASPEED_HACE_HEXDUMP_ENABLED 1
#define TRACE_BCM2835_MBOX_PROPERTY_ENABLED 1
#define TRACE_BCM2835_MBOX_WRITE_ENABLED 1
#define TRACE_BCM2835_MBOX_READ_ENABLED 1
#define TRACE_BCM2835_MBOX_IRQ_ENABLED 1
#define TRACE_VIA1_RTC_UPDATE_DATA_OUT_ENABLED 1
#define TRACE_VIA1_RTC_UPDATE_DATA_IN_ENABLED 1
#define TRACE_VIA1_RTC_INTERNAL_STATUS_ENABLED 1
#define TRACE_VIA1_RTC_INTERNAL_CMD_ENABLED 1
#define TRACE_VIA1_RTC_CMD_INVALID_ENABLED 1
#define TRACE_VIA1_RTC_INTERNAL_TIME_ENABLED 1
#define TRACE_VIA1_RTC_INTERNAL_SET_CMD_ENABLED 1
#define TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_ENABLED 1
#define TRACE_VIA1_RTC_INTERNAL_SET_ALT_ENABLED 1
#define TRACE_VIA1_RTC_CMD_SECONDS_READ_ENABLED 1
#define TRACE_VIA1_RTC_CMD_SECONDS_WRITE_ENABLED 1
#define TRACE_VIA1_RTC_CMD_TEST_WRITE_ENABLED 1
#define TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_ENABLED 1
#define TRACE_VIA1_RTC_CMD_PRAM_READ_ENABLED 1
#define TRACE_VIA1_RTC_CMD_PRAM_WRITE_ENABLED 1
#define TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_ENABLED 1
#define TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_ENABLED 1
#define TRACE_VIA1_ADB_SEND_ENABLED 1
#define TRACE_VIA1_ADB_RECEIVE_ENABLED 1
#define TRACE_VIA1_ADB_POLL_ENABLED 1
#define TRACE_VIA1_ADB_NETBSD_ENUM_HACK_ENABLED 1
#define TRACE_VIA1_AUXMODE_ENABLED 1
#define TRACE_VIA1_TIMER_HACK_STATE_ENABLED 1
#define TRACE_GRLIB_AHB_PNP_READ_ENABLED 1
#define TRACE_GRLIB_APB_PNP_READ_ENABLED 1
#define TRACE_LED_SET_INTENSITY_ENABLED 1
#define TRACE_LED_CHANGE_INTENSITY_ENABLED 1
#define TRACE_BCM2835_CPRMAN_READ_ENABLED 1
#define TRACE_BCM2835_CPRMAN_WRITE_ENABLED 1
#define TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_ENABLED 1
#define TRACE_VIRT_CTRL_READ_ENABLED 1
#define TRACE_VIRT_CTRL_WRITE_ENABLED 1
#define TRACE_VIRT_CTRL_RESET_ENABLED 1
#define TRACE_VIRT_CTRL_REALIZE_ENABLED 1
#define TRACE_VIRT_CTRL_INSTANCE_INIT_ENABLED 1
#define TRACE_LASI_CHIP_MEM_VALID_ENABLED 1
#define TRACE_LASI_CHIP_READ_ENABLED 1
#define TRACE_LASI_CHIP_WRITE_ENABLED 1
#define TRACE_DJMEMC_READ_ENABLED 1
#define TRACE_DJMEMC_WRITE_ENABLED 1
#define TRACE_IOSB_READ_ENABLED 1
#define TRACE_IOSB_WRITE_ENABLED 1
#define TRACE_ASPEED_SLI_WRITE_ENABLED 1
#define TRACE_ASPEED_SLI_READ_ENABLED 1
#define TRACE_ASPEED_SLIIO_WRITE_ENABLED 1
#define TRACE_ASPEED_SLIIO_READ_ENABLED 1
#define TRACE_IVSHMEM_FLAT_IRQ_HANDLER_ENABLED 1
#define TRACE_IVSHMEM_FLAT_NEW_PEER_ENABLED 1
#define TRACE_IVSHMEM_FLAT_ADD_VECTOR_FAILURE_ENABLED 1
#define TRACE_IVSHMEM_FLAT_ADD_VECTOR_SUCCESS_ENABLED 1
#define TRACE_IVSHMEM_FLAT_IRQ_RESOLVED_ENABLED 1
#define TRACE_IVSHMEM_FLAT_PROTO_VER_OWN_ID_ENABLED 1
#define TRACE_IVSHMEM_FLAT_SHMEM_SIZE_ENABLED 1
#define TRACE_IVSHMEM_FLAT_SHMEM_MAP_ENABLED 1
#define TRACE_IVSHMEM_FLAT_MMIO_MAP_ENABLED 1
#define TRACE_IVSHMEM_FLAT_READ_MMR_ENABLED 1
#define TRACE_IVSHMEM_FLAT_READ_MMR_DOORBELL_ENABLED 1
#define TRACE_IVSHMEM_FLAT_READ_WRITE_MMR_INVALID_ENABLED 1
#define TRACE_IVSHMEM_FLAT_INTERRUPT_INVALID_PEER_ENABLED 1
#define TRACE_IVSHMEM_FLAT_WRITE_MMR_ENABLED 1
#define TRACE_IVSHMEM_FLAT_INTERRUPT_PEER_ENABLED 1
#define TRACE_I2C_ECHO_EVENT_ENABLED 1
#define TRACE_I2C_ECHO_RECV_ENABLED 1
#define TRACE_I2C_ECHO_SEND_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_ALLWINNER_CPUCFG_CPU_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_CPUCFG_CPU_RESET) || \
    false)

static inline void trace_allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr)
{
    if (trace_event_get_state(TRACE_ALLWINNER_CPUCFG_CPU_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 4 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_cpucfg_cpu_reset " "id %u, reset_addr 0x%" PRIx32 "\n", cpu_id, reset_addr);
#line 893 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_CPUCFG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_CPUCFG_READ) || \
    false)

static inline void trace_allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_CPUCFG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_cpucfg_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 908 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_CPUCFG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_CPUCFG_WRITE) || \
    false)

static inline void trace_allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_CPUCFG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 6 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_cpucfg_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 923 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE) || \
    false)

static inline void trace_allwinner_h3_dramc_rowmirror_disable(void)
{
    if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 9 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_h3_dramc_rowmirror_disable " "Disable row mirror" "\n");
#line 938 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE) || \
    false)

static inline void trace_allwinner_h3_dramc_rowmirror_enable(uint64_t addr)
{
    if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 10 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_h3_dramc_rowmirror_enable " "Enable row mirror: addr 0x%" PRIx64 "\n", addr);
#line 953 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_H3_DRAMCOM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMCOM_READ) || \
    false)

static inline void trace_allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMCOM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 11 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_h3_dramcom_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 968 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_H3_DRAMCOM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMCOM_WRITE) || \
    false)

static inline void trace_allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMCOM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 12 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_h3_dramcom_write " "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 983 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_H3_DRAMCTL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMCTL_READ) || \
    false)

static inline void trace_allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMCTL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 13 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_h3_dramctl_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 998 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_H3_DRAMCTL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMCTL_WRITE) || \
    false)

static inline void trace_allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMCTL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 14 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_h3_dramctl_write " "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 1013 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_H3_DRAMPHY_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMPHY_READ) || \
    false)

static inline void trace_allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMPHY_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_h3_dramphy_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 1028 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_H3_DRAMPHY_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMPHY_WRITE) || \
    false)

static inline void trace_allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMPHY_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 16 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_h3_dramphy_write " "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 1043 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE) || \
    false)

static inline void trace_allwinner_r40_dramc_detect_cells_disable(void)
{
    if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 19 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_r40_dramc_detect_cells_disable " "Disable detect cells" "\n");
#line 1058 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE) || \
    false)

static inline void trace_allwinner_r40_dramc_detect_cells_enable(void)
{
    if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 20 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_r40_dramc_detect_cells_enable " "Enable detect cells" "\n");
#line 1073 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS) || \
    false)

static inline void trace_allwinner_r40_dramc_map_rows(uint8_t row_bits, uint8_t bank_bits, uint8_t col_bits)
{
    if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 21 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_r40_dramc_map_rows " "DRAM layout: row_bits %d, bank_bits %d, col_bits %d" "\n", row_bits, bank_bits, col_bits);
#line 1088 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL) || \
    false)

static inline void trace_allwinner_r40_dramc_offset_to_cell(uint64_t offset, int row, int bank, int col)
{
    if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 22 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_r40_dramc_offset_to_cell " "offset 0x%" PRIx64 " row %d bank %d col %d" "\n", offset, row, bank, col);
#line 1103 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE) || \
    false)

static inline void trace_allwinner_r40_dramc_detect_cell_write(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 23 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_r40_dramc_detect_cell_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 "" "\n", offset, data);
#line 1118 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ) || \
    false)

static inline void trace_allwinner_r40_dramc_detect_cell_read(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 24 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_r40_dramc_detect_cell_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 "" "\n", offset, data);
#line 1133 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_R40_DRAMCOM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMCOM_READ) || \
    false)

static inline void trace_allwinner_r40_dramcom_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMCOM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 25 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_r40_dramcom_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 1148 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_R40_DRAMCOM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMCOM_WRITE) || \
    false)

static inline void trace_allwinner_r40_dramcom_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMCOM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 26 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_r40_dramcom_write " "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 1163 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_R40_DRAMCTL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMCTL_READ) || \
    false)

static inline void trace_allwinner_r40_dramctl_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMCTL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 27 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_r40_dramctl_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 1178 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_R40_DRAMCTL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMCTL_WRITE) || \
    false)

static inline void trace_allwinner_r40_dramctl_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMCTL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 28 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_r40_dramctl_write " "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 1193 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_R40_DRAMPHY_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMPHY_READ) || \
    false)

static inline void trace_allwinner_r40_dramphy_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMPHY_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 29 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_r40_dramphy_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 1208 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_R40_DRAMPHY_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMPHY_WRITE) || \
    false)

static inline void trace_allwinner_r40_dramphy_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMPHY_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 30 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_r40_dramphy_write " "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 1223 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_SID_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SID_READ) || \
    false)

static inline void trace_allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_SID_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 33 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_sid_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 1238 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_SID_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SID_WRITE) || \
    false)

static inline void trace_allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ALLWINNER_SID_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 34 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_sid_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size);
#line 1253 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_SRAMC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SRAMC_READ) || \
    false)

static inline void trace_allwinner_sramc_read(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ALLWINNER_SRAMC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 37 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_sramc_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data);
#line 1268 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ALLWINNER_SRAMC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SRAMC_WRITE) || \
    false)

static inline void trace_allwinner_sramc_write(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ALLWINNER_SRAMC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 38 "../xemu/hw/misc/trace-events"
            qemu_log("allwinner_sramc_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data);
#line 1283 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_AVR_POWER_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AVR_POWER_READ) || \
    false)

static inline void trace_avr_power_read(uint8_t value)
{
    if (trace_event_get_state(TRACE_AVR_POWER_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 41 "../xemu/hw/misc/trace-events"
            qemu_log("avr_power_read " "power_reduc read value:%u" "\n", value);
#line 1298 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_AVR_POWER_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AVR_POWER_WRITE) || \
    false)

static inline void trace_avr_power_write(uint8_t value)
{
    if (trace_event_get_state(TRACE_AVR_POWER_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 42 "../xemu/hw/misc/trace-events"
            qemu_log("avr_power_write " "power_reduc write value:%u" "\n", value);
#line 1313 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_AXP2XX_RX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AXP2XX_RX) || \
    false)

static inline void trace_axp2xx_rx(uint8_t reg, uint8_t data)
{
    if (trace_event_get_state(TRACE_AXP2XX_RX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 45 "../xemu/hw/misc/trace-events"
            qemu_log("axp2xx_rx " "Read reg 0x%" PRIx8 " : 0x%" PRIx8 "\n", reg, data);
#line 1328 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_AXP2XX_SELECT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AXP2XX_SELECT) || \
    false)

static inline void trace_axp2xx_select(uint8_t reg)
{
    if (trace_event_get_state(TRACE_AXP2XX_SELECT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 46 "../xemu/hw/misc/trace-events"
            qemu_log("axp2xx_select " "Accessing reg 0x%" PRIx8 "\n", reg);
#line 1343 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_AXP2XX_TX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_AXP2XX_TX) || \
    false)

static inline void trace_axp2xx_tx(uint8_t reg, uint8_t data)
{
    if (trace_event_get_state(TRACE_AXP2XX_TX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 47 "../xemu/hw/misc/trace-events"
            qemu_log("axp2xx_tx " "Write reg 0x%" PRIx8 " : 0x%" PRIx8 "\n", reg, data);
#line 1358 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_WRITEL_MER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_MER) || \
    false)

static inline void trace_ecc_mem_writel_mer(uint32_t val)
{
    if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_MER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 50 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_writel_mer " "Write memory enable 0x%08x" "\n", val);
#line 1373 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_WRITEL_MDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_MDR) || \
    false)

static inline void trace_ecc_mem_writel_mdr(uint32_t val)
{
    if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_MDR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 51 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_writel_mdr " "Write memory delay 0x%08x" "\n", val);
#line 1388 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_WRITEL_MFSR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_MFSR) || \
    false)

static inline void trace_ecc_mem_writel_mfsr(uint32_t val)
{
    if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_MFSR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 52 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_writel_mfsr " "Write memory fault status 0x%08x" "\n", val);
#line 1403 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_WRITEL_VCR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_VCR) || \
    false)

static inline void trace_ecc_mem_writel_vcr(uint32_t val)
{
    if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_VCR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 53 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_writel_vcr " "Write slot configuration 0x%08x" "\n", val);
#line 1418 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_WRITEL_DR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_DR) || \
    false)

static inline void trace_ecc_mem_writel_dr(uint32_t val)
{
    if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_DR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 54 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_writel_dr " "Write diagnostic 0x%08x" "\n", val);
#line 1433 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_WRITEL_ECR0_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_ECR0) || \
    false)

static inline void trace_ecc_mem_writel_ecr0(uint32_t val)
{
    if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_ECR0)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 55 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_writel_ecr0 " "Write event count 1 0x%08x" "\n", val);
#line 1448 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_WRITEL_ECR1_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_ECR1) || \
    false)

static inline void trace_ecc_mem_writel_ecr1(uint32_t val)
{
    if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_ECR1)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 56 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_writel_ecr1 " "Write event count 2 0x%08x" "\n", val);
#line 1463 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_READL_MER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_MER) || \
    false)

static inline void trace_ecc_mem_readl_mer(uint32_t ret)
{
    if (trace_event_get_state(TRACE_ECC_MEM_READL_MER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 57 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_readl_mer " "Read memory enable 0x%08x" "\n", ret);
#line 1478 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_READL_MDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_MDR) || \
    false)

static inline void trace_ecc_mem_readl_mdr(uint32_t ret)
{
    if (trace_event_get_state(TRACE_ECC_MEM_READL_MDR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 58 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_readl_mdr " "Read memory delay 0x%08x" "\n", ret);
#line 1493 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_READL_MFSR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_MFSR) || \
    false)

static inline void trace_ecc_mem_readl_mfsr(uint32_t ret)
{
    if (trace_event_get_state(TRACE_ECC_MEM_READL_MFSR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 59 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_readl_mfsr " "Read memory fault status 0x%08x" "\n", ret);
#line 1508 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_READL_VCR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_VCR) || \
    false)

static inline void trace_ecc_mem_readl_vcr(uint32_t ret)
{
    if (trace_event_get_state(TRACE_ECC_MEM_READL_VCR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 60 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_readl_vcr " "Read slot configuration 0x%08x" "\n", ret);
#line 1523 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_READL_MFAR0_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_MFAR0) || \
    false)

static inline void trace_ecc_mem_readl_mfar0(uint32_t ret)
{
    if (trace_event_get_state(TRACE_ECC_MEM_READL_MFAR0)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 61 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_readl_mfar0 " "Read memory fault address 0 0x%08x" "\n", ret);
#line 1538 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_READL_MFAR1_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_MFAR1) || \
    false)

static inline void trace_ecc_mem_readl_mfar1(uint32_t ret)
{
    if (trace_event_get_state(TRACE_ECC_MEM_READL_MFAR1)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 62 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_readl_mfar1 " "Read memory fault address 1 0x%08x" "\n", ret);
#line 1553 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_READL_DR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_DR) || \
    false)

static inline void trace_ecc_mem_readl_dr(uint32_t ret)
{
    if (trace_event_get_state(TRACE_ECC_MEM_READL_DR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 63 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_readl_dr " "Read diagnostic 0x%08x" "\n", ret);
#line 1568 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_READL_ECR0_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_ECR0) || \
    false)

static inline void trace_ecc_mem_readl_ecr0(uint32_t ret)
{
    if (trace_event_get_state(TRACE_ECC_MEM_READL_ECR0)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 64 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_readl_ecr0 " "Read event count 1 0x%08x" "\n", ret);
#line 1583 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_MEM_READL_ECR1_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_ECR1) || \
    false)

static inline void trace_ecc_mem_readl_ecr1(uint32_t ret)
{
    if (trace_event_get_state(TRACE_ECC_MEM_READL_ECR1)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 65 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_mem_readl_ecr1 " "Read event count 2 0x%08x" "\n", ret);
#line 1598 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_DIAG_MEM_WRITEB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_DIAG_MEM_WRITEB) || \
    false)

static inline void trace_ecc_diag_mem_writeb(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_ECC_DIAG_MEM_WRITEB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 66 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_diag_mem_writeb " "Write diagnostic %"PRId64" = 0x%02x" "\n", addr, val);
#line 1613 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ECC_DIAG_MEM_READB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ECC_DIAG_MEM_READB) || \
    false)

static inline void trace_ecc_diag_mem_readb(uint64_t addr, uint32_t ret)
{
    if (trace_event_get_state(TRACE_ECC_DIAG_MEM_READB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 67 "../xemu/hw/misc/trace-events"
            qemu_log("ecc_diag_mem_readb " "Read diagnostic %"PRId64"= 0x%02x" "\n", addr, ret);
#line 1628 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_EMPTY_SLOT_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_EMPTY_SLOT_WRITE) || \
    false)

static inline void trace_empty_slot_write(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char *name)
{
    if (trace_event_get_state(TRACE_EMPTY_SLOT_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 70 "../xemu/hw/misc/trace-events"
            qemu_log("empty_slot_write " "wr addr:0x%04"PRIx64" data:0x%0*"PRIx64" size %u [%s]" "\n", addr, width, value, size, name);
#line 1643 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE) || \
    false)

static inline void trace_slavio_misc_update_irq_raise(void)
{
    if (trace_event_get_state(TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 73 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_misc_update_irq_raise " "Raise IRQ" "\n");
#line 1658 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER) || \
    false)

static inline void trace_slavio_misc_update_irq_lower(void)
{
    if (trace_event_get_state(TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 74 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_misc_update_irq_lower " "Lower IRQ" "\n");
#line 1673 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_SET_POWER_FAIL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_SET_POWER_FAIL) || \
    false)

static inline void trace_slavio_set_power_fail(int power_failing, uint8_t config)
{
    if (trace_event_get_state(TRACE_SLAVIO_SET_POWER_FAIL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 75 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_set_power_fail " "Power fail: %d, config: %d" "\n", power_failing, config);
#line 1688 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_CFG_MEM_WRITEB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_CFG_MEM_WRITEB) || \
    false)

static inline void trace_slavio_cfg_mem_writeb(uint32_t val)
{
    if (trace_event_get_state(TRACE_SLAVIO_CFG_MEM_WRITEB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 76 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_cfg_mem_writeb " "Write config 0x%02x" "\n", val);
#line 1703 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_CFG_MEM_READB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_CFG_MEM_READB) || \
    false)

static inline void trace_slavio_cfg_mem_readb(uint32_t ret)
{
    if (trace_event_get_state(TRACE_SLAVIO_CFG_MEM_READB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 77 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_cfg_mem_readb " "Read config 0x%02x" "\n", ret);
#line 1718 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_DIAG_MEM_WRITEB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_DIAG_MEM_WRITEB) || \
    false)

static inline void trace_slavio_diag_mem_writeb(uint32_t val)
{
    if (trace_event_get_state(TRACE_SLAVIO_DIAG_MEM_WRITEB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 78 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_diag_mem_writeb " "Write diag 0x%02x" "\n", val);
#line 1733 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_DIAG_MEM_READB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_DIAG_MEM_READB) || \
    false)

static inline void trace_slavio_diag_mem_readb(uint32_t ret)
{
    if (trace_event_get_state(TRACE_SLAVIO_DIAG_MEM_READB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 79 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_diag_mem_readb " "Read diag 0x%02x" "\n", ret);
#line 1748 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_MDM_MEM_WRITEB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_MDM_MEM_WRITEB) || \
    false)

static inline void trace_slavio_mdm_mem_writeb(uint32_t val)
{
    if (trace_event_get_state(TRACE_SLAVIO_MDM_MEM_WRITEB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 80 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_mdm_mem_writeb " "Write modem control 0x%02x" "\n", val);
#line 1763 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_MDM_MEM_READB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_MDM_MEM_READB) || \
    false)

static inline void trace_slavio_mdm_mem_readb(uint32_t ret)
{
    if (trace_event_get_state(TRACE_SLAVIO_MDM_MEM_READB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 81 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_mdm_mem_readb " "Read modem control 0x%02x" "\n", ret);
#line 1778 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_AUX1_MEM_WRITEB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_AUX1_MEM_WRITEB) || \
    false)

static inline void trace_slavio_aux1_mem_writeb(uint32_t val)
{
    if (trace_event_get_state(TRACE_SLAVIO_AUX1_MEM_WRITEB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 82 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_aux1_mem_writeb " "Write aux1 0x%02x" "\n", val);
#line 1793 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_AUX1_MEM_READB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_AUX1_MEM_READB) || \
    false)

static inline void trace_slavio_aux1_mem_readb(uint32_t ret)
{
    if (trace_event_get_state(TRACE_SLAVIO_AUX1_MEM_READB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 83 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_aux1_mem_readb " "Read aux1 0x%02x" "\n", ret);
#line 1808 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_AUX2_MEM_WRITEB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_AUX2_MEM_WRITEB) || \
    false)

static inline void trace_slavio_aux2_mem_writeb(uint32_t val)
{
    if (trace_event_get_state(TRACE_SLAVIO_AUX2_MEM_WRITEB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 84 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_aux2_mem_writeb " "Write aux2 0x%02x" "\n", val);
#line 1823 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_AUX2_MEM_READB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_AUX2_MEM_READB) || \
    false)

static inline void trace_slavio_aux2_mem_readb(uint32_t ret)
{
    if (trace_event_get_state(TRACE_SLAVIO_AUX2_MEM_READB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 85 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_aux2_mem_readb " "Read aux2 0x%02x" "\n", ret);
#line 1838 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_APC_MEM_WRITEB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APC_MEM_WRITEB) || \
    false)

static inline void trace_apc_mem_writeb(uint32_t val)
{
    if (trace_event_get_state(TRACE_APC_MEM_WRITEB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 86 "../xemu/hw/misc/trace-events"
            qemu_log("apc_mem_writeb " "Write power management 0x%02x" "\n", val);
#line 1853 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_APC_MEM_READB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_APC_MEM_READB) || \
    false)

static inline void trace_apc_mem_readb(uint32_t ret)
{
    if (trace_event_get_state(TRACE_APC_MEM_READB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 87 "../xemu/hw/misc/trace-events"
            qemu_log("apc_mem_readb " "Read power management 0x%02x" "\n", ret);
#line 1868 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_SYSCTRL_MEM_WRITEL) || \
    false)

static inline void trace_slavio_sysctrl_mem_writel(uint32_t val)
{
    if (trace_event_get_state(TRACE_SLAVIO_SYSCTRL_MEM_WRITEL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 88 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_sysctrl_mem_writel " "Write system control 0x%08x" "\n", val);
#line 1883 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_SYSCTRL_MEM_READL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_SYSCTRL_MEM_READL) || \
    false)

static inline void trace_slavio_sysctrl_mem_readl(uint32_t ret)
{
    if (trace_event_get_state(TRACE_SLAVIO_SYSCTRL_MEM_READL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 89 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_sysctrl_mem_readl " "Read system control 0x%08x" "\n", ret);
#line 1898 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_LED_MEM_WRITEW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_LED_MEM_WRITEW) || \
    false)

static inline void trace_slavio_led_mem_writew(uint32_t val)
{
    if (trace_event_get_state(TRACE_SLAVIO_LED_MEM_WRITEW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 90 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_led_mem_writew " "Write diagnostic LED 0x%04x" "\n", val);
#line 1913 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_SLAVIO_LED_MEM_READW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_LED_MEM_READW) || \
    false)

static inline void trace_slavio_led_mem_readw(uint32_t ret)
{
    if (trace_event_get_state(TRACE_SLAVIO_LED_MEM_READW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 91 "../xemu/hw/misc/trace-events"
            qemu_log("slavio_led_mem_readw " "Read diagnostic LED 0x%04x" "\n", ret);
#line 1928 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_SBC_IGNORE_CMD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SBC_IGNORE_CMD) || \
    false)

static inline void trace_aspeed_sbc_ignore_cmd(uint32_t cmd)
{
    if (trace_event_get_state(TRACE_ASPEED_SBC_IGNORE_CMD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 94 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_sbc_ignore_cmd " "Ignoring command 0x%" PRIx32 "\n", cmd);
#line 1943 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_SBC_HANDLE_CMD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SBC_HANDLE_CMD) || \
    false)

static inline void trace_aspeed_sbc_handle_cmd(uint32_t cmd, uint32_t addr, bool ret)
{
    if (trace_event_get_state(TRACE_ASPEED_SBC_HANDLE_CMD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 95 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_sbc_handle_cmd " "Handling command 0x%" PRIx32 " for OTP addr 0x%" PRIx32 " Result: %d" "\n", cmd, addr, ret);
#line 1958 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_SBC_OTP_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SBC_OTP_READ) || \
    false)

static inline void trace_aspeed_sbc_otp_read(uint32_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_SBC_OTP_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 96 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_sbc_otp_read " "OTP Memory read: addr 0x%" PRIx32 " value 0x%" PRIx32 "\n", addr, value);
#line 1973 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_SBC_OTP_PROG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SBC_OTP_PROG) || \
    false)

static inline void trace_aspeed_sbc_otp_prog(uint32_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_SBC_OTP_PROG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 97 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_sbc_otp_prog " "OTP Memory write: addr 0x%" PRIx32 " value 0x%" PRIx32 "\n", addr, value);
#line 1988 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_SCU_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SCU_WRITE) || \
    false)

static inline void trace_aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_SCU_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 100 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_scu_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data);
#line 2003 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_SCU_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SCU_READ) || \
    false)

static inline void trace_aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_SCU_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 101 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_scu_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data);
#line 2018 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_AST2700_SCU_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_AST2700_SCU_WRITE) || \
    false)

static inline void trace_aspeed_ast2700_scu_write(uint64_t offset, unsigned size, uint32_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_AST2700_SCU_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 102 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_ast2700_scu_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data);
#line 2033 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_AST2700_SCU_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_AST2700_SCU_READ) || \
    false)

static inline void trace_aspeed_ast2700_scu_read(uint64_t offset, unsigned size, uint32_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_AST2700_SCU_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 103 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_ast2700_scu_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data);
#line 2048 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_AST2700_SCUIO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_AST2700_SCUIO_WRITE) || \
    false)

static inline void trace_aspeed_ast2700_scuio_write(uint64_t offset, unsigned size, uint32_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_AST2700_SCUIO_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 104 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_ast2700_scuio_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data);
#line 2063 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_AST2700_SCUIO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_AST2700_SCUIO_READ) || \
    false)

static inline void trace_aspeed_ast2700_scuio_read(uint64_t offset, unsigned size, uint32_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_AST2700_SCUIO_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 105 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_ast2700_scuio_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data);
#line 2078 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MPS2_SCC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MPS2_SCC_READ) || \
    false)

static inline void trace_mps2_scc_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_MPS2_SCC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 108 "../xemu/hw/misc/trace-events"
            qemu_log("mps2_scc_read " "MPS2 SCC read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 2093 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MPS2_SCC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MPS2_SCC_WRITE) || \
    false)

static inline void trace_mps2_scc_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_MPS2_SCC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 109 "../xemu/hw/misc/trace-events"
            qemu_log("mps2_scc_write " "MPS2 SCC write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 2108 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MPS2_SCC_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MPS2_SCC_RESET) || \
    false)

static inline void trace_mps2_scc_reset(void)
{
    if (trace_event_get_state(TRACE_MPS2_SCC_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 110 "../xemu/hw/misc/trace-events"
            qemu_log("mps2_scc_reset " "MPS2 SCC: reset" "\n");
#line 2123 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MPS2_SCC_CFG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MPS2_SCC_CFG_WRITE) || \
    false)

static inline void trace_mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value)
{
    if (trace_event_get_state(TRACE_MPS2_SCC_CFG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 111 "../xemu/hw/misc/trace-events"
            qemu_log("mps2_scc_cfg_write " "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 "\n", function, device, value);
#line 2138 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MPS2_SCC_CFG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MPS2_SCC_CFG_READ) || \
    false)

static inline void trace_mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value)
{
    if (trace_event_get_state(TRACE_MPS2_SCC_CFG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 112 "../xemu/hw/misc/trace-events"
            qemu_log("mps2_scc_cfg_read " "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 "\n", function, device, value);
#line 2153 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MPS2_FPGAIO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MPS2_FPGAIO_READ) || \
    false)

static inline void trace_mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_MPS2_FPGAIO_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 115 "../xemu/hw/misc/trace-events"
            qemu_log("mps2_fpgaio_read " "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 2168 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MPS2_FPGAIO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MPS2_FPGAIO_WRITE) || \
    false)

static inline void trace_mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_MPS2_FPGAIO_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 116 "../xemu/hw/misc/trace-events"
            qemu_log("mps2_fpgaio_write " "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 2183 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MPS2_FPGAIO_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MPS2_FPGAIO_RESET) || \
    false)

static inline void trace_mps2_fpgaio_reset(void)
{
    if (trace_event_get_state(TRACE_MPS2_FPGAIO_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 117 "../xemu/hw/misc/trace-events"
            qemu_log("mps2_fpgaio_reset " "MPS2 FPGAIO: reset" "\n");
#line 2198 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MSF2_SYSREG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSF2_SYSREG_WRITE) || \
    false)

static inline void trace_msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev)
{
    if (trace_event_get_state(TRACE_MSF2_SYSREG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 120 "../xemu/hw/misc/trace-events"
            qemu_log("msf2_sysreg_write " "msf2-sysreg write: addr 0x%08" PRIx64 " data 0x%" PRIx32 " prev 0x%" PRIx32 "\n", offset, val, prev);
#line 2213 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MSF2_SYSREG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSF2_SYSREG_READ) || \
    false)

static inline void trace_msf2_sysreg_read(uint64_t offset, uint32_t val)
{
    if (trace_event_get_state(TRACE_MSF2_SYSREG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 121 "../xemu/hw/misc/trace-events"
            qemu_log("msf2_sysreg_read " "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08" PRIx32 "\n", offset, val);
#line 2228 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSF2_SYSREG_WRITE_PLL_STATUS) || \
    false)

static inline void trace_msf2_sysreg_write_pll_status(void)
{
    if (trace_event_get_state(TRACE_MSF2_SYSREG_WRITE_PLL_STATUS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 122 "../xemu/hw/misc/trace-events"
            qemu_log("msf2_sysreg_write_pll_status " "Invalid write to read only PLL status register" "\n");
#line 2243 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX7_GPR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX7_GPR_READ) || \
    false)

static inline void trace_imx7_gpr_read(uint64_t offset)
{
    if (trace_event_get_state(TRACE_IMX7_GPR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 125 "../xemu/hw/misc/trace-events"
            qemu_log("imx7_gpr_read " "addr 0x%08" PRIx64 "\n", offset);
#line 2258 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX7_GPR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX7_GPR_WRITE) || \
    false)

static inline void trace_imx7_gpr_write(uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_IMX7_GPR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 126 "../xemu/hw/misc/trace-events"
            qemu_log("imx7_gpr_write " "addr 0x%08" PRIx64 "value 0x%08" PRIx64 "\n", offset, value);
#line 2273 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX7_SNVS_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX7_SNVS_READ) || \
    false)

static inline void trace_imx7_snvs_read(uint64_t offset, uint64_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_IMX7_SNVS_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 129 "../xemu/hw/misc/trace-events"
            qemu_log("imx7_snvs_read " "i.MX SNVS read: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" "\n", offset, value, size);
#line 2288 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX7_SNVS_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX7_SNVS_WRITE) || \
    false)

static inline void trace_imx7_snvs_write(uint64_t offset, uint64_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_IMX7_SNVS_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 130 "../xemu/hw/misc/trace-events"
            qemu_log("imx7_snvs_write " "i.MX SNVS write: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" "\n", offset, value, size);
#line 2303 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MOS6522_SET_COUNTER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MOS6522_SET_COUNTER) || \
    false)

static inline void trace_mos6522_set_counter(int index, unsigned int val)
{
    if (trace_event_get_state(TRACE_MOS6522_SET_COUNTER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 133 "../xemu/hw/misc/trace-events"
            qemu_log("mos6522_set_counter " "T%d.counter=%d" "\n", index, val);
#line 2318 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MOS6522_GET_NEXT_IRQ_TIME_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MOS6522_GET_NEXT_IRQ_TIME) || \
    false)

static inline void trace_mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta)
{
    if (trace_event_get_state(TRACE_MOS6522_GET_NEXT_IRQ_TIME)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 134 "../xemu/hw/misc/trace-events"
            qemu_log("mos6522_get_next_irq_time " "latch=%d counter=0x%"PRIx64 " delta_next=0x%"PRIx64 "\n", latch, d, delta);
#line 2333 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MOS6522_SET_SR_INT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MOS6522_SET_SR_INT) || \
    false)

static inline void trace_mos6522_set_sr_int(void)
{
    if (trace_event_get_state(TRACE_MOS6522_SET_SR_INT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 135 "../xemu/hw/misc/trace-events"
            qemu_log("mos6522_set_sr_int " "set sr_int" "\n");
#line 2348 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MOS6522_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MOS6522_WRITE) || \
    false)

static inline void trace_mos6522_write(uint64_t addr, const char *name, uint64_t val)
{
    if (trace_event_get_state(TRACE_MOS6522_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 136 "../xemu/hw/misc/trace-events"
            qemu_log("mos6522_write " "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64 "\n", addr, name, val);
#line 2363 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_MOS6522_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MOS6522_READ) || \
    false)

static inline void trace_mos6522_read(uint64_t addr, const char *name, unsigned val)
{
    if (trace_event_get_state(TRACE_MOS6522_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 137 "../xemu/hw/misc/trace-events"
            qemu_log("mos6522_read " "reg=0x%"PRIx64 " [%s] val=0x%x" "\n", addr, name, val);
#line 2378 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM_CLK_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_CLK_READ) || \
    false)

static inline void trace_npcm_clk_read(uint64_t offset, uint32_t value)
{
    if (trace_event_get_state(TRACE_NPCM_CLK_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 140 "../xemu/hw/misc/trace-events"
            qemu_log("npcm_clk_read " " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", offset, value);
#line 2393 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM_CLK_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_CLK_WRITE) || \
    false)

static inline void trace_npcm_clk_write(uint64_t offset, uint32_t value)
{
    if (trace_event_get_state(TRACE_NPCM_CLK_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 141 "../xemu/hw/misc/trace-events"
            qemu_log("npcm_clk_write " "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", offset, value);
#line 2408 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM_GCR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GCR_READ) || \
    false)

static inline void trace_npcm_gcr_read(uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_NPCM_GCR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 144 "../xemu/hw/misc/trace-events"
            qemu_log("npcm_gcr_read " " offset: 0x%04" PRIx64 " value: 0x%08" PRIx64 "\n", offset, value);
#line 2423 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM_GCR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GCR_WRITE) || \
    false)

static inline void trace_npcm_gcr_write(uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_NPCM_GCR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 145 "../xemu/hw/misc/trace-events"
            qemu_log("npcm_gcr_write " "offset: 0x%04" PRIx64 " value: 0x%08" PRIx64 "\n", offset, value);
#line 2438 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM7XX_MFT_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_MFT_READ) || \
    false)

static inline void trace_npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_MFT_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 148 "../xemu/hw/misc/trace-events"
            qemu_log("npcm7xx_mft_read " "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 "\n", name, offset, value);
#line 2453 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM7XX_MFT_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_MFT_WRITE) || \
    false)

static inline void trace_npcm7xx_mft_write(const char *name, uint64_t offset, uint16_t value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_MFT_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 149 "../xemu/hw/misc/trace-events"
            qemu_log("npcm7xx_mft_write " "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 "\n", name, offset, value);
#line 2468 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM7XX_MFT_RPM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_MFT_RPM) || \
    false)

static inline void trace_npcm7xx_mft_rpm(const char *clock, uint32_t clock_hz, int state, int32_t cnt, uint32_t rpm, uint32_t duty)
{
    if (trace_event_get_state(TRACE_NPCM7XX_MFT_RPM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 150 "../xemu/hw/misc/trace-events"
            qemu_log("npcm7xx_mft_rpm " " fan clk: %s clock_hz: %" PRIu32 ", state: %d, cnt: %" PRIi32 ", rpm: %" PRIu32 ", duty: %" PRIu32 "\n", clock, clock_hz, state, cnt, rpm, duty);
#line 2483 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM7XX_MFT_CAPTURE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_MFT_CAPTURE) || \
    false)

static inline void trace_npcm7xx_mft_capture(const char *name, int irq_level)
{
    if (trace_event_get_state(TRACE_NPCM7XX_MFT_CAPTURE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 151 "../xemu/hw/misc/trace-events"
            qemu_log("npcm7xx_mft_capture " "%s: level: %d" "\n", name, irq_level);
#line 2498 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM7XX_MFT_UPDATE_CLOCK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_MFT_UPDATE_CLOCK) || \
    false)

static inline void trace_npcm7xx_mft_update_clock(const char *name, uint16_t sel, uint64_t clock_period, uint64_t prescaled_clock_period)
{
    if (trace_event_get_state(TRACE_NPCM7XX_MFT_UPDATE_CLOCK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 152 "../xemu/hw/misc/trace-events"
            qemu_log("npcm7xx_mft_update_clock " "%s: sel: 0x%02" PRIx16 ", period: %" PRIu64 ", prescaled: %" PRIu64 "\n", name, sel, clock_period, prescaled_clock_period);
#line 2513 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM7XX_MFT_SET_DUTY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_MFT_SET_DUTY) || \
    false)

static inline void trace_npcm7xx_mft_set_duty(const char *name, int n, int value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_MFT_SET_DUTY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 153 "../xemu/hw/misc/trace-events"
            qemu_log("npcm7xx_mft_set_duty " "%s[%d]: %d" "\n", name, n, value);
#line 2528 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM7XX_RNG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_RNG_READ) || \
    false)

static inline void trace_npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_NPCM7XX_RNG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 156 "../xemu/hw/misc/trace-events"
            qemu_log("npcm7xx_rng_read " "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" "\n", offset, value, size);
#line 2543 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM7XX_RNG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_RNG_WRITE) || \
    false)

static inline void trace_npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_NPCM7XX_RNG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 157 "../xemu/hw/misc/trace-events"
            qemu_log("npcm7xx_rng_write " "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" "\n", offset, value, size);
#line 2558 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM7XX_PWM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_PWM_READ) || \
    false)

static inline void trace_npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_PWM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 160 "../xemu/hw/misc/trace-events"
            qemu_log("npcm7xx_pwm_read " "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", id, offset, value);
#line 2573 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM7XX_PWM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_PWM_WRITE) || \
    false)

static inline void trace_npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_PWM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 161 "../xemu/hw/misc/trace-events"
            qemu_log("npcm7xx_pwm_write " "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", id, offset, value);
#line 2588 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM7XX_PWM_UPDATE_FREQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_PWM_UPDATE_FREQ) || \
    false)

static inline void trace_npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_PWM_UPDATE_FREQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 162 "../xemu/hw/misc/trace-events"
            qemu_log("npcm7xx_pwm_update_freq " "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" "\n", id, index, old_value, new_value);
#line 2603 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_NPCM7XX_PWM_UPDATE_DUTY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_PWM_UPDATE_DUTY) || \
    false)

static inline void trace_npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_PWM_UPDATE_DUTY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 163 "../xemu/hw/misc/trace-events"
            qemu_log("npcm7xx_pwm_update_duty " "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" "\n", id, index, old_value, new_value);
#line 2618 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32_RCC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32_RCC_READ) || \
    false)

static inline void trace_stm32_rcc_read(uint64_t addr, uint64_t data)
{
    if (trace_event_get_state(TRACE_STM32_RCC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 166 "../xemu/hw/misc/trace-events"
            qemu_log("stm32_rcc_read " "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data);
#line 2633 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32_RCC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32_RCC_WRITE) || \
    false)

static inline void trace_stm32_rcc_write(uint64_t addr, uint64_t data)
{
    if (trace_event_get_state(TRACE_STM32_RCC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 167 "../xemu/hw/misc/trace-events"
            qemu_log("stm32_rcc_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data);
#line 2648 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32_RCC_PULSE_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32_RCC_PULSE_ENABLE) || \
    false)

static inline void trace_stm32_rcc_pulse_enable(int line, int level)
{
    if (trace_event_get_state(TRACE_STM32_RCC_PULSE_ENABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 168 "../xemu/hw/misc/trace-events"
            qemu_log("stm32_rcc_pulse_enable " "Enable: %d to %d" "\n", line, level);
#line 2663 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32_RCC_PULSE_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32_RCC_PULSE_RESET) || \
    false)

static inline void trace_stm32_rcc_pulse_reset(int line, int level)
{
    if (trace_event_get_state(TRACE_STM32_RCC_PULSE_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 169 "../xemu/hw/misc/trace-events"
            qemu_log("stm32_rcc_pulse_reset " "Reset: %d to %d" "\n", line, level);
#line 2678 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32F4XX_SYSCFG_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_SYSCFG_SET_IRQ) || \
    false)

static inline void trace_stm32f4xx_syscfg_set_irq(int gpio, int line, int level)
{
    if (trace_event_get_state(TRACE_STM32F4XX_SYSCFG_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 172 "../xemu/hw/misc/trace-events"
            qemu_log("stm32f4xx_syscfg_set_irq " "Interrupt: GPIO: %d, Line: %d; Level: %d" "\n", gpio, line, level);
#line 2693 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32F4XX_PULSE_EXTI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_PULSE_EXTI) || \
    false)

static inline void trace_stm32f4xx_pulse_exti(int irq)
{
    if (trace_event_get_state(TRACE_STM32F4XX_PULSE_EXTI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 173 "../xemu/hw/misc/trace-events"
            qemu_log("stm32f4xx_pulse_exti " "Pulse EXTI: %d" "\n", irq);
#line 2708 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32F4XX_SYSCFG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_SYSCFG_READ) || \
    false)

static inline void trace_stm32f4xx_syscfg_read(uint64_t addr)
{
    if (trace_event_get_state(TRACE_STM32F4XX_SYSCFG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 174 "../xemu/hw/misc/trace-events"
            qemu_log("stm32f4xx_syscfg_read " "reg read: addr: 0x%" PRIx64 " " "\n", addr);
#line 2723 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32F4XX_SYSCFG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_SYSCFG_WRITE) || \
    false)

static inline void trace_stm32f4xx_syscfg_write(uint64_t addr, uint64_t data)
{
    if (trace_event_get_state(TRACE_STM32F4XX_SYSCFG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 175 "../xemu/hw/misc/trace-events"
            qemu_log("stm32f4xx_syscfg_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data);
#line 2738 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32F4XX_EXTI_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_EXTI_SET_IRQ) || \
    false)

static inline void trace_stm32f4xx_exti_set_irq(int irq, int level)
{
    if (trace_event_get_state(TRACE_STM32F4XX_EXTI_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 178 "../xemu/hw/misc/trace-events"
            qemu_log("stm32f4xx_exti_set_irq " "Set EXTI: %d to %d" "\n", irq, level);
#line 2753 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32F4XX_EXTI_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_EXTI_READ) || \
    false)

static inline void trace_stm32f4xx_exti_read(uint64_t addr)
{
    if (trace_event_get_state(TRACE_STM32F4XX_EXTI_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 179 "../xemu/hw/misc/trace-events"
            qemu_log("stm32f4xx_exti_read " "reg read: addr: 0x%" PRIx64 " " "\n", addr);
#line 2768 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32F4XX_EXTI_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_EXTI_WRITE) || \
    false)

static inline void trace_stm32f4xx_exti_write(uint64_t addr, uint64_t data)
{
    if (trace_event_get_state(TRACE_STM32F4XX_EXTI_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 180 "../xemu/hw/misc/trace-events"
            qemu_log("stm32f4xx_exti_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data);
#line 2783 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_SYSCFG_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_SYSCFG_SET_IRQ) || \
    false)

static inline void trace_stm32l4x5_syscfg_set_irq(int gpio, int line, int level)
{
    if (trace_event_get_state(TRACE_STM32L4X5_SYSCFG_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 183 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_syscfg_set_irq " "irq from GPIO: %d, line: %d, level: %d" "\n", gpio, line, level);
#line 2798 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI) || \
    false)

static inline void trace_stm32l4x5_syscfg_forward_exti(int irq)
{
    if (trace_event_get_state(TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 184 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_syscfg_forward_exti " "irq %d forwarded to EXTI" "\n", irq);
#line 2813 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_SYSCFG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_SYSCFG_READ) || \
    false)

static inline void trace_stm32l4x5_syscfg_read(uint64_t addr)
{
    if (trace_event_get_state(TRACE_STM32L4X5_SYSCFG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 185 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_syscfg_read " "reg read: addr: 0x%" PRIx64 " " "\n", addr);
#line 2828 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_SYSCFG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_SYSCFG_WRITE) || \
    false)

static inline void trace_stm32l4x5_syscfg_write(uint64_t addr, uint64_t data)
{
    if (trace_event_get_state(TRACE_STM32L4X5_SYSCFG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 186 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_syscfg_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data);
#line 2843 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_EXTI_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_EXTI_SET_IRQ) || \
    false)

static inline void trace_stm32l4x5_exti_set_irq(int irq, int level)
{
    if (trace_event_get_state(TRACE_STM32L4X5_EXTI_SET_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 189 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_exti_set_irq " "Set EXTI: %d to %d" "\n", irq, level);
#line 2858 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_EXTI_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_EXTI_READ) || \
    false)

static inline void trace_stm32l4x5_exti_read(uint64_t addr, uint64_t data)
{
    if (trace_event_get_state(TRACE_STM32L4X5_EXTI_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 190 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_exti_read " "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data);
#line 2873 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_EXTI_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_EXTI_WRITE) || \
    false)

static inline void trace_stm32l4x5_exti_write(uint64_t addr, uint64_t data)
{
    if (trace_event_get_state(TRACE_STM32L4X5_EXTI_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 191 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_exti_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data);
#line 2888 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_RCC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_READ) || \
    false)

static inline void trace_stm32l4x5_rcc_read(uint64_t addr, uint32_t data)
{
    if (trace_event_get_state(TRACE_STM32L4X5_RCC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 194 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_rcc_read " "RCC: Read <0x%" PRIx64 "> -> 0x%" PRIx32 "\n", addr, data);
#line 2903 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_RCC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_WRITE) || \
    false)

static inline void trace_stm32l4x5_rcc_write(uint64_t addr, uint32_t data)
{
    if (trace_event_get_state(TRACE_STM32L4X5_RCC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 195 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_rcc_write " "RCC: Write <0x%" PRIx64 "> <- 0x%" PRIx32 "\n", addr, data);
#line 2918 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_RCC_MUX_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_MUX_ENABLE) || \
    false)

static inline void trace_stm32l4x5_rcc_mux_enable(uint32_t mux_id)
{
    if (trace_event_get_state(TRACE_STM32L4X5_RCC_MUX_ENABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 196 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_rcc_mux_enable " "RCC: Mux %d enabled" "\n", mux_id);
#line 2933 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_RCC_MUX_DISABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_MUX_DISABLE) || \
    false)

static inline void trace_stm32l4x5_rcc_mux_disable(uint32_t mux_id)
{
    if (trace_event_get_state(TRACE_STM32L4X5_RCC_MUX_DISABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 197 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_rcc_mux_disable " "RCC: Mux %d disabled" "\n", mux_id);
#line 2948 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_MUX_SET_FACTOR) || \
    false)

static inline void trace_stm32l4x5_rcc_mux_set_factor(uint32_t mux_id, uint32_t old_multiplier, uint32_t new_multiplier, uint32_t old_divider, uint32_t new_divider)
{
    if (trace_event_get_state(TRACE_STM32L4X5_RCC_MUX_SET_FACTOR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 198 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_rcc_mux_set_factor " "RCC: Mux %d factor changed: multiplier (%u -> %u), divider (%u -> %u)" "\n", mux_id, old_multiplier, new_multiplier, old_divider, new_divider);
#line 2963 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_RCC_MUX_SET_SRC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_MUX_SET_SRC) || \
    false)

static inline void trace_stm32l4x5_rcc_mux_set_src(uint32_t mux_id, uint32_t old_src, uint32_t new_src)
{
    if (trace_event_get_state(TRACE_STM32L4X5_RCC_MUX_SET_SRC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 199 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_rcc_mux_set_src " "RCC: Mux %d source changed: from %u to %u" "\n", mux_id, old_src, new_src);
#line 2978 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_RCC_MUX_UPDATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_MUX_UPDATE) || \
    false)

static inline void trace_stm32l4x5_rcc_mux_update(uint32_t mux_id, uint32_t src, uint64_t src_freq, uint32_t multiplier, uint32_t divider)
{
    if (trace_event_get_state(TRACE_STM32L4X5_RCC_MUX_UPDATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 200 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_rcc_mux_update " "RCC: Mux %d src %d update: src_freq %" PRIu64 " multiplier %" PRIu32 " divider %" PRIu32 "\n", mux_id, src, src_freq, multiplier, divider);
#line 2993 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER) || \
    false)

static inline void trace_stm32l4x5_rcc_pll_set_vco_multiplier(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier)
{
    if (trace_event_get_state(TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 201 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_rcc_pll_set_vco_multiplier " "RCC: PLL %u: vco_multiplier changed (%u -> %u)" "\n", pll_id, old_multiplier, new_multiplier);
#line 3008 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE) || \
    false)

static inline void trace_stm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id)
{
    if (trace_event_get_state(TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 202 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_rcc_pll_channel_enable " "RCC: PLL %u, channel %u enabled" "\n", pll_id, channel_id);
#line 3023 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE) || \
    false)

static inline void trace_stm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id)
{
    if (trace_event_get_state(TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 203 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_rcc_pll_channel_disable " "RCC: PLL %u, channel %u disabled" "\n", pll_id, channel_id);
#line 3038 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER) || \
    false)

static inline void trace_stm32l4x5_rcc_pll_set_channel_divider(uint32_t pll_id, uint32_t channel_id, uint32_t old_divider, uint32_t new_divider)
{
    if (trace_event_get_state(TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 204 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_rcc_pll_set_channel_divider " "RCC: PLL %u, channel %u: divider changed (%u -> %u)" "\n", pll_id, channel_id, old_divider, new_divider);
#line 3053 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_STM32L4X5_RCC_PLL_UPDATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_PLL_UPDATE) || \
    false)

static inline void trace_stm32l4x5_rcc_pll_update(uint32_t pll_id, uint32_t channel_id, uint64_t vco_freq, uint64_t old_freq, uint64_t new_freq)
{
    if (trace_event_get_state(TRACE_STM32L4X5_RCC_PLL_UPDATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 205 "../xemu/hw/misc/trace-events"
            qemu_log("stm32l4x5_rcc_pll_update " "RCC: PLL %d channel %d update: vco_freq %" PRIu64 " old_freq %" PRIu64 " new_freq %" PRIu64 "\n", pll_id, channel_id, vco_freq, old_freq, new_freq);
#line 3068 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_MPC_REG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_MPC_REG_READ) || \
    false)

static inline void trace_tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_TZ_MPC_REG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 208 "../xemu/hw/misc/trace-events"
            qemu_log("tz_mpc_reg_read " "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3083 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_MPC_REG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_MPC_REG_WRITE) || \
    false)

static inline void trace_tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_TZ_MPC_REG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 209 "../xemu/hw/misc/trace-events"
            qemu_log("tz_mpc_reg_write " "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3098 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_MPC_MEM_BLOCKED_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_MPC_MEM_BLOCKED_READ) || \
    false)

static inline void trace_tz_mpc_mem_blocked_read(uint64_t addr, unsigned size, bool secure)
{
    if (trace_event_get_state(TRACE_TZ_MPC_MEM_BLOCKED_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 210 "../xemu/hw/misc/trace-events"
            qemu_log("tz_mpc_mem_blocked_read " "TZ MPC blocked read: offset 0x%" PRIx64 " size %u secure %d" "\n", addr, size, secure);
#line 3113 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_MPC_MEM_BLOCKED_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_MPC_MEM_BLOCKED_WRITE) || \
    false)

static inline void trace_tz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secure)
{
    if (trace_event_get_state(TRACE_TZ_MPC_MEM_BLOCKED_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 211 "../xemu/hw/misc/trace-events"
            qemu_log("tz_mpc_mem_blocked_write " "TZ MPC blocked write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", addr, data, size, secure);
#line 3128 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_MPC_TRANSLATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_MPC_TRANSLATE) || \
    false)

static inline void trace_tz_mpc_translate(uint64_t addr, int flags, const char *idx, const char *res)
{
    if (trace_event_get_state(TRACE_TZ_MPC_TRANSLATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 212 "../xemu/hw/misc/trace-events"
            qemu_log("tz_mpc_translate " "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s" "\n", addr, flags, idx, res);
#line 3143 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_MPC_IOMMU_NOTIFY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_MPC_IOMMU_NOTIFY) || \
    false)

static inline void trace_tz_mpc_iommu_notify(uint64_t addr)
{
    if (trace_event_get_state(TRACE_TZ_MPC_IOMMU_NOTIFY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 213 "../xemu/hw/misc/trace-events"
            qemu_log("tz_mpc_iommu_notify " "TZ MPC iommu: notifying UNMAP/MAP for 0x%" PRIx64 "\n", addr);
#line 3158 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_MSC_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_MSC_RESET) || \
    false)

static inline void trace_tz_msc_reset(void)
{
    if (trace_event_get_state(TRACE_TZ_MSC_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 216 "../xemu/hw/misc/trace-events"
            qemu_log("tz_msc_reset " "TZ MSC: reset" "\n");
#line 3173 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_MSC_CFG_NONSEC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_MSC_CFG_NONSEC) || \
    false)

static inline void trace_tz_msc_cfg_nonsec(int level)
{
    if (trace_event_get_state(TRACE_TZ_MSC_CFG_NONSEC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 217 "../xemu/hw/misc/trace-events"
            qemu_log("tz_msc_cfg_nonsec " "TZ MSC: cfg_nonsec = %d" "\n", level);
#line 3188 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_MSC_CFG_SEC_RESP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_MSC_CFG_SEC_RESP) || \
    false)

static inline void trace_tz_msc_cfg_sec_resp(int level)
{
    if (trace_event_get_state(TRACE_TZ_MSC_CFG_SEC_RESP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 218 "../xemu/hw/misc/trace-events"
            qemu_log("tz_msc_cfg_sec_resp " "TZ MSC: cfg_sec_resp = %d" "\n", level);
#line 3203 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_MSC_IRQ_CLEAR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_MSC_IRQ_CLEAR) || \
    false)

static inline void trace_tz_msc_irq_clear(int level)
{
    if (trace_event_get_state(TRACE_TZ_MSC_IRQ_CLEAR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 219 "../xemu/hw/misc/trace-events"
            qemu_log("tz_msc_irq_clear " "TZ MSC: int_clear = %d" "\n", level);
#line 3218 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_MSC_UPDATE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_MSC_UPDATE_IRQ) || \
    false)

static inline void trace_tz_msc_update_irq(int level)
{
    if (trace_event_get_state(TRACE_TZ_MSC_UPDATE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 220 "../xemu/hw/misc/trace-events"
            qemu_log("tz_msc_update_irq " "TZ MSC: setting irq line to %d" "\n", level);
#line 3233 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_MSC_ACCESS_BLOCKED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_MSC_ACCESS_BLOCKED) || \
    false)

static inline void trace_tz_msc_access_blocked(uint64_t offset)
{
    if (trace_event_get_state(TRACE_TZ_MSC_ACCESS_BLOCKED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 221 "../xemu/hw/misc/trace-events"
            qemu_log("tz_msc_access_blocked " "TZ MSC: offset 0x%" PRIx64 " access blocked" "\n", offset);
#line 3248 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_PPC_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_RESET) || \
    false)

static inline void trace_tz_ppc_reset(void)
{
    if (trace_event_get_state(TRACE_TZ_PPC_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 224 "../xemu/hw/misc/trace-events"
            qemu_log("tz_ppc_reset " "TZ PPC: reset" "\n");
#line 3263 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_PPC_CFG_NONSEC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_CFG_NONSEC) || \
    false)

static inline void trace_tz_ppc_cfg_nonsec(int n, int level)
{
    if (trace_event_get_state(TRACE_TZ_PPC_CFG_NONSEC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 225 "../xemu/hw/misc/trace-events"
            qemu_log("tz_ppc_cfg_nonsec " "TZ PPC: cfg_nonsec[%d] = %d" "\n", n, level);
#line 3278 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_PPC_CFG_AP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_CFG_AP) || \
    false)

static inline void trace_tz_ppc_cfg_ap(int n, int level)
{
    if (trace_event_get_state(TRACE_TZ_PPC_CFG_AP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 226 "../xemu/hw/misc/trace-events"
            qemu_log("tz_ppc_cfg_ap " "TZ PPC: cfg_ap[%d] = %d" "\n", n, level);
#line 3293 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_PPC_CFG_SEC_RESP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_CFG_SEC_RESP) || \
    false)

static inline void trace_tz_ppc_cfg_sec_resp(int level)
{
    if (trace_event_get_state(TRACE_TZ_PPC_CFG_SEC_RESP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 227 "../xemu/hw/misc/trace-events"
            qemu_log("tz_ppc_cfg_sec_resp " "TZ PPC: cfg_sec_resp = %d" "\n", level);
#line 3308 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_PPC_IRQ_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_IRQ_ENABLE) || \
    false)

static inline void trace_tz_ppc_irq_enable(int level)
{
    if (trace_event_get_state(TRACE_TZ_PPC_IRQ_ENABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 228 "../xemu/hw/misc/trace-events"
            qemu_log("tz_ppc_irq_enable " "TZ PPC: int_enable = %d" "\n", level);
#line 3323 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_PPC_IRQ_CLEAR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_IRQ_CLEAR) || \
    false)

static inline void trace_tz_ppc_irq_clear(int level)
{
    if (trace_event_get_state(TRACE_TZ_PPC_IRQ_CLEAR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 229 "../xemu/hw/misc/trace-events"
            qemu_log("tz_ppc_irq_clear " "TZ PPC: int_clear = %d" "\n", level);
#line 3338 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_PPC_UPDATE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_UPDATE_IRQ) || \
    false)

static inline void trace_tz_ppc_update_irq(int level)
{
    if (trace_event_get_state(TRACE_TZ_PPC_UPDATE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 230 "../xemu/hw/misc/trace-events"
            qemu_log("tz_ppc_update_irq " "TZ PPC: setting irq line to %d" "\n", level);
#line 3353 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_PPC_READ_BLOCKED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_READ_BLOCKED) || \
    false)

static inline void trace_tz_ppc_read_blocked(int n, uint64_t offset, bool secure, bool user)
{
    if (trace_event_get_state(TRACE_TZ_PPC_READ_BLOCKED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 231 "../xemu/hw/misc/trace-events"
            qemu_log("tz_ppc_read_blocked " "TZ PPC: port %d offset 0x%" PRIx64 " read (secure %d user %d) blocked" "\n", n, offset, secure, user);
#line 3368 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_TZ_PPC_WRITE_BLOCKED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_WRITE_BLOCKED) || \
    false)

static inline void trace_tz_ppc_write_blocked(int n, uint64_t offset, bool secure, bool user)
{
    if (trace_event_get_state(TRACE_TZ_PPC_WRITE_BLOCKED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 232 "../xemu/hw/misc/trace-events"
            qemu_log("tz_ppc_write_blocked " "TZ PPC: port %d offset 0x%" PRIx64 " write (secure %d user %d) blocked" "\n", n, offset, secure, user);
#line 3383 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IOTKIT_SECCTL_S_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SECCTL_S_READ) || \
    false)

static inline void trace_iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_IOTKIT_SECCTL_S_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 235 "../xemu/hw/misc/trace-events"
            qemu_log("iotkit_secctl_s_read " "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3398 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IOTKIT_SECCTL_S_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SECCTL_S_WRITE) || \
    false)

static inline void trace_iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_IOTKIT_SECCTL_S_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 236 "../xemu/hw/misc/trace-events"
            qemu_log("iotkit_secctl_s_write " "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3413 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IOTKIT_SECCTL_NS_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SECCTL_NS_READ) || \
    false)

static inline void trace_iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_IOTKIT_SECCTL_NS_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 237 "../xemu/hw/misc/trace-events"
            qemu_log("iotkit_secctl_ns_read " "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3428 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IOTKIT_SECCTL_NS_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SECCTL_NS_WRITE) || \
    false)

static inline void trace_iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_IOTKIT_SECCTL_NS_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 238 "../xemu/hw/misc/trace-events"
            qemu_log("iotkit_secctl_ns_write " "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3443 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_ANALOG_GET_PERIPH_CLK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_ANALOG_GET_PERIPH_CLK) || \
    false)

static inline void trace_imx6_analog_get_periph_clk(uint32_t freq)
{
    if (trace_event_get_state(TRACE_IMX6_ANALOG_GET_PERIPH_CLK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 241 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_analog_get_periph_clk " "freq = %u Hz" "\n", freq);
#line 3458 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_ANALOG_GET_PLL2_CLK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_ANALOG_GET_PLL2_CLK) || \
    false)

static inline void trace_imx6_analog_get_pll2_clk(uint32_t freq)
{
    if (trace_event_get_state(TRACE_IMX6_ANALOG_GET_PLL2_CLK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 242 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_analog_get_pll2_clk " "freq = %u Hz" "\n", freq);
#line 3473 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK) || \
    false)

static inline void trace_imx6_analog_get_pll2_pfd0_clk(uint32_t freq)
{
    if (trace_event_get_state(TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 243 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_analog_get_pll2_pfd0_clk " "freq = %u Hz" "\n", freq);
#line 3488 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK) || \
    false)

static inline void trace_imx6_analog_get_pll2_pfd2_clk(uint32_t freq)
{
    if (trace_event_get_state(TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 244 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_analog_get_pll2_pfd2_clk " "freq = %u Hz" "\n", freq);
#line 3503 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_ANALOG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_ANALOG_READ) || \
    false)

static inline void trace_imx6_analog_read(const char *reg, uint32_t value)
{
    if (trace_event_get_state(TRACE_IMX6_ANALOG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 245 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_analog_read " "reg[%s] => 0x%" PRIx32 "\n", reg, value);
#line 3518 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_ANALOG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_ANALOG_WRITE) || \
    false)

static inline void trace_imx6_analog_write(const char *reg, uint32_t value)
{
    if (trace_event_get_state(TRACE_IMX6_ANALOG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 246 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_analog_write " "reg[%s] <= 0x%" PRIx32 "\n", reg, value);
#line 3533 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_CCM_GET_AHB_CLK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_GET_AHB_CLK) || \
    false)

static inline void trace_imx6_ccm_get_ahb_clk(uint32_t freq)
{
    if (trace_event_get_state(TRACE_IMX6_CCM_GET_AHB_CLK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 247 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_ccm_get_ahb_clk " "freq = %u Hz" "\n", freq);
#line 3548 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_CCM_GET_IPG_CLK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_GET_IPG_CLK) || \
    false)

static inline void trace_imx6_ccm_get_ipg_clk(uint32_t freq)
{
    if (trace_event_get_state(TRACE_IMX6_CCM_GET_IPG_CLK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 248 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_ccm_get_ipg_clk " "freq = %u Hz" "\n", freq);
#line 3563 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_CCM_GET_PER_CLK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_GET_PER_CLK) || \
    false)

static inline void trace_imx6_ccm_get_per_clk(uint32_t freq)
{
    if (trace_event_get_state(TRACE_IMX6_CCM_GET_PER_CLK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 249 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_ccm_get_per_clk " "freq = %u Hz" "\n", freq);
#line 3578 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY) || \
    false)

static inline void trace_imx6_ccm_get_clock_frequency(unsigned clock, uint32_t freq)
{
    if (trace_event_get_state(TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 250 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_ccm_get_clock_frequency " "(Clock = %d) = %u" "\n", clock, freq);
#line 3593 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_CCM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_READ) || \
    false)

static inline void trace_imx6_ccm_read(const char *reg, uint32_t value)
{
    if (trace_event_get_state(TRACE_IMX6_CCM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 251 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_ccm_read " "reg[%s] => 0x%" PRIx32 "\n", reg, value);
#line 3608 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_CCM_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_RESET) || \
    false)

static inline void trace_imx6_ccm_reset(void)
{
    if (trace_event_get_state(TRACE_IMX6_CCM_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 252 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_ccm_reset " "" "\n");
#line 3623 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_CCM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_WRITE) || \
    false)

static inline void trace_imx6_ccm_write(const char *reg, uint32_t value)
{
    if (trace_event_get_state(TRACE_IMX6_CCM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 253 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_ccm_write " "reg[%s] <= 0x%" PRIx32 "\n", reg, value);
#line 3638 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_CCM_ENTRY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CCM_ENTRY) || \
    false)

static inline void trace_ccm_entry(void)
{
    if (trace_event_get_state(TRACE_CCM_ENTRY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 256 "../xemu/hw/misc/trace-events"
            qemu_log("ccm_entry " "" "\n");
#line 3653 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_CCM_FREQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CCM_FREQ) || \
    false)

static inline void trace_ccm_freq(uint32_t freq)
{
    if (trace_event_get_state(TRACE_CCM_FREQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 257 "../xemu/hw/misc/trace-events"
            qemu_log("ccm_freq " "freq = %d" "\n", freq);
#line 3668 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_CCM_CLOCK_FREQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CCM_CLOCK_FREQ) || \
    false)

static inline void trace_ccm_clock_freq(uint32_t clock, uint32_t freq)
{
    if (trace_event_get_state(TRACE_CCM_CLOCK_FREQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 258 "../xemu/hw/misc/trace-events"
            qemu_log("ccm_clock_freq " "(Clock = %d) = %d" "\n", clock, freq);
#line 3683 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_CCM_READ_REG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CCM_READ_REG) || \
    false)

static inline void trace_ccm_read_reg(const char *reg_name, uint32_t value)
{
    if (trace_event_get_state(TRACE_CCM_READ_REG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 259 "../xemu/hw/misc/trace-events"
            qemu_log("ccm_read_reg " "reg[%s] <= 0x%" PRIx32 "\n", reg_name, value);
#line 3698 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_CCM_WRITE_REG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_CCM_WRITE_REG) || \
    false)

static inline void trace_ccm_write_reg(const char *reg_name, uint32_t value)
{
    if (trace_event_get_state(TRACE_CCM_WRITE_REG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 260 "../xemu/hw/misc/trace-events"
            qemu_log("ccm_write_reg " "reg[%s] => 0x%" PRIx32 "\n", reg_name, value);
#line 3713 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_SRC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_SRC_READ) || \
    false)

static inline void trace_imx6_src_read(const char *reg_name, uint32_t value)
{
    if (trace_event_get_state(TRACE_IMX6_SRC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 263 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_src_read " "reg[%s] => 0x%" PRIx32 "\n", reg_name, value);
#line 3728 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_SRC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_SRC_WRITE) || \
    false)

static inline void trace_imx6_src_write(const char *reg_name, uint64_t value)
{
    if (trace_event_get_state(TRACE_IMX6_SRC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 264 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_src_write " "reg[%s] <= 0x%" PRIx64 "\n", reg_name, value);
#line 3743 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_CLEAR_RESET_BIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_CLEAR_RESET_BIT) || \
    false)

static inline void trace_imx6_clear_reset_bit(const char *reg_name, uint32_t value)
{
    if (trace_event_get_state(TRACE_IMX6_CLEAR_RESET_BIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 265 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_clear_reset_bit " "reg[%s] <= 0x%" PRIx32 "\n", reg_name, value);
#line 3758 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX6_SRC_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX6_SRC_RESET) || \
    false)

static inline void trace_imx6_src_reset(void)
{
    if (trace_event_get_state(TRACE_IMX6_SRC_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 266 "../xemu/hw/misc/trace-events"
            qemu_log("imx6_src_reset " "" "\n");
#line 3773 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX7_SRC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX7_SRC_READ) || \
    false)

static inline void trace_imx7_src_read(const char *reg_name, uint32_t value)
{
    if (trace_event_get_state(TRACE_IMX7_SRC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 269 "../xemu/hw/misc/trace-events"
            qemu_log("imx7_src_read " "reg[%s] => 0x%" PRIx32 "\n", reg_name, value);
#line 3788 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IMX7_SRC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX7_SRC_WRITE) || \
    false)

static inline void trace_imx7_src_write(const char *reg_name, uint32_t value)
{
    if (trace_event_get_state(TRACE_IMX7_SRC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 270 "../xemu/hw/misc/trace-events"
            qemu_log("imx7_src_write " "reg[%s] <= 0x%" PRIx32 "\n", reg_name, value);
#line 3803 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IOTKIT_SYSINFO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SYSINFO_READ) || \
    false)

static inline void trace_iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_IOTKIT_SYSINFO_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 273 "../xemu/hw/misc/trace-events"
            qemu_log("iotkit_sysinfo_read " "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3818 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IOTKIT_SYSINFO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SYSINFO_WRITE) || \
    false)

static inline void trace_iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_IOTKIT_SYSINFO_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 274 "../xemu/hw/misc/trace-events"
            qemu_log("iotkit_sysinfo_write " "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3833 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IOTKIT_SYSCTL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SYSCTL_READ) || \
    false)

static inline void trace_iotkit_sysctl_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_IOTKIT_SYSCTL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 277 "../xemu/hw/misc/trace-events"
            qemu_log("iotkit_sysctl_read " "IoTKit SysCtl read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3848 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IOTKIT_SYSCTL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SYSCTL_WRITE) || \
    false)

static inline void trace_iotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_IOTKIT_SYSCTL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 278 "../xemu/hw/misc/trace-events"
            qemu_log("iotkit_sysctl_write " "IoTKit SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3863 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IOTKIT_SYSCTL_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SYSCTL_RESET) || \
    false)

static inline void trace_iotkit_sysctl_reset(void)
{
    if (trace_event_get_state(TRACE_IOTKIT_SYSCTL_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 279 "../xemu/hw/misc/trace-events"
            qemu_log("iotkit_sysctl_reset " "IoTKit SysCtl: reset" "\n");
#line 3878 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ARMSSE_CPU_PWRCTRL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARMSSE_CPU_PWRCTRL_READ) || \
    false)

static inline void trace_armsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ARMSSE_CPU_PWRCTRL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 282 "../xemu/hw/misc/trace-events"
            qemu_log("armsse_cpu_pwrctrl_read " "SSE-300 CPU_PWRCTRL read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3893 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ARMSSE_CPU_PWRCTRL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARMSSE_CPU_PWRCTRL_WRITE) || \
    false)

static inline void trace_armsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ARMSSE_CPU_PWRCTRL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 283 "../xemu/hw/misc/trace-events"
            qemu_log("armsse_cpu_pwrctrl_write " "SSE-300 CPU_PWRCTRL write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3908 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ARMSSE_CPUID_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARMSSE_CPUID_READ) || \
    false)

static inline void trace_armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ARMSSE_CPUID_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 286 "../xemu/hw/misc/trace-events"
            qemu_log("armsse_cpuid_read " "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3923 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ARMSSE_CPUID_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARMSSE_CPUID_WRITE) || \
    false)

static inline void trace_armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ARMSSE_CPUID_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 287 "../xemu/hw/misc/trace-events"
            qemu_log("armsse_cpuid_write " "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3938 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ARMSSE_MHU_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARMSSE_MHU_READ) || \
    false)

static inline void trace_armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ARMSSE_MHU_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 290 "../xemu/hw/misc/trace-events"
            qemu_log("armsse_mhu_read " "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3953 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ARMSSE_MHU_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARMSSE_MHU_WRITE) || \
    false)

static inline void trace_armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_ARMSSE_MHU_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 291 "../xemu/hw/misc/trace-events"
            qemu_log("armsse_mhu_write " "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size);
#line 3968 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_XDMA_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_XDMA_WRITE) || \
    false)

static inline void trace_aspeed_xdma_write(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_XDMA_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 294 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_xdma_write " "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data);
#line 3983 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_I3C_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I3C_READ) || \
    false)

static inline void trace_aspeed_i3c_read(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_I3C_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 297 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_i3c_read " "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data);
#line 3998 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_I3C_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I3C_WRITE) || \
    false)

static inline void trace_aspeed_i3c_write(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_I3C_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 298 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_i3c_write " "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data);
#line 4013 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_I3C_DEVICE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I3C_DEVICE_READ) || \
    false)

static inline void trace_aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_I3C_DEVICE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 299 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_i3c_device_read " "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", deviceid, offset, data);
#line 4028 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_I3C_DEVICE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I3C_DEVICE_WRITE) || \
    false)

static inline void trace_aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_I3C_DEVICE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 300 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_i3c_device_write " "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", deviceid, offset, data);
#line 4043 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_SDMC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SDMC_WRITE) || \
    false)

static inline void trace_aspeed_sdmc_write(uint64_t reg, uint64_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_SDMC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 303 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_sdmc_write " "reg @0x%" PRIx64 " data: 0x%" PRIx64 "\n", reg, data);
#line 4058 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_SDMC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SDMC_READ) || \
    false)

static inline void trace_aspeed_sdmc_read(uint64_t reg, uint64_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_SDMC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 304 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_sdmc_read " "reg @0x%" PRIx64 " data: 0x%" PRIx64 "\n", reg, data);
#line 4073 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_PECI_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_PECI_READ) || \
    false)

static inline void trace_aspeed_peci_read(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_PECI_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 307 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_peci_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data);
#line 4088 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_PECI_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_PECI_WRITE) || \
    false)

static inline void trace_aspeed_peci_write(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_PECI_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 308 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_peci_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data);
#line 4103 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_PECI_RAISE_INTERRUPT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_PECI_RAISE_INTERRUPT) || \
    false)

static inline void trace_aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status)
{
    if (trace_event_get_state(TRACE_ASPEED_PECI_RAISE_INTERRUPT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 309 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_peci_raise_interrupt " "ctrl 0x%" PRIx32 " status 0x%" PRIx32 "\n", ctrl, status);
#line 4118 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_HACE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_HACE_READ) || \
    false)

static inline void trace_aspeed_hace_read(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_HACE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 312 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_hace_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data);
#line 4133 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_HACE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_HACE_WRITE) || \
    false)

static inline void trace_aspeed_hace_write(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_HACE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 313 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_hace_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data);
#line 4148 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_HACE_HASH_SG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_HACE_HASH_SG) || \
    false)

static inline void trace_aspeed_hace_hash_sg(int index, uint64_t list_addr, uint64_t buf_addr, uint32_t len)
{
    if (trace_event_get_state(TRACE_ASPEED_HACE_HASH_SG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 314 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_hace_hash_sg " "%d: list_addr 0x%" PRIx64 " buf_addr 0x%" PRIx64 " len 0x%" PRIx32 "\n", index, list_addr, buf_addr, len);
#line 4163 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_HACE_HASH_ADDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_HACE_HASH_ADDR) || \
    false)

static inline void trace_aspeed_hace_hash_addr(const char *s, uint64_t addr)
{
    if (trace_event_get_state(TRACE_ASPEED_HACE_HASH_ADDR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 315 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_hace_hash_addr " "%s: 0x%" PRIx64 "\n", s, addr);
#line 4178 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_HACE_HASH_EXECUTE_ACC_MODE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_HACE_HASH_EXECUTE_ACC_MODE) || \
    false)

static inline void trace_aspeed_hace_hash_execute_acc_mode(bool final_request)
{
    if (trace_event_get_state(TRACE_ASPEED_HACE_HASH_EXECUTE_ACC_MODE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 316 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_hace_hash_execute_acc_mode " "final request: %d" "\n", final_request);
#line 4193 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_HACE_HEXDUMP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_HACE_HEXDUMP) || \
    false)

static inline void trace_aspeed_hace_hexdump(const char *desc, uint32_t offset, char *s)
{
    if (trace_event_get_state(TRACE_ASPEED_HACE_HEXDUMP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 317 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_hace_hexdump " "%s: 0x%08x: %s" "\n", desc, offset, s);
#line 4208 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_BCM2835_MBOX_PROPERTY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_MBOX_PROPERTY) || \
    false)

static inline void trace_bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen)
{
    if (trace_event_get_state(TRACE_BCM2835_MBOX_PROPERTY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 320 "../xemu/hw/misc/trace-events"
            qemu_log("bcm2835_mbox_property " "mbox property tag:0x%08x in_sz:%u out_sz:%zu" "\n", tag, bufsize, resplen);
#line 4223 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_BCM2835_MBOX_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_MBOX_WRITE) || \
    false)

static inline void trace_bcm2835_mbox_write(unsigned int size, uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_BCM2835_MBOX_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 323 "../xemu/hw/misc/trace-events"
            qemu_log("bcm2835_mbox_write " "mbox write sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 "\n", size, addr, value);
#line 4238 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_BCM2835_MBOX_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_MBOX_READ) || \
    false)

static inline void trace_bcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_BCM2835_MBOX_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 324 "../xemu/hw/misc/trace-events"
            qemu_log("bcm2835_mbox_read " "mbox read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 "\n", size, addr, value);
#line 4253 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_BCM2835_MBOX_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_MBOX_IRQ) || \
    false)

static inline void trace_bcm2835_mbox_irq(unsigned level)
{
    if (trace_event_get_state(TRACE_BCM2835_MBOX_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 325 "../xemu/hw/misc/trace-events"
            qemu_log("bcm2835_mbox_irq " "mbox irq:ARM level:%u" "\n", level);
#line 4268 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_UPDATE_DATA_OUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_UPDATE_DATA_OUT) || \
    false)

static inline void trace_via1_rtc_update_data_out(int count, int value)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_UPDATE_DATA_OUT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 328 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_update_data_out " "count=%d value=0x%02x" "\n", count, value);
#line 4283 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_UPDATE_DATA_IN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_UPDATE_DATA_IN) || \
    false)

static inline void trace_via1_rtc_update_data_in(int count, int value)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_UPDATE_DATA_IN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 329 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_update_data_in " "count=%d value=0x%02x" "\n", count, value);
#line 4298 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_INTERNAL_STATUS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_INTERNAL_STATUS) || \
    false)

static inline void trace_via1_rtc_internal_status(int cmd, int alt, int value)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_INTERNAL_STATUS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 330 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_internal_status " "cmd=0x%02x alt=0x%02x value=0x%02x" "\n", cmd, alt, value);
#line 4313 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_INTERNAL_CMD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_INTERNAL_CMD) || \
    false)

static inline void trace_via1_rtc_internal_cmd(int cmd)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_INTERNAL_CMD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 331 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_internal_cmd " "cmd=0x%02x" "\n", cmd);
#line 4328 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_CMD_INVALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_INVALID) || \
    false)

static inline void trace_via1_rtc_cmd_invalid(int value)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_CMD_INVALID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 332 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_cmd_invalid " "value=0x%02x" "\n", value);
#line 4343 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_INTERNAL_TIME_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_INTERNAL_TIME) || \
    false)

static inline void trace_via1_rtc_internal_time(uint32_t time)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_INTERNAL_TIME)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 333 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_internal_time " "time=0x%08x" "\n", time);
#line 4358 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_INTERNAL_SET_CMD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_INTERNAL_SET_CMD) || \
    false)

static inline void trace_via1_rtc_internal_set_cmd(int cmd)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_INTERNAL_SET_CMD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 334 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_internal_set_cmd " "cmd=0x%02x" "\n", cmd);
#line 4373 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD) || \
    false)

static inline void trace_via1_rtc_internal_ignore_cmd(int cmd)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 335 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_internal_ignore_cmd " "cmd=0x%02x" "\n", cmd);
#line 4388 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_INTERNAL_SET_ALT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_INTERNAL_SET_ALT) || \
    false)

static inline void trace_via1_rtc_internal_set_alt(int alt, int sector, int offset)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_INTERNAL_SET_ALT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 336 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_internal_set_alt " "alt=0x%02x sector=%u offset=%u" "\n", alt, sector, offset);
#line 4403 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_CMD_SECONDS_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_SECONDS_READ) || \
    false)

static inline void trace_via1_rtc_cmd_seconds_read(int reg, int value)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_CMD_SECONDS_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 337 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_cmd_seconds_read " "reg=%d value=0x%02x" "\n", reg, value);
#line 4418 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_CMD_SECONDS_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_SECONDS_WRITE) || \
    false)

static inline void trace_via1_rtc_cmd_seconds_write(int reg, int value)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_CMD_SECONDS_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 338 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_cmd_seconds_write " "reg=%d value=0x%02x" "\n", reg, value);
#line 4433 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_CMD_TEST_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_TEST_WRITE) || \
    false)

static inline void trace_via1_rtc_cmd_test_write(int value)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_CMD_TEST_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 339 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_cmd_test_write " "value=0x%02x" "\n", value);
#line 4448 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_WPROTECT_WRITE) || \
    false)

static inline void trace_via1_rtc_cmd_wprotect_write(int value)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_CMD_WPROTECT_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 340 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_cmd_wprotect_write " "value=0x%02x" "\n", value);
#line 4463 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_CMD_PRAM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_PRAM_READ) || \
    false)

static inline void trace_via1_rtc_cmd_pram_read(int addr, int value)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_CMD_PRAM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 341 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_cmd_pram_read " "addr=%u value=0x%02x" "\n", addr, value);
#line 4478 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_CMD_PRAM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_PRAM_WRITE) || \
    false)

static inline void trace_via1_rtc_cmd_pram_write(int addr, int value)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_CMD_PRAM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 342 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_cmd_pram_write " "addr=%u value=0x%02x" "\n", addr, value);
#line 4493 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_PRAM_SECT_READ) || \
    false)

static inline void trace_via1_rtc_cmd_pram_sect_read(int sector, int offset, int addr, int value)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_CMD_PRAM_SECT_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 343 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_cmd_pram_sect_read " "sector=%u offset=%u addr=0x%x value=0x%02x" "\n", sector, offset, addr, value);
#line 4508 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE) || \
    false)

static inline void trace_via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value)
{
    if (trace_event_get_state(TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 344 "../xemu/hw/misc/trace-events"
            qemu_log("via1_rtc_cmd_pram_sect_write " "sector=%u offset=%u addr=0x%x value=0x%02x" "\n", sector, offset, addr, value);
#line 4523 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_ADB_SEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_ADB_SEND) || \
    false)

static inline void trace_via1_adb_send(const char *state, uint8_t data, const char *vadbint)
{
    if (trace_event_get_state(TRACE_VIA1_ADB_SEND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 345 "../xemu/hw/misc/trace-events"
            qemu_log("via1_adb_send " "state %s data=0x%02x vADBInt=%s" "\n", state, data, vadbint);
#line 4538 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_ADB_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_ADB_RECEIVE) || \
    false)

static inline void trace_via1_adb_receive(const char *state, uint8_t data, const char *vadbint, int status, int index, int size)
{
    if (trace_event_get_state(TRACE_VIA1_ADB_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 346 "../xemu/hw/misc/trace-events"
            qemu_log("via1_adb_receive " "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" "\n", state, data, vadbint, status, index, size);
#line 4553 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_ADB_POLL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_ADB_POLL) || \
    false)

static inline void trace_via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size)
{
    if (trace_event_get_state(TRACE_VIA1_ADB_POLL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 347 "../xemu/hw/misc/trace-events"
            qemu_log("via1_adb_poll " "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" "\n", data, vadbint, status, index, size);
#line 4568 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_ADB_NETBSD_ENUM_HACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_ADB_NETBSD_ENUM_HACK) || \
    false)

static inline void trace_via1_adb_netbsd_enum_hack(void)
{
    if (trace_event_get_state(TRACE_VIA1_ADB_NETBSD_ENUM_HACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 348 "../xemu/hw/misc/trace-events"
            qemu_log("via1_adb_netbsd_enum_hack " "using NetBSD enum hack" "\n");
#line 4583 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_AUXMODE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_AUXMODE) || \
    false)

static inline void trace_via1_auxmode(int mode)
{
    if (trace_event_get_state(TRACE_VIA1_AUXMODE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 349 "../xemu/hw/misc/trace-events"
            qemu_log("via1_auxmode " "setting auxmode to %d" "\n", mode);
#line 4598 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIA1_TIMER_HACK_STATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIA1_TIMER_HACK_STATE) || \
    false)

static inline void trace_via1_timer_hack_state(int state)
{
    if (trace_event_get_state(TRACE_VIA1_TIMER_HACK_STATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 350 "../xemu/hw/misc/trace-events"
            qemu_log("via1_timer_hack_state " "setting timer_hack_state to %d" "\n", state);
#line 4613 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_GRLIB_AHB_PNP_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_AHB_PNP_READ) || \
    false)

static inline void trace_grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value)
{
    if (trace_event_get_state(TRACE_GRLIB_AHB_PNP_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 353 "../xemu/hw/misc/trace-events"
            qemu_log("grlib_ahb_pnp_read " "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" "\n", addr, size, value);
#line 4628 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_GRLIB_APB_PNP_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRLIB_APB_PNP_READ) || \
    false)

static inline void trace_grlib_apb_pnp_read(uint64_t addr, unsigned size, uint32_t value)
{
    if (trace_event_get_state(TRACE_GRLIB_APB_PNP_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 354 "../xemu/hw/misc/trace-events"
            qemu_log("grlib_apb_pnp_read " "APB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" "\n", addr, size, value);
#line 4643 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_LED_SET_INTENSITY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LED_SET_INTENSITY) || \
    false)

static inline void trace_led_set_intensity(const char *color, const char *desc, uint8_t intensity_percent)
{
    if (trace_event_get_state(TRACE_LED_SET_INTENSITY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 357 "../xemu/hw/misc/trace-events"
            qemu_log("led_set_intensity " "LED desc:'%s' color:%s intensity: %u%%" "\n", color, desc, intensity_percent);
#line 4658 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_LED_CHANGE_INTENSITY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LED_CHANGE_INTENSITY) || \
    false)

static inline void trace_led_change_intensity(const char *color, const char *desc, uint8_t old_intensity_percent, uint8_t new_intensity_percent)
{
    if (trace_event_get_state(TRACE_LED_CHANGE_INTENSITY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 358 "../xemu/hw/misc/trace-events"
            qemu_log("led_change_intensity " "LED desc:'%s' color:%s intensity %u%% -> %u%%" "\n", color, desc, old_intensity_percent, new_intensity_percent);
#line 4673 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_BCM2835_CPRMAN_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_CPRMAN_READ) || \
    false)

static inline void trace_bcm2835_cprman_read(uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_BCM2835_CPRMAN_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 361 "../xemu/hw/misc/trace-events"
            qemu_log("bcm2835_cprman_read " "offset:0x%" PRIx64 " value:0x%" PRIx64 "\n", offset, value);
#line 4688 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_BCM2835_CPRMAN_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_CPRMAN_WRITE) || \
    false)

static inline void trace_bcm2835_cprman_write(uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_BCM2835_CPRMAN_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 362 "../xemu/hw/misc/trace-events"
            qemu_log("bcm2835_cprman_write " "offset:0x%" PRIx64 " value:0x%" PRIx64 "\n", offset, value);
#line 4703 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC) || \
    false)

static inline void trace_bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 363 "../xemu/hw/misc/trace-events"
            qemu_log("bcm2835_cprman_write_invalid_magic " "offset:0x%" PRIx64 " value:0x%" PRIx64 "\n", offset, value);
#line 4718 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIRT_CTRL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRT_CTRL_READ) || \
    false)

static inline void trace_virt_ctrl_read(void *dev, unsigned int addr, unsigned int size, uint64_t value)
{
    if (trace_event_get_state(TRACE_VIRT_CTRL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 366 "../xemu/hw/misc/trace-events"
            qemu_log("virt_ctrl_read " "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", dev, addr, size, value);
#line 4733 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIRT_CTRL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRT_CTRL_WRITE) || \
    false)

static inline void trace_virt_ctrl_write(void *dev, unsigned int addr, unsigned int size, uint64_t value)
{
    if (trace_event_get_state(TRACE_VIRT_CTRL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 367 "../xemu/hw/misc/trace-events"
            qemu_log("virt_ctrl_write " "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", dev, addr, size, value);
#line 4748 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIRT_CTRL_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRT_CTRL_RESET) || \
    false)

static inline void trace_virt_ctrl_reset(void *dev)
{
    if (trace_event_get_state(TRACE_VIRT_CTRL_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 368 "../xemu/hw/misc/trace-events"
            qemu_log("virt_ctrl_reset " "ctrl: %p" "\n", dev);
#line 4763 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIRT_CTRL_REALIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRT_CTRL_REALIZE) || \
    false)

static inline void trace_virt_ctrl_realize(void *dev)
{
    if (trace_event_get_state(TRACE_VIRT_CTRL_REALIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 369 "../xemu/hw/misc/trace-events"
            qemu_log("virt_ctrl_realize " "ctrl: %p" "\n", dev);
#line 4778 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_VIRT_CTRL_INSTANCE_INIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRT_CTRL_INSTANCE_INIT) || \
    false)

static inline void trace_virt_ctrl_instance_init(void *dev)
{
    if (trace_event_get_state(TRACE_VIRT_CTRL_INSTANCE_INIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 370 "../xemu/hw/misc/trace-events"
            qemu_log("virt_ctrl_instance_init " "ctrl: %p" "\n", dev);
#line 4793 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_LASI_CHIP_MEM_VALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LASI_CHIP_MEM_VALID) || \
    false)

static inline void trace_lasi_chip_mem_valid(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_LASI_CHIP_MEM_VALID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 373 "../xemu/hw/misc/trace-events"
            qemu_log("lasi_chip_mem_valid " "access to addr 0x%"PRIx64" is %d" "\n", addr, val);
#line 4808 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_LASI_CHIP_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LASI_CHIP_READ) || \
    false)

static inline void trace_lasi_chip_read(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_LASI_CHIP_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 374 "../xemu/hw/misc/trace-events"
            qemu_log("lasi_chip_read " "addr 0x%"PRIx64" val 0x%08x" "\n", addr, val);
#line 4823 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_LASI_CHIP_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LASI_CHIP_WRITE) || \
    false)

static inline void trace_lasi_chip_write(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_LASI_CHIP_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 375 "../xemu/hw/misc/trace-events"
            qemu_log("lasi_chip_write " "addr 0x%"PRIx64" val 0x%08x" "\n", addr, val);
#line 4838 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_DJMEMC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DJMEMC_READ) || \
    false)

static inline void trace_djmemc_read(int reg, uint64_t value, unsigned int size)
{
    if (trace_event_get_state(TRACE_DJMEMC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 378 "../xemu/hw/misc/trace-events"
            qemu_log("djmemc_read " "reg=0x%x value=0x%"PRIx64" size=%u" "\n", reg, value, size);
#line 4853 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_DJMEMC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DJMEMC_WRITE) || \
    false)

static inline void trace_djmemc_write(int reg, uint64_t value, unsigned int size)
{
    if (trace_event_get_state(TRACE_DJMEMC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 379 "../xemu/hw/misc/trace-events"
            qemu_log("djmemc_write " "reg=0x%x value=0x%"PRIx64" size=%u" "\n", reg, value, size);
#line 4868 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IOSB_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOSB_READ) || \
    false)

static inline void trace_iosb_read(int reg, uint64_t value, unsigned int size)
{
    if (trace_event_get_state(TRACE_IOSB_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 382 "../xemu/hw/misc/trace-events"
            qemu_log("iosb_read " "reg=0x%x value=0x%"PRIx64" size=%u" "\n", reg, value, size);
#line 4883 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IOSB_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOSB_WRITE) || \
    false)

static inline void trace_iosb_write(int reg, uint64_t value, unsigned int size)
{
    if (trace_event_get_state(TRACE_IOSB_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 383 "../xemu/hw/misc/trace-events"
            qemu_log("iosb_write " "reg=0x%x value=0x%"PRIx64" size=%u" "\n", reg, value, size);
#line 4898 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_SLI_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SLI_WRITE) || \
    false)

static inline void trace_aspeed_sli_write(uint64_t offset, unsigned int size, uint32_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_SLI_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 386 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_sli_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data);
#line 4913 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_SLI_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SLI_READ) || \
    false)

static inline void trace_aspeed_sli_read(uint64_t offset, unsigned int size, uint32_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_SLI_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 387 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_sli_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data);
#line 4928 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_SLIIO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SLIIO_WRITE) || \
    false)

static inline void trace_aspeed_sliio_write(uint64_t offset, unsigned int size, uint32_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_SLIIO_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 388 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_sliio_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data);
#line 4943 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_ASPEED_SLIIO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SLIIO_READ) || \
    false)

static inline void trace_aspeed_sliio_read(uint64_t offset, unsigned int size, uint32_t data)
{
    if (trace_event_get_state(TRACE_ASPEED_SLIIO_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 389 "../xemu/hw/misc/trace-events"
            qemu_log("aspeed_sliio_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data);
#line 4958 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_IRQ_HANDLER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_IRQ_HANDLER) || \
    false)

static inline void trace_ivshmem_flat_irq_handler(uint16_t vector_id)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_IRQ_HANDLER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 392 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_irq_handler " "Caught interrupt request: vector %d" "\n", vector_id);
#line 4973 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_NEW_PEER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_NEW_PEER) || \
    false)

static inline void trace_ivshmem_flat_new_peer(uint16_t peer_id)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_NEW_PEER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 393 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_new_peer " "New peer ID: %d" "\n", peer_id);
#line 4988 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_ADD_VECTOR_FAILURE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_ADD_VECTOR_FAILURE) || \
    false)

static inline void trace_ivshmem_flat_add_vector_failure(uint16_t vector_id, uint32_t vector_fd, uint16_t peer_id)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_ADD_VECTOR_FAILURE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 394 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_add_vector_failure " "Failed to add vector %u (fd = %u) to peer ID %u, maximum number of vectors reached" "\n", vector_id, vector_fd, peer_id);
#line 5003 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_ADD_VECTOR_SUCCESS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_ADD_VECTOR_SUCCESS) || \
    false)

static inline void trace_ivshmem_flat_add_vector_success(uint16_t vector_id, uint32_t vector_fd, uint16_t peer_id)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_ADD_VECTOR_SUCCESS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 395 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_add_vector_success " "Successful addition of vector %u (fd = %u) to peer ID %u" "\n", vector_id, vector_fd, peer_id);
#line 5018 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_IRQ_RESOLVED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_IRQ_RESOLVED) || \
    false)

static inline void trace_ivshmem_flat_irq_resolved(const char *irq_qompath)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_IRQ_RESOLVED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 396 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_irq_resolved " "IRQ QOM path '%s' correctly resolved" "\n", irq_qompath);
#line 5033 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_PROTO_VER_OWN_ID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_PROTO_VER_OWN_ID) || \
    false)

static inline void trace_ivshmem_flat_proto_ver_own_id(uint64_t proto_ver, uint16_t peer_id)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_PROTO_VER_OWN_ID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 397 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_proto_ver_own_id " "Protocol Version = 0x%"PRIx64", Own Peer ID = %u" "\n", proto_ver, peer_id);
#line 5048 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_SHMEM_SIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_SHMEM_SIZE) || \
    false)

static inline void trace_ivshmem_flat_shmem_size(int fd, uint64_t size)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_SHMEM_SIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 398 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_shmem_size " "Shmem fd (%d) total size is %"PRIu64" byte(s)" "\n", fd, size);
#line 5063 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_SHMEM_MAP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_SHMEM_MAP) || \
    false)

static inline void trace_ivshmem_flat_shmem_map(uint64_t addr)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_SHMEM_MAP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 399 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_shmem_map " "Mapping shmem @ 0x%"PRIx64 "\n", addr);
#line 5078 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_MMIO_MAP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_MMIO_MAP) || \
    false)

static inline void trace_ivshmem_flat_mmio_map(uint64_t addr)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_MMIO_MAP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 400 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_mmio_map " "Mapping MMRs @ 0x%"PRIx64 "\n", addr);
#line 5093 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_READ_MMR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_READ_MMR) || \
    false)

static inline void trace_ivshmem_flat_read_mmr(uint64_t addr_offset)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_READ_MMR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 401 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_read_mmr " "Read access at offset %"PRIu64 "\n", addr_offset);
#line 5108 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_READ_MMR_DOORBELL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_READ_MMR_DOORBELL) || \
    false)

static inline void trace_ivshmem_flat_read_mmr_doorbell(void)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_READ_MMR_DOORBELL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 402 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_read_mmr_doorbell " "DOORBELL register is write-only!" "\n");
#line 5123 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_READ_WRITE_MMR_INVALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_READ_WRITE_MMR_INVALID) || \
    false)

static inline void trace_ivshmem_flat_read_write_mmr_invalid(uint64_t addr_offset)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_READ_WRITE_MMR_INVALID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 403 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_read_write_mmr_invalid " "No ivshmem register mapped at offset %"PRIu64 "\n", addr_offset);
#line 5138 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_INTERRUPT_INVALID_PEER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_INTERRUPT_INVALID_PEER) || \
    false)

static inline void trace_ivshmem_flat_interrupt_invalid_peer(uint16_t peer_id)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_INTERRUPT_INVALID_PEER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 404 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_interrupt_invalid_peer " "Can't interrupt non-existing peer %u" "\n", peer_id);
#line 5153 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_WRITE_MMR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_WRITE_MMR) || \
    false)

static inline void trace_ivshmem_flat_write_mmr(uint64_t addr_offset)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_WRITE_MMR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 405 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_write_mmr " "Write access at offset %"PRIu64 "\n", addr_offset);
#line 5168 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_IVSHMEM_FLAT_INTERRUPT_PEER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IVSHMEM_FLAT_INTERRUPT_PEER) || \
    false)

static inline void trace_ivshmem_flat_interrupt_peer(uint16_t peer_id, uint16_t vector_id)
{
    if (trace_event_get_state(TRACE_IVSHMEM_FLAT_INTERRUPT_PEER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 406 "../xemu/hw/misc/trace-events"
            qemu_log("ivshmem_flat_interrupt_peer " "Interrupting peer ID %u, vector %u..." "\n", peer_id, vector_id);
#line 5183 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_I2C_ECHO_EVENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_ECHO_EVENT) || \
    false)

static inline void trace_i2c_echo_event(const char *id, const char *event)
{
    if (trace_event_get_state(TRACE_I2C_ECHO_EVENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 409 "../xemu/hw/misc/trace-events"
            qemu_log("i2c_echo_event " "%s: %s" "\n", id, event);
#line 5198 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_I2C_ECHO_RECV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_ECHO_RECV) || \
    false)

static inline void trace_i2c_echo_recv(const char *id, uint8_t data)
{
    if (trace_event_get_state(TRACE_I2C_ECHO_RECV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 410 "../xemu/hw/misc/trace-events"
            qemu_log("i2c_echo_recv " "%s: recv 0x%02" PRIx8 "\n", id, data);
#line 5213 "trace/trace-hw_misc.h"
        }
    }
}

#define TRACE_I2C_ECHO_SEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_ECHO_SEND) || \
    false)

static inline void trace_i2c_echo_send(const char *id, uint8_t data)
{
    if (trace_event_get_state(TRACE_I2C_ECHO_SEND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 411 "../xemu/hw/misc/trace-events"
            qemu_log("i2c_echo_send " "%s: send 0x%02" PRIx8 "\n", id, data);
#line 5228 "trace/trace-hw_misc.h"
        }
    }
}
#endif /* TRACE_HW_MISC_GENERATED_TRACERS_H */
