/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_acpi.h"

uint16_t _TRACE_MHP_ACPI_INVALID_SLOT_SELECTED_DSTATE;
uint16_t _TRACE_MHP_ACPI_EJECTING_INVALID_SLOT_DSTATE;
uint16_t _TRACE_MHP_ACPI_READ_ADDR_LO_DSTATE;
uint16_t _TRACE_MHP_ACPI_READ_ADDR_HI_DSTATE;
uint16_t _TRACE_MHP_ACPI_READ_SIZE_LO_DSTATE;
uint16_t _TRACE_MHP_ACPI_READ_SIZE_HI_DSTATE;
uint16_t _TRACE_MHP_ACPI_READ_PXM_DSTATE;
uint16_t _TRACE_MHP_ACPI_READ_FLAGS_DSTATE;
uint16_t _TRACE_MHP_ACPI_WRITE_SLOT_DSTATE;
uint16_t _TRACE_MHP_ACPI_WRITE_OST_EV_DSTATE;
uint16_t _TRACE_MHP_ACPI_WRITE_OST_STATUS_DSTATE;
uint16_t _TRACE_MHP_ACPI_CLEAR_INSERT_EVT_DSTATE;
uint16_t _TRACE_MHP_ACPI_CLEAR_REMOVE_EVT_DSTATE;
uint16_t _TRACE_MHP_ACPI_PC_DIMM_DELETED_DSTATE;
uint16_t _TRACE_MHP_ACPI_PC_DIMM_DELETE_FAILED_DSTATE;
uint16_t _TRACE_ACPI_GPE_EN_IOPORT_READB_DSTATE;
uint16_t _TRACE_ACPI_GPE_EN_IOPORT_WRITEB_DSTATE;
uint16_t _TRACE_ACPI_GPE_STS_IOPORT_READB_DSTATE;
uint16_t _TRACE_ACPI_GPE_STS_IOPORT_WRITEB_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_INVALID_IDX_SELECTED_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_READ_FLAGS_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_WRITE_IDX_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_WRITE_CMD_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_READ_CMD_DATA_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_READ_CMD_DATA2_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_CPU_HAS_EVENTS_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_CLEAR_INSERTING_EVT_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_CLEAR_REMOVE_EVT_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_EJECTING_INVALID_CPU_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_EJECTING_CPU_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_FW_REMOVE_INVALID_CPU_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_FW_REMOVE_CPU_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_WRITE_OST_EV_DSTATE;
uint16_t _TRACE_CPUHP_ACPI_WRITE_OST_STATUS_DSTATE;
uint16_t _TRACE_ACPI_PCI_EJECT_SLOT_DSTATE;
uint16_t _TRACE_ACPI_PCI_UNPLUG_DSTATE;
uint16_t _TRACE_ACPI_PCI_UNPLUG_REQUEST_DSTATE;
uint16_t _TRACE_ACPI_PCI_UP_READ_DSTATE;
uint16_t _TRACE_ACPI_PCI_DOWN_READ_DSTATE;
uint16_t _TRACE_ACPI_PCI_FEATURES_READ_DSTATE;
uint16_t _TRACE_ACPI_PCI_ACPI_INDEX_READ_DSTATE;
uint16_t _TRACE_ACPI_PCI_ACPI_INDEX_WRITE_DSTATE;
uint16_t _TRACE_ACPI_PCI_RMV_READ_DSTATE;
uint16_t _TRACE_ACPI_PCI_SEL_READ_DSTATE;
uint16_t _TRACE_ACPI_PCI_EJ_WRITE_DSTATE;
uint16_t _TRACE_ACPI_PCI_SEL_WRITE_DSTATE;
uint16_t _TRACE_TCO_TIMER_RELOAD_DSTATE;
uint16_t _TRACE_TCO_TIMER_EXPIRED_DSTATE;
uint16_t _TRACE_TCO_IO_WRITE_DSTATE;
uint16_t _TRACE_TCO_IO_READ_DSTATE;
uint16_t _TRACE_ACPI_ERST_REG_WRITE_DSTATE;
uint16_t _TRACE_ACPI_ERST_REG_READ_DSTATE;
uint16_t _TRACE_ACPI_ERST_MEM_WRITE_DSTATE;
uint16_t _TRACE_ACPI_ERST_MEM_READ_DSTATE;
uint16_t _TRACE_ACPI_ERST_PCI_BAR_0_DSTATE;
uint16_t _TRACE_ACPI_ERST_PCI_BAR_1_DSTATE;
uint16_t _TRACE_ACPI_ERST_REALIZEFN_IN_DSTATE;
uint16_t _TRACE_ACPI_ERST_REALIZEFN_OUT_DSTATE;
uint16_t _TRACE_ACPI_ERST_RESET_IN_DSTATE;
uint16_t _TRACE_ACPI_ERST_RESET_OUT_DSTATE;
uint16_t _TRACE_ACPI_ERST_POST_LOAD_DSTATE;
uint16_t _TRACE_ACPI_ERST_CLASS_INIT_IN_DSTATE;
uint16_t _TRACE_ACPI_ERST_CLASS_INIT_OUT_DSTATE;
uint16_t _TRACE_ACPI_NVDIMM_READ_FIT_DSTATE;
uint16_t _TRACE_ACPI_NVDIMM_LABEL_INFO_DSTATE;
uint16_t _TRACE_ACPI_NVDIMM_LABEL_OVERFLOW_DSTATE;
uint16_t _TRACE_ACPI_NVDIMM_LABEL_OVERSIZE_DSTATE;
uint16_t _TRACE_ACPI_NVDIMM_LABEL_XFER_EXCEED_DSTATE;
uint16_t _TRACE_ACPI_NVDIMM_READ_LABEL_DSTATE;
uint16_t _TRACE_ACPI_NVDIMM_WRITE_LABEL_DSTATE;
uint16_t _TRACE_ACPI_NVDIMM_READ_IO_PORT_DSTATE;
uint16_t _TRACE_ACPI_NVDIMM_DSM_MEM_ADDR_DSTATE;
uint16_t _TRACE_ACPI_NVDIMM_DSM_INFO_DSTATE;
uint16_t _TRACE_ACPI_NVDIMM_INVALID_REVISION_DSTATE;
TraceEvent _TRACE_MHP_ACPI_INVALID_SLOT_SELECTED_EVENT = {
    .id = 0,
    .name = "mhp_acpi_invalid_slot_selected",
    .sstate = TRACE_MHP_ACPI_INVALID_SLOT_SELECTED_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_INVALID_SLOT_SELECTED_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_EJECTING_INVALID_SLOT_EVENT = {
    .id = 0,
    .name = "mhp_acpi_ejecting_invalid_slot",
    .sstate = TRACE_MHP_ACPI_EJECTING_INVALID_SLOT_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_EJECTING_INVALID_SLOT_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_READ_ADDR_LO_EVENT = {
    .id = 0,
    .name = "mhp_acpi_read_addr_lo",
    .sstate = TRACE_MHP_ACPI_READ_ADDR_LO_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_READ_ADDR_LO_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_READ_ADDR_HI_EVENT = {
    .id = 0,
    .name = "mhp_acpi_read_addr_hi",
    .sstate = TRACE_MHP_ACPI_READ_ADDR_HI_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_READ_ADDR_HI_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_READ_SIZE_LO_EVENT = {
    .id = 0,
    .name = "mhp_acpi_read_size_lo",
    .sstate = TRACE_MHP_ACPI_READ_SIZE_LO_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_READ_SIZE_LO_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_READ_SIZE_HI_EVENT = {
    .id = 0,
    .name = "mhp_acpi_read_size_hi",
    .sstate = TRACE_MHP_ACPI_READ_SIZE_HI_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_READ_SIZE_HI_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_READ_PXM_EVENT = {
    .id = 0,
    .name = "mhp_acpi_read_pxm",
    .sstate = TRACE_MHP_ACPI_READ_PXM_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_READ_PXM_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_READ_FLAGS_EVENT = {
    .id = 0,
    .name = "mhp_acpi_read_flags",
    .sstate = TRACE_MHP_ACPI_READ_FLAGS_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_READ_FLAGS_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_WRITE_SLOT_EVENT = {
    .id = 0,
    .name = "mhp_acpi_write_slot",
    .sstate = TRACE_MHP_ACPI_WRITE_SLOT_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_WRITE_SLOT_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_WRITE_OST_EV_EVENT = {
    .id = 0,
    .name = "mhp_acpi_write_ost_ev",
    .sstate = TRACE_MHP_ACPI_WRITE_OST_EV_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_WRITE_OST_EV_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_WRITE_OST_STATUS_EVENT = {
    .id = 0,
    .name = "mhp_acpi_write_ost_status",
    .sstate = TRACE_MHP_ACPI_WRITE_OST_STATUS_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_WRITE_OST_STATUS_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_CLEAR_INSERT_EVT_EVENT = {
    .id = 0,
    .name = "mhp_acpi_clear_insert_evt",
    .sstate = TRACE_MHP_ACPI_CLEAR_INSERT_EVT_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_CLEAR_INSERT_EVT_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_CLEAR_REMOVE_EVT_EVENT = {
    .id = 0,
    .name = "mhp_acpi_clear_remove_evt",
    .sstate = TRACE_MHP_ACPI_CLEAR_REMOVE_EVT_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_CLEAR_REMOVE_EVT_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_PC_DIMM_DELETED_EVENT = {
    .id = 0,
    .name = "mhp_acpi_pc_dimm_deleted",
    .sstate = TRACE_MHP_ACPI_PC_DIMM_DELETED_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_PC_DIMM_DELETED_DSTATE
};
TraceEvent _TRACE_MHP_ACPI_PC_DIMM_DELETE_FAILED_EVENT = {
    .id = 0,
    .name = "mhp_acpi_pc_dimm_delete_failed",
    .sstate = TRACE_MHP_ACPI_PC_DIMM_DELETE_FAILED_ENABLED,
    .dstate = &_TRACE_MHP_ACPI_PC_DIMM_DELETE_FAILED_DSTATE
};
TraceEvent _TRACE_ACPI_GPE_EN_IOPORT_READB_EVENT = {
    .id = 0,
    .name = "acpi_gpe_en_ioport_readb",
    .sstate = TRACE_ACPI_GPE_EN_IOPORT_READB_ENABLED,
    .dstate = &_TRACE_ACPI_GPE_EN_IOPORT_READB_DSTATE
};
TraceEvent _TRACE_ACPI_GPE_EN_IOPORT_WRITEB_EVENT = {
    .id = 0,
    .name = "acpi_gpe_en_ioport_writeb",
    .sstate = TRACE_ACPI_GPE_EN_IOPORT_WRITEB_ENABLED,
    .dstate = &_TRACE_ACPI_GPE_EN_IOPORT_WRITEB_DSTATE
};
TraceEvent _TRACE_ACPI_GPE_STS_IOPORT_READB_EVENT = {
    .id = 0,
    .name = "acpi_gpe_sts_ioport_readb",
    .sstate = TRACE_ACPI_GPE_STS_IOPORT_READB_ENABLED,
    .dstate = &_TRACE_ACPI_GPE_STS_IOPORT_READB_DSTATE
};
TraceEvent _TRACE_ACPI_GPE_STS_IOPORT_WRITEB_EVENT = {
    .id = 0,
    .name = "acpi_gpe_sts_ioport_writeb",
    .sstate = TRACE_ACPI_GPE_STS_IOPORT_WRITEB_ENABLED,
    .dstate = &_TRACE_ACPI_GPE_STS_IOPORT_WRITEB_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_INVALID_IDX_SELECTED_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_invalid_idx_selected",
    .sstate = TRACE_CPUHP_ACPI_INVALID_IDX_SELECTED_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_INVALID_IDX_SELECTED_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_READ_FLAGS_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_read_flags",
    .sstate = TRACE_CPUHP_ACPI_READ_FLAGS_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_READ_FLAGS_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_WRITE_IDX_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_write_idx",
    .sstate = TRACE_CPUHP_ACPI_WRITE_IDX_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_WRITE_IDX_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_WRITE_CMD_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_write_cmd",
    .sstate = TRACE_CPUHP_ACPI_WRITE_CMD_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_WRITE_CMD_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_READ_CMD_DATA_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_read_cmd_data",
    .sstate = TRACE_CPUHP_ACPI_READ_CMD_DATA_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_READ_CMD_DATA_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_READ_CMD_DATA2_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_read_cmd_data2",
    .sstate = TRACE_CPUHP_ACPI_READ_CMD_DATA2_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_READ_CMD_DATA2_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_CPU_HAS_EVENTS_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_cpu_has_events",
    .sstate = TRACE_CPUHP_ACPI_CPU_HAS_EVENTS_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_CPU_HAS_EVENTS_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_CLEAR_INSERTING_EVT_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_clear_inserting_evt",
    .sstate = TRACE_CPUHP_ACPI_CLEAR_INSERTING_EVT_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_CLEAR_INSERTING_EVT_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_CLEAR_REMOVE_EVT_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_clear_remove_evt",
    .sstate = TRACE_CPUHP_ACPI_CLEAR_REMOVE_EVT_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_CLEAR_REMOVE_EVT_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_EJECTING_INVALID_CPU_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_ejecting_invalid_cpu",
    .sstate = TRACE_CPUHP_ACPI_EJECTING_INVALID_CPU_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_EJECTING_INVALID_CPU_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_EJECTING_CPU_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_ejecting_cpu",
    .sstate = TRACE_CPUHP_ACPI_EJECTING_CPU_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_EJECTING_CPU_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_FW_REMOVE_INVALID_CPU_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_fw_remove_invalid_cpu",
    .sstate = TRACE_CPUHP_ACPI_FW_REMOVE_INVALID_CPU_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_FW_REMOVE_INVALID_CPU_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_FW_REMOVE_CPU_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_fw_remove_cpu",
    .sstate = TRACE_CPUHP_ACPI_FW_REMOVE_CPU_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_FW_REMOVE_CPU_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_WRITE_OST_EV_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_write_ost_ev",
    .sstate = TRACE_CPUHP_ACPI_WRITE_OST_EV_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_WRITE_OST_EV_DSTATE
};
TraceEvent _TRACE_CPUHP_ACPI_WRITE_OST_STATUS_EVENT = {
    .id = 0,
    .name = "cpuhp_acpi_write_ost_status",
    .sstate = TRACE_CPUHP_ACPI_WRITE_OST_STATUS_ENABLED,
    .dstate = &_TRACE_CPUHP_ACPI_WRITE_OST_STATUS_DSTATE
};
TraceEvent _TRACE_ACPI_PCI_EJECT_SLOT_EVENT = {
    .id = 0,
    .name = "acpi_pci_eject_slot",
    .sstate = TRACE_ACPI_PCI_EJECT_SLOT_ENABLED,
    .dstate = &_TRACE_ACPI_PCI_EJECT_SLOT_DSTATE
};
TraceEvent _TRACE_ACPI_PCI_UNPLUG_EVENT = {
    .id = 0,
    .name = "acpi_pci_unplug",
    .sstate = TRACE_ACPI_PCI_UNPLUG_ENABLED,
    .dstate = &_TRACE_ACPI_PCI_UNPLUG_DSTATE
};
TraceEvent _TRACE_ACPI_PCI_UNPLUG_REQUEST_EVENT = {
    .id = 0,
    .name = "acpi_pci_unplug_request",
    .sstate = TRACE_ACPI_PCI_UNPLUG_REQUEST_ENABLED,
    .dstate = &_TRACE_ACPI_PCI_UNPLUG_REQUEST_DSTATE
};
TraceEvent _TRACE_ACPI_PCI_UP_READ_EVENT = {
    .id = 0,
    .name = "acpi_pci_up_read",
    .sstate = TRACE_ACPI_PCI_UP_READ_ENABLED,
    .dstate = &_TRACE_ACPI_PCI_UP_READ_DSTATE
};
TraceEvent _TRACE_ACPI_PCI_DOWN_READ_EVENT = {
    .id = 0,
    .name = "acpi_pci_down_read",
    .sstate = TRACE_ACPI_PCI_DOWN_READ_ENABLED,
    .dstate = &_TRACE_ACPI_PCI_DOWN_READ_DSTATE
};
TraceEvent _TRACE_ACPI_PCI_FEATURES_READ_EVENT = {
    .id = 0,
    .name = "acpi_pci_features_read",
    .sstate = TRACE_ACPI_PCI_FEATURES_READ_ENABLED,
    .dstate = &_TRACE_ACPI_PCI_FEATURES_READ_DSTATE
};
TraceEvent _TRACE_ACPI_PCI_ACPI_INDEX_READ_EVENT = {
    .id = 0,
    .name = "acpi_pci_acpi_index_read",
    .sstate = TRACE_ACPI_PCI_ACPI_INDEX_READ_ENABLED,
    .dstate = &_TRACE_ACPI_PCI_ACPI_INDEX_READ_DSTATE
};
TraceEvent _TRACE_ACPI_PCI_ACPI_INDEX_WRITE_EVENT = {
    .id = 0,
    .name = "acpi_pci_acpi_index_write",
    .sstate = TRACE_ACPI_PCI_ACPI_INDEX_WRITE_ENABLED,
    .dstate = &_TRACE_ACPI_PCI_ACPI_INDEX_WRITE_DSTATE
};
TraceEvent _TRACE_ACPI_PCI_RMV_READ_EVENT = {
    .id = 0,
    .name = "acpi_pci_rmv_read",
    .sstate = TRACE_ACPI_PCI_RMV_READ_ENABLED,
    .dstate = &_TRACE_ACPI_PCI_RMV_READ_DSTATE
};
TraceEvent _TRACE_ACPI_PCI_SEL_READ_EVENT = {
    .id = 0,
    .name = "acpi_pci_sel_read",
    .sstate = TRACE_ACPI_PCI_SEL_READ_ENABLED,
    .dstate = &_TRACE_ACPI_PCI_SEL_READ_DSTATE
};
TraceEvent _TRACE_ACPI_PCI_EJ_WRITE_EVENT = {
    .id = 0,
    .name = "acpi_pci_ej_write",
    .sstate = TRACE_ACPI_PCI_EJ_WRITE_ENABLED,
    .dstate = &_TRACE_ACPI_PCI_EJ_WRITE_DSTATE
};
TraceEvent _TRACE_ACPI_PCI_SEL_WRITE_EVENT = {
    .id = 0,
    .name = "acpi_pci_sel_write",
    .sstate = TRACE_ACPI_PCI_SEL_WRITE_ENABLED,
    .dstate = &_TRACE_ACPI_PCI_SEL_WRITE_DSTATE
};
TraceEvent _TRACE_TCO_TIMER_RELOAD_EVENT = {
    .id = 0,
    .name = "tco_timer_reload",
    .sstate = TRACE_TCO_TIMER_RELOAD_ENABLED,
    .dstate = &_TRACE_TCO_TIMER_RELOAD_DSTATE
};
TraceEvent _TRACE_TCO_TIMER_EXPIRED_EVENT = {
    .id = 0,
    .name = "tco_timer_expired",
    .sstate = TRACE_TCO_TIMER_EXPIRED_ENABLED,
    .dstate = &_TRACE_TCO_TIMER_EXPIRED_DSTATE
};
TraceEvent _TRACE_TCO_IO_WRITE_EVENT = {
    .id = 0,
    .name = "tco_io_write",
    .sstate = TRACE_TCO_IO_WRITE_ENABLED,
    .dstate = &_TRACE_TCO_IO_WRITE_DSTATE
};
TraceEvent _TRACE_TCO_IO_READ_EVENT = {
    .id = 0,
    .name = "tco_io_read",
    .sstate = TRACE_TCO_IO_READ_ENABLED,
    .dstate = &_TRACE_TCO_IO_READ_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_REG_WRITE_EVENT = {
    .id = 0,
    .name = "acpi_erst_reg_write",
    .sstate = TRACE_ACPI_ERST_REG_WRITE_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_REG_WRITE_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_REG_READ_EVENT = {
    .id = 0,
    .name = "acpi_erst_reg_read",
    .sstate = TRACE_ACPI_ERST_REG_READ_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_REG_READ_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_MEM_WRITE_EVENT = {
    .id = 0,
    .name = "acpi_erst_mem_write",
    .sstate = TRACE_ACPI_ERST_MEM_WRITE_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_MEM_WRITE_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_MEM_READ_EVENT = {
    .id = 0,
    .name = "acpi_erst_mem_read",
    .sstate = TRACE_ACPI_ERST_MEM_READ_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_MEM_READ_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_PCI_BAR_0_EVENT = {
    .id = 0,
    .name = "acpi_erst_pci_bar_0",
    .sstate = TRACE_ACPI_ERST_PCI_BAR_0_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_PCI_BAR_0_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_PCI_BAR_1_EVENT = {
    .id = 0,
    .name = "acpi_erst_pci_bar_1",
    .sstate = TRACE_ACPI_ERST_PCI_BAR_1_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_PCI_BAR_1_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_REALIZEFN_IN_EVENT = {
    .id = 0,
    .name = "acpi_erst_realizefn_in",
    .sstate = TRACE_ACPI_ERST_REALIZEFN_IN_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_REALIZEFN_IN_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_REALIZEFN_OUT_EVENT = {
    .id = 0,
    .name = "acpi_erst_realizefn_out",
    .sstate = TRACE_ACPI_ERST_REALIZEFN_OUT_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_REALIZEFN_OUT_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_RESET_IN_EVENT = {
    .id = 0,
    .name = "acpi_erst_reset_in",
    .sstate = TRACE_ACPI_ERST_RESET_IN_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_RESET_IN_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_RESET_OUT_EVENT = {
    .id = 0,
    .name = "acpi_erst_reset_out",
    .sstate = TRACE_ACPI_ERST_RESET_OUT_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_RESET_OUT_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_POST_LOAD_EVENT = {
    .id = 0,
    .name = "acpi_erst_post_load",
    .sstate = TRACE_ACPI_ERST_POST_LOAD_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_POST_LOAD_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_CLASS_INIT_IN_EVENT = {
    .id = 0,
    .name = "acpi_erst_class_init_in",
    .sstate = TRACE_ACPI_ERST_CLASS_INIT_IN_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_CLASS_INIT_IN_DSTATE
};
TraceEvent _TRACE_ACPI_ERST_CLASS_INIT_OUT_EVENT = {
    .id = 0,
    .name = "acpi_erst_class_init_out",
    .sstate = TRACE_ACPI_ERST_CLASS_INIT_OUT_ENABLED,
    .dstate = &_TRACE_ACPI_ERST_CLASS_INIT_OUT_DSTATE
};
TraceEvent _TRACE_ACPI_NVDIMM_READ_FIT_EVENT = {
    .id = 0,
    .name = "acpi_nvdimm_read_fit",
    .sstate = TRACE_ACPI_NVDIMM_READ_FIT_ENABLED,
    .dstate = &_TRACE_ACPI_NVDIMM_READ_FIT_DSTATE
};
TraceEvent _TRACE_ACPI_NVDIMM_LABEL_INFO_EVENT = {
    .id = 0,
    .name = "acpi_nvdimm_label_info",
    .sstate = TRACE_ACPI_NVDIMM_LABEL_INFO_ENABLED,
    .dstate = &_TRACE_ACPI_NVDIMM_LABEL_INFO_DSTATE
};
TraceEvent _TRACE_ACPI_NVDIMM_LABEL_OVERFLOW_EVENT = {
    .id = 0,
    .name = "acpi_nvdimm_label_overflow",
    .sstate = TRACE_ACPI_NVDIMM_LABEL_OVERFLOW_ENABLED,
    .dstate = &_TRACE_ACPI_NVDIMM_LABEL_OVERFLOW_DSTATE
};
TraceEvent _TRACE_ACPI_NVDIMM_LABEL_OVERSIZE_EVENT = {
    .id = 0,
    .name = "acpi_nvdimm_label_oversize",
    .sstate = TRACE_ACPI_NVDIMM_LABEL_OVERSIZE_ENABLED,
    .dstate = &_TRACE_ACPI_NVDIMM_LABEL_OVERSIZE_DSTATE
};
TraceEvent _TRACE_ACPI_NVDIMM_LABEL_XFER_EXCEED_EVENT = {
    .id = 0,
    .name = "acpi_nvdimm_label_xfer_exceed",
    .sstate = TRACE_ACPI_NVDIMM_LABEL_XFER_EXCEED_ENABLED,
    .dstate = &_TRACE_ACPI_NVDIMM_LABEL_XFER_EXCEED_DSTATE
};
TraceEvent _TRACE_ACPI_NVDIMM_READ_LABEL_EVENT = {
    .id = 0,
    .name = "acpi_nvdimm_read_label",
    .sstate = TRACE_ACPI_NVDIMM_READ_LABEL_ENABLED,
    .dstate = &_TRACE_ACPI_NVDIMM_READ_LABEL_DSTATE
};
TraceEvent _TRACE_ACPI_NVDIMM_WRITE_LABEL_EVENT = {
    .id = 0,
    .name = "acpi_nvdimm_write_label",
    .sstate = TRACE_ACPI_NVDIMM_WRITE_LABEL_ENABLED,
    .dstate = &_TRACE_ACPI_NVDIMM_WRITE_LABEL_DSTATE
};
TraceEvent _TRACE_ACPI_NVDIMM_READ_IO_PORT_EVENT = {
    .id = 0,
    .name = "acpi_nvdimm_read_io_port",
    .sstate = TRACE_ACPI_NVDIMM_READ_IO_PORT_ENABLED,
    .dstate = &_TRACE_ACPI_NVDIMM_READ_IO_PORT_DSTATE
};
TraceEvent _TRACE_ACPI_NVDIMM_DSM_MEM_ADDR_EVENT = {
    .id = 0,
    .name = "acpi_nvdimm_dsm_mem_addr",
    .sstate = TRACE_ACPI_NVDIMM_DSM_MEM_ADDR_ENABLED,
    .dstate = &_TRACE_ACPI_NVDIMM_DSM_MEM_ADDR_DSTATE
};
TraceEvent _TRACE_ACPI_NVDIMM_DSM_INFO_EVENT = {
    .id = 0,
    .name = "acpi_nvdimm_dsm_info",
    .sstate = TRACE_ACPI_NVDIMM_DSM_INFO_ENABLED,
    .dstate = &_TRACE_ACPI_NVDIMM_DSM_INFO_DSTATE
};
TraceEvent _TRACE_ACPI_NVDIMM_INVALID_REVISION_EVENT = {
    .id = 0,
    .name = "acpi_nvdimm_invalid_revision",
    .sstate = TRACE_ACPI_NVDIMM_INVALID_REVISION_ENABLED,
    .dstate = &_TRACE_ACPI_NVDIMM_INVALID_REVISION_DSTATE
};
TraceEvent *hw_acpi_trace_events[] = {
    &_TRACE_MHP_ACPI_INVALID_SLOT_SELECTED_EVENT,
    &_TRACE_MHP_ACPI_EJECTING_INVALID_SLOT_EVENT,
    &_TRACE_MHP_ACPI_READ_ADDR_LO_EVENT,
    &_TRACE_MHP_ACPI_READ_ADDR_HI_EVENT,
    &_TRACE_MHP_ACPI_READ_SIZE_LO_EVENT,
    &_TRACE_MHP_ACPI_READ_SIZE_HI_EVENT,
    &_TRACE_MHP_ACPI_READ_PXM_EVENT,
    &_TRACE_MHP_ACPI_READ_FLAGS_EVENT,
    &_TRACE_MHP_ACPI_WRITE_SLOT_EVENT,
    &_TRACE_MHP_ACPI_WRITE_OST_EV_EVENT,
    &_TRACE_MHP_ACPI_WRITE_OST_STATUS_EVENT,
    &_TRACE_MHP_ACPI_CLEAR_INSERT_EVT_EVENT,
    &_TRACE_MHP_ACPI_CLEAR_REMOVE_EVT_EVENT,
    &_TRACE_MHP_ACPI_PC_DIMM_DELETED_EVENT,
    &_TRACE_MHP_ACPI_PC_DIMM_DELETE_FAILED_EVENT,
    &_TRACE_ACPI_GPE_EN_IOPORT_READB_EVENT,
    &_TRACE_ACPI_GPE_EN_IOPORT_WRITEB_EVENT,
    &_TRACE_ACPI_GPE_STS_IOPORT_READB_EVENT,
    &_TRACE_ACPI_GPE_STS_IOPORT_WRITEB_EVENT,
    &_TRACE_CPUHP_ACPI_INVALID_IDX_SELECTED_EVENT,
    &_TRACE_CPUHP_ACPI_READ_FLAGS_EVENT,
    &_TRACE_CPUHP_ACPI_WRITE_IDX_EVENT,
    &_TRACE_CPUHP_ACPI_WRITE_CMD_EVENT,
    &_TRACE_CPUHP_ACPI_READ_CMD_DATA_EVENT,
    &_TRACE_CPUHP_ACPI_READ_CMD_DATA2_EVENT,
    &_TRACE_CPUHP_ACPI_CPU_HAS_EVENTS_EVENT,
    &_TRACE_CPUHP_ACPI_CLEAR_INSERTING_EVT_EVENT,
    &_TRACE_CPUHP_ACPI_CLEAR_REMOVE_EVT_EVENT,
    &_TRACE_CPUHP_ACPI_EJECTING_INVALID_CPU_EVENT,
    &_TRACE_CPUHP_ACPI_EJECTING_CPU_EVENT,
    &_TRACE_CPUHP_ACPI_FW_REMOVE_INVALID_CPU_EVENT,
    &_TRACE_CPUHP_ACPI_FW_REMOVE_CPU_EVENT,
    &_TRACE_CPUHP_ACPI_WRITE_OST_EV_EVENT,
    &_TRACE_CPUHP_ACPI_WRITE_OST_STATUS_EVENT,
    &_TRACE_ACPI_PCI_EJECT_SLOT_EVENT,
    &_TRACE_ACPI_PCI_UNPLUG_EVENT,
    &_TRACE_ACPI_PCI_UNPLUG_REQUEST_EVENT,
    &_TRACE_ACPI_PCI_UP_READ_EVENT,
    &_TRACE_ACPI_PCI_DOWN_READ_EVENT,
    &_TRACE_ACPI_PCI_FEATURES_READ_EVENT,
    &_TRACE_ACPI_PCI_ACPI_INDEX_READ_EVENT,
    &_TRACE_ACPI_PCI_ACPI_INDEX_WRITE_EVENT,
    &_TRACE_ACPI_PCI_RMV_READ_EVENT,
    &_TRACE_ACPI_PCI_SEL_READ_EVENT,
    &_TRACE_ACPI_PCI_EJ_WRITE_EVENT,
    &_TRACE_ACPI_PCI_SEL_WRITE_EVENT,
    &_TRACE_TCO_TIMER_RELOAD_EVENT,
    &_TRACE_TCO_TIMER_EXPIRED_EVENT,
    &_TRACE_TCO_IO_WRITE_EVENT,
    &_TRACE_TCO_IO_READ_EVENT,
    &_TRACE_ACPI_ERST_REG_WRITE_EVENT,
    &_TRACE_ACPI_ERST_REG_READ_EVENT,
    &_TRACE_ACPI_ERST_MEM_WRITE_EVENT,
    &_TRACE_ACPI_ERST_MEM_READ_EVENT,
    &_TRACE_ACPI_ERST_PCI_BAR_0_EVENT,
    &_TRACE_ACPI_ERST_PCI_BAR_1_EVENT,
    &_TRACE_ACPI_ERST_REALIZEFN_IN_EVENT,
    &_TRACE_ACPI_ERST_REALIZEFN_OUT_EVENT,
    &_TRACE_ACPI_ERST_RESET_IN_EVENT,
    &_TRACE_ACPI_ERST_RESET_OUT_EVENT,
    &_TRACE_ACPI_ERST_POST_LOAD_EVENT,
    &_TRACE_ACPI_ERST_CLASS_INIT_IN_EVENT,
    &_TRACE_ACPI_ERST_CLASS_INIT_OUT_EVENT,
    &_TRACE_ACPI_NVDIMM_READ_FIT_EVENT,
    &_TRACE_ACPI_NVDIMM_LABEL_INFO_EVENT,
    &_TRACE_ACPI_NVDIMM_LABEL_OVERFLOW_EVENT,
    &_TRACE_ACPI_NVDIMM_LABEL_OVERSIZE_EVENT,
    &_TRACE_ACPI_NVDIMM_LABEL_XFER_EXCEED_EVENT,
    &_TRACE_ACPI_NVDIMM_READ_LABEL_EVENT,
    &_TRACE_ACPI_NVDIMM_WRITE_LABEL_EVENT,
    &_TRACE_ACPI_NVDIMM_READ_IO_PORT_EVENT,
    &_TRACE_ACPI_NVDIMM_DSM_MEM_ADDR_EVENT,
    &_TRACE_ACPI_NVDIMM_DSM_INFO_EVENT,
    &_TRACE_ACPI_NVDIMM_INVALID_REVISION_EVENT,
  NULL,
};

static void trace_hw_acpi_register_events(void)
{
    trace_event_register_group(hw_acpi_trace_events);
}
trace_init(trace_hw_acpi_register_events)
