/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_misc.h"

uint16_t _TRACE_ALLWINNER_CPUCFG_CPU_RESET_DSTATE;
uint16_t _TRACE_ALLWINNER_CPUCFG_READ_DSTATE;
uint16_t _TRACE_ALLWINNER_CPUCFG_WRITE_DSTATE;
uint16_t _TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_DSTATE;
uint16_t _TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_DSTATE;
uint16_t _TRACE_ALLWINNER_H3_DRAMCOM_READ_DSTATE;
uint16_t _TRACE_ALLWINNER_H3_DRAMCOM_WRITE_DSTATE;
uint16_t _TRACE_ALLWINNER_H3_DRAMCTL_READ_DSTATE;
uint16_t _TRACE_ALLWINNER_H3_DRAMCTL_WRITE_DSTATE;
uint16_t _TRACE_ALLWINNER_H3_DRAMPHY_READ_DSTATE;
uint16_t _TRACE_ALLWINNER_H3_DRAMPHY_WRITE_DSTATE;
uint16_t _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_DSTATE;
uint16_t _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_DSTATE;
uint16_t _TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_DSTATE;
uint16_t _TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_DSTATE;
uint16_t _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_DSTATE;
uint16_t _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_DSTATE;
uint16_t _TRACE_ALLWINNER_R40_DRAMCOM_READ_DSTATE;
uint16_t _TRACE_ALLWINNER_R40_DRAMCOM_WRITE_DSTATE;
uint16_t _TRACE_ALLWINNER_R40_DRAMCTL_READ_DSTATE;
uint16_t _TRACE_ALLWINNER_R40_DRAMCTL_WRITE_DSTATE;
uint16_t _TRACE_ALLWINNER_R40_DRAMPHY_READ_DSTATE;
uint16_t _TRACE_ALLWINNER_R40_DRAMPHY_WRITE_DSTATE;
uint16_t _TRACE_ALLWINNER_SID_READ_DSTATE;
uint16_t _TRACE_ALLWINNER_SID_WRITE_DSTATE;
uint16_t _TRACE_ALLWINNER_SRAMC_READ_DSTATE;
uint16_t _TRACE_ALLWINNER_SRAMC_WRITE_DSTATE;
uint16_t _TRACE_AVR_POWER_READ_DSTATE;
uint16_t _TRACE_AVR_POWER_WRITE_DSTATE;
uint16_t _TRACE_AXP2XX_RX_DSTATE;
uint16_t _TRACE_AXP2XX_SELECT_DSTATE;
uint16_t _TRACE_AXP2XX_TX_DSTATE;
uint16_t _TRACE_ECC_MEM_WRITEL_MER_DSTATE;
uint16_t _TRACE_ECC_MEM_WRITEL_MDR_DSTATE;
uint16_t _TRACE_ECC_MEM_WRITEL_MFSR_DSTATE;
uint16_t _TRACE_ECC_MEM_WRITEL_VCR_DSTATE;
uint16_t _TRACE_ECC_MEM_WRITEL_DR_DSTATE;
uint16_t _TRACE_ECC_MEM_WRITEL_ECR0_DSTATE;
uint16_t _TRACE_ECC_MEM_WRITEL_ECR1_DSTATE;
uint16_t _TRACE_ECC_MEM_READL_MER_DSTATE;
uint16_t _TRACE_ECC_MEM_READL_MDR_DSTATE;
uint16_t _TRACE_ECC_MEM_READL_MFSR_DSTATE;
uint16_t _TRACE_ECC_MEM_READL_VCR_DSTATE;
uint16_t _TRACE_ECC_MEM_READL_MFAR0_DSTATE;
uint16_t _TRACE_ECC_MEM_READL_MFAR1_DSTATE;
uint16_t _TRACE_ECC_MEM_READL_DR_DSTATE;
uint16_t _TRACE_ECC_MEM_READL_ECR0_DSTATE;
uint16_t _TRACE_ECC_MEM_READL_ECR1_DSTATE;
uint16_t _TRACE_ECC_DIAG_MEM_WRITEB_DSTATE;
uint16_t _TRACE_ECC_DIAG_MEM_READB_DSTATE;
uint16_t _TRACE_EMPTY_SLOT_WRITE_DSTATE;
uint16_t _TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_DSTATE;
uint16_t _TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_DSTATE;
uint16_t _TRACE_SLAVIO_SET_POWER_FAIL_DSTATE;
uint16_t _TRACE_SLAVIO_CFG_MEM_WRITEB_DSTATE;
uint16_t _TRACE_SLAVIO_CFG_MEM_READB_DSTATE;
uint16_t _TRACE_SLAVIO_DIAG_MEM_WRITEB_DSTATE;
uint16_t _TRACE_SLAVIO_DIAG_MEM_READB_DSTATE;
uint16_t _TRACE_SLAVIO_MDM_MEM_WRITEB_DSTATE;
uint16_t _TRACE_SLAVIO_MDM_MEM_READB_DSTATE;
uint16_t _TRACE_SLAVIO_AUX1_MEM_WRITEB_DSTATE;
uint16_t _TRACE_SLAVIO_AUX1_MEM_READB_DSTATE;
uint16_t _TRACE_SLAVIO_AUX2_MEM_WRITEB_DSTATE;
uint16_t _TRACE_SLAVIO_AUX2_MEM_READB_DSTATE;
uint16_t _TRACE_APC_MEM_WRITEB_DSTATE;
uint16_t _TRACE_APC_MEM_READB_DSTATE;
uint16_t _TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_DSTATE;
uint16_t _TRACE_SLAVIO_SYSCTRL_MEM_READL_DSTATE;
uint16_t _TRACE_SLAVIO_LED_MEM_WRITEW_DSTATE;
uint16_t _TRACE_SLAVIO_LED_MEM_READW_DSTATE;
uint16_t _TRACE_ASPEED_SBC_IGNORE_CMD_DSTATE;
uint16_t _TRACE_ASPEED_SBC_HANDLE_CMD_DSTATE;
uint16_t _TRACE_ASPEED_SBC_OTP_READ_DSTATE;
uint16_t _TRACE_ASPEED_SBC_OTP_PROG_DSTATE;
uint16_t _TRACE_ASPEED_SCU_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_SCU_READ_DSTATE;
uint16_t _TRACE_ASPEED_AST2700_SCU_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_AST2700_SCU_READ_DSTATE;
uint16_t _TRACE_ASPEED_AST2700_SCUIO_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_AST2700_SCUIO_READ_DSTATE;
uint16_t _TRACE_MPS2_SCC_READ_DSTATE;
uint16_t _TRACE_MPS2_SCC_WRITE_DSTATE;
uint16_t _TRACE_MPS2_SCC_RESET_DSTATE;
uint16_t _TRACE_MPS2_SCC_CFG_WRITE_DSTATE;
uint16_t _TRACE_MPS2_SCC_CFG_READ_DSTATE;
uint16_t _TRACE_MPS2_FPGAIO_READ_DSTATE;
uint16_t _TRACE_MPS2_FPGAIO_WRITE_DSTATE;
uint16_t _TRACE_MPS2_FPGAIO_RESET_DSTATE;
uint16_t _TRACE_MSF2_SYSREG_WRITE_DSTATE;
uint16_t _TRACE_MSF2_SYSREG_READ_DSTATE;
uint16_t _TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_DSTATE;
uint16_t _TRACE_IMX7_GPR_READ_DSTATE;
uint16_t _TRACE_IMX7_GPR_WRITE_DSTATE;
uint16_t _TRACE_IMX7_SNVS_READ_DSTATE;
uint16_t _TRACE_IMX7_SNVS_WRITE_DSTATE;
uint16_t _TRACE_MOS6522_SET_COUNTER_DSTATE;
uint16_t _TRACE_MOS6522_GET_NEXT_IRQ_TIME_DSTATE;
uint16_t _TRACE_MOS6522_SET_SR_INT_DSTATE;
uint16_t _TRACE_MOS6522_WRITE_DSTATE;
uint16_t _TRACE_MOS6522_READ_DSTATE;
uint16_t _TRACE_NPCM_CLK_READ_DSTATE;
uint16_t _TRACE_NPCM_CLK_WRITE_DSTATE;
uint16_t _TRACE_NPCM_GCR_READ_DSTATE;
uint16_t _TRACE_NPCM_GCR_WRITE_DSTATE;
uint16_t _TRACE_NPCM7XX_MFT_READ_DSTATE;
uint16_t _TRACE_NPCM7XX_MFT_WRITE_DSTATE;
uint16_t _TRACE_NPCM7XX_MFT_RPM_DSTATE;
uint16_t _TRACE_NPCM7XX_MFT_CAPTURE_DSTATE;
uint16_t _TRACE_NPCM7XX_MFT_UPDATE_CLOCK_DSTATE;
uint16_t _TRACE_NPCM7XX_MFT_SET_DUTY_DSTATE;
uint16_t _TRACE_NPCM7XX_RNG_READ_DSTATE;
uint16_t _TRACE_NPCM7XX_RNG_WRITE_DSTATE;
uint16_t _TRACE_NPCM7XX_PWM_READ_DSTATE;
uint16_t _TRACE_NPCM7XX_PWM_WRITE_DSTATE;
uint16_t _TRACE_NPCM7XX_PWM_UPDATE_FREQ_DSTATE;
uint16_t _TRACE_NPCM7XX_PWM_UPDATE_DUTY_DSTATE;
uint16_t _TRACE_STM32_RCC_READ_DSTATE;
uint16_t _TRACE_STM32_RCC_WRITE_DSTATE;
uint16_t _TRACE_STM32_RCC_PULSE_ENABLE_DSTATE;
uint16_t _TRACE_STM32_RCC_PULSE_RESET_DSTATE;
uint16_t _TRACE_STM32F4XX_SYSCFG_SET_IRQ_DSTATE;
uint16_t _TRACE_STM32F4XX_PULSE_EXTI_DSTATE;
uint16_t _TRACE_STM32F4XX_SYSCFG_READ_DSTATE;
uint16_t _TRACE_STM32F4XX_SYSCFG_WRITE_DSTATE;
uint16_t _TRACE_STM32F4XX_EXTI_SET_IRQ_DSTATE;
uint16_t _TRACE_STM32F4XX_EXTI_READ_DSTATE;
uint16_t _TRACE_STM32F4XX_EXTI_WRITE_DSTATE;
uint16_t _TRACE_STM32L4X5_SYSCFG_SET_IRQ_DSTATE;
uint16_t _TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_DSTATE;
uint16_t _TRACE_STM32L4X5_SYSCFG_READ_DSTATE;
uint16_t _TRACE_STM32L4X5_SYSCFG_WRITE_DSTATE;
uint16_t _TRACE_STM32L4X5_EXTI_SET_IRQ_DSTATE;
uint16_t _TRACE_STM32L4X5_EXTI_READ_DSTATE;
uint16_t _TRACE_STM32L4X5_EXTI_WRITE_DSTATE;
uint16_t _TRACE_STM32L4X5_RCC_READ_DSTATE;
uint16_t _TRACE_STM32L4X5_RCC_WRITE_DSTATE;
uint16_t _TRACE_STM32L4X5_RCC_MUX_ENABLE_DSTATE;
uint16_t _TRACE_STM32L4X5_RCC_MUX_DISABLE_DSTATE;
uint16_t _TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_DSTATE;
uint16_t _TRACE_STM32L4X5_RCC_MUX_SET_SRC_DSTATE;
uint16_t _TRACE_STM32L4X5_RCC_MUX_UPDATE_DSTATE;
uint16_t _TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_DSTATE;
uint16_t _TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_DSTATE;
uint16_t _TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_DSTATE;
uint16_t _TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_DSTATE;
uint16_t _TRACE_STM32L4X5_RCC_PLL_UPDATE_DSTATE;
uint16_t _TRACE_TZ_MPC_REG_READ_DSTATE;
uint16_t _TRACE_TZ_MPC_REG_WRITE_DSTATE;
uint16_t _TRACE_TZ_MPC_MEM_BLOCKED_READ_DSTATE;
uint16_t _TRACE_TZ_MPC_MEM_BLOCKED_WRITE_DSTATE;
uint16_t _TRACE_TZ_MPC_TRANSLATE_DSTATE;
uint16_t _TRACE_TZ_MPC_IOMMU_NOTIFY_DSTATE;
uint16_t _TRACE_TZ_MSC_RESET_DSTATE;
uint16_t _TRACE_TZ_MSC_CFG_NONSEC_DSTATE;
uint16_t _TRACE_TZ_MSC_CFG_SEC_RESP_DSTATE;
uint16_t _TRACE_TZ_MSC_IRQ_CLEAR_DSTATE;
uint16_t _TRACE_TZ_MSC_UPDATE_IRQ_DSTATE;
uint16_t _TRACE_TZ_MSC_ACCESS_BLOCKED_DSTATE;
uint16_t _TRACE_TZ_PPC_RESET_DSTATE;
uint16_t _TRACE_TZ_PPC_CFG_NONSEC_DSTATE;
uint16_t _TRACE_TZ_PPC_CFG_AP_DSTATE;
uint16_t _TRACE_TZ_PPC_CFG_SEC_RESP_DSTATE;
uint16_t _TRACE_TZ_PPC_IRQ_ENABLE_DSTATE;
uint16_t _TRACE_TZ_PPC_IRQ_CLEAR_DSTATE;
uint16_t _TRACE_TZ_PPC_UPDATE_IRQ_DSTATE;
uint16_t _TRACE_TZ_PPC_READ_BLOCKED_DSTATE;
uint16_t _TRACE_TZ_PPC_WRITE_BLOCKED_DSTATE;
uint16_t _TRACE_IOTKIT_SECCTL_S_READ_DSTATE;
uint16_t _TRACE_IOTKIT_SECCTL_S_WRITE_DSTATE;
uint16_t _TRACE_IOTKIT_SECCTL_NS_READ_DSTATE;
uint16_t _TRACE_IOTKIT_SECCTL_NS_WRITE_DSTATE;
uint16_t _TRACE_IMX6_ANALOG_GET_PERIPH_CLK_DSTATE;
uint16_t _TRACE_IMX6_ANALOG_GET_PLL2_CLK_DSTATE;
uint16_t _TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_DSTATE;
uint16_t _TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_DSTATE;
uint16_t _TRACE_IMX6_ANALOG_READ_DSTATE;
uint16_t _TRACE_IMX6_ANALOG_WRITE_DSTATE;
uint16_t _TRACE_IMX6_CCM_GET_AHB_CLK_DSTATE;
uint16_t _TRACE_IMX6_CCM_GET_IPG_CLK_DSTATE;
uint16_t _TRACE_IMX6_CCM_GET_PER_CLK_DSTATE;
uint16_t _TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_DSTATE;
uint16_t _TRACE_IMX6_CCM_READ_DSTATE;
uint16_t _TRACE_IMX6_CCM_RESET_DSTATE;
uint16_t _TRACE_IMX6_CCM_WRITE_DSTATE;
uint16_t _TRACE_CCM_ENTRY_DSTATE;
uint16_t _TRACE_CCM_FREQ_DSTATE;
uint16_t _TRACE_CCM_CLOCK_FREQ_DSTATE;
uint16_t _TRACE_CCM_READ_REG_DSTATE;
uint16_t _TRACE_CCM_WRITE_REG_DSTATE;
uint16_t _TRACE_IMX6_SRC_READ_DSTATE;
uint16_t _TRACE_IMX6_SRC_WRITE_DSTATE;
uint16_t _TRACE_IMX6_CLEAR_RESET_BIT_DSTATE;
uint16_t _TRACE_IMX6_SRC_RESET_DSTATE;
uint16_t _TRACE_IMX7_SRC_READ_DSTATE;
uint16_t _TRACE_IMX7_SRC_WRITE_DSTATE;
uint16_t _TRACE_IOTKIT_SYSINFO_READ_DSTATE;
uint16_t _TRACE_IOTKIT_SYSINFO_WRITE_DSTATE;
uint16_t _TRACE_IOTKIT_SYSCTL_READ_DSTATE;
uint16_t _TRACE_IOTKIT_SYSCTL_WRITE_DSTATE;
uint16_t _TRACE_IOTKIT_SYSCTL_RESET_DSTATE;
uint16_t _TRACE_ARMSSE_CPU_PWRCTRL_READ_DSTATE;
uint16_t _TRACE_ARMSSE_CPU_PWRCTRL_WRITE_DSTATE;
uint16_t _TRACE_ARMSSE_CPUID_READ_DSTATE;
uint16_t _TRACE_ARMSSE_CPUID_WRITE_DSTATE;
uint16_t _TRACE_ARMSSE_MHU_READ_DSTATE;
uint16_t _TRACE_ARMSSE_MHU_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_XDMA_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_I3C_READ_DSTATE;
uint16_t _TRACE_ASPEED_I3C_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_I3C_DEVICE_READ_DSTATE;
uint16_t _TRACE_ASPEED_I3C_DEVICE_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_SDMC_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_SDMC_READ_DSTATE;
uint16_t _TRACE_ASPEED_PECI_READ_DSTATE;
uint16_t _TRACE_ASPEED_PECI_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_PECI_RAISE_INTERRUPT_DSTATE;
uint16_t _TRACE_ASPEED_HACE_READ_DSTATE;
uint16_t _TRACE_ASPEED_HACE_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_HACE_HASH_SG_DSTATE;
uint16_t _TRACE_ASPEED_HACE_HASH_ADDR_DSTATE;
uint16_t _TRACE_ASPEED_HACE_HASH_EXECUTE_ACC_MODE_DSTATE;
uint16_t _TRACE_ASPEED_HACE_HEXDUMP_DSTATE;
uint16_t _TRACE_BCM2835_MBOX_PROPERTY_DSTATE;
uint16_t _TRACE_BCM2835_MBOX_WRITE_DSTATE;
uint16_t _TRACE_BCM2835_MBOX_READ_DSTATE;
uint16_t _TRACE_BCM2835_MBOX_IRQ_DSTATE;
uint16_t _TRACE_VIA1_RTC_UPDATE_DATA_OUT_DSTATE;
uint16_t _TRACE_VIA1_RTC_UPDATE_DATA_IN_DSTATE;
uint16_t _TRACE_VIA1_RTC_INTERNAL_STATUS_DSTATE;
uint16_t _TRACE_VIA1_RTC_INTERNAL_CMD_DSTATE;
uint16_t _TRACE_VIA1_RTC_CMD_INVALID_DSTATE;
uint16_t _TRACE_VIA1_RTC_INTERNAL_TIME_DSTATE;
uint16_t _TRACE_VIA1_RTC_INTERNAL_SET_CMD_DSTATE;
uint16_t _TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_DSTATE;
uint16_t _TRACE_VIA1_RTC_INTERNAL_SET_ALT_DSTATE;
uint16_t _TRACE_VIA1_RTC_CMD_SECONDS_READ_DSTATE;
uint16_t _TRACE_VIA1_RTC_CMD_SECONDS_WRITE_DSTATE;
uint16_t _TRACE_VIA1_RTC_CMD_TEST_WRITE_DSTATE;
uint16_t _TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_DSTATE;
uint16_t _TRACE_VIA1_RTC_CMD_PRAM_READ_DSTATE;
uint16_t _TRACE_VIA1_RTC_CMD_PRAM_WRITE_DSTATE;
uint16_t _TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_DSTATE;
uint16_t _TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_DSTATE;
uint16_t _TRACE_VIA1_ADB_SEND_DSTATE;
uint16_t _TRACE_VIA1_ADB_RECEIVE_DSTATE;
uint16_t _TRACE_VIA1_ADB_POLL_DSTATE;
uint16_t _TRACE_VIA1_ADB_NETBSD_ENUM_HACK_DSTATE;
uint16_t _TRACE_VIA1_AUXMODE_DSTATE;
uint16_t _TRACE_VIA1_TIMER_HACK_STATE_DSTATE;
uint16_t _TRACE_GRLIB_AHB_PNP_READ_DSTATE;
uint16_t _TRACE_GRLIB_APB_PNP_READ_DSTATE;
uint16_t _TRACE_LED_SET_INTENSITY_DSTATE;
uint16_t _TRACE_LED_CHANGE_INTENSITY_DSTATE;
uint16_t _TRACE_BCM2835_CPRMAN_READ_DSTATE;
uint16_t _TRACE_BCM2835_CPRMAN_WRITE_DSTATE;
uint16_t _TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_DSTATE;
uint16_t _TRACE_VIRT_CTRL_READ_DSTATE;
uint16_t _TRACE_VIRT_CTRL_WRITE_DSTATE;
uint16_t _TRACE_VIRT_CTRL_RESET_DSTATE;
uint16_t _TRACE_VIRT_CTRL_REALIZE_DSTATE;
uint16_t _TRACE_VIRT_CTRL_INSTANCE_INIT_DSTATE;
uint16_t _TRACE_LASI_CHIP_MEM_VALID_DSTATE;
uint16_t _TRACE_LASI_CHIP_READ_DSTATE;
uint16_t _TRACE_LASI_CHIP_WRITE_DSTATE;
uint16_t _TRACE_DJMEMC_READ_DSTATE;
uint16_t _TRACE_DJMEMC_WRITE_DSTATE;
uint16_t _TRACE_IOSB_READ_DSTATE;
uint16_t _TRACE_IOSB_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_SLI_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_SLI_READ_DSTATE;
uint16_t _TRACE_ASPEED_SLIIO_WRITE_DSTATE;
uint16_t _TRACE_ASPEED_SLIIO_READ_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_IRQ_HANDLER_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_NEW_PEER_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_ADD_VECTOR_FAILURE_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_ADD_VECTOR_SUCCESS_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_IRQ_RESOLVED_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_PROTO_VER_OWN_ID_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_SHMEM_SIZE_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_SHMEM_MAP_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_MMIO_MAP_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_READ_MMR_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_READ_MMR_DOORBELL_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_READ_WRITE_MMR_INVALID_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_INTERRUPT_INVALID_PEER_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_WRITE_MMR_DSTATE;
uint16_t _TRACE_IVSHMEM_FLAT_INTERRUPT_PEER_DSTATE;
uint16_t _TRACE_I2C_ECHO_EVENT_DSTATE;
uint16_t _TRACE_I2C_ECHO_RECV_DSTATE;
uint16_t _TRACE_I2C_ECHO_SEND_DSTATE;
TraceEvent _TRACE_ALLWINNER_CPUCFG_CPU_RESET_EVENT = {
    .id = 0,
    .name = "allwinner_cpucfg_cpu_reset",
    .sstate = TRACE_ALLWINNER_CPUCFG_CPU_RESET_ENABLED,
    .dstate = &_TRACE_ALLWINNER_CPUCFG_CPU_RESET_DSTATE
};
TraceEvent _TRACE_ALLWINNER_CPUCFG_READ_EVENT = {
    .id = 0,
    .name = "allwinner_cpucfg_read",
    .sstate = TRACE_ALLWINNER_CPUCFG_READ_ENABLED,
    .dstate = &_TRACE_ALLWINNER_CPUCFG_READ_DSTATE
};
TraceEvent _TRACE_ALLWINNER_CPUCFG_WRITE_EVENT = {
    .id = 0,
    .name = "allwinner_cpucfg_write",
    .sstate = TRACE_ALLWINNER_CPUCFG_WRITE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_CPUCFG_WRITE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_EVENT = {
    .id = 0,
    .name = "allwinner_h3_dramc_rowmirror_disable",
    .sstate = TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_EVENT = {
    .id = 0,
    .name = "allwinner_h3_dramc_rowmirror_enable",
    .sstate = TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_H3_DRAMCOM_READ_EVENT = {
    .id = 0,
    .name = "allwinner_h3_dramcom_read",
    .sstate = TRACE_ALLWINNER_H3_DRAMCOM_READ_ENABLED,
    .dstate = &_TRACE_ALLWINNER_H3_DRAMCOM_READ_DSTATE
};
TraceEvent _TRACE_ALLWINNER_H3_DRAMCOM_WRITE_EVENT = {
    .id = 0,
    .name = "allwinner_h3_dramcom_write",
    .sstate = TRACE_ALLWINNER_H3_DRAMCOM_WRITE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_H3_DRAMCOM_WRITE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_H3_DRAMCTL_READ_EVENT = {
    .id = 0,
    .name = "allwinner_h3_dramctl_read",
    .sstate = TRACE_ALLWINNER_H3_DRAMCTL_READ_ENABLED,
    .dstate = &_TRACE_ALLWINNER_H3_DRAMCTL_READ_DSTATE
};
TraceEvent _TRACE_ALLWINNER_H3_DRAMCTL_WRITE_EVENT = {
    .id = 0,
    .name = "allwinner_h3_dramctl_write",
    .sstate = TRACE_ALLWINNER_H3_DRAMCTL_WRITE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_H3_DRAMCTL_WRITE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_H3_DRAMPHY_READ_EVENT = {
    .id = 0,
    .name = "allwinner_h3_dramphy_read",
    .sstate = TRACE_ALLWINNER_H3_DRAMPHY_READ_ENABLED,
    .dstate = &_TRACE_ALLWINNER_H3_DRAMPHY_READ_DSTATE
};
TraceEvent _TRACE_ALLWINNER_H3_DRAMPHY_WRITE_EVENT = {
    .id = 0,
    .name = "allwinner_h3_dramphy_write",
    .sstate = TRACE_ALLWINNER_H3_DRAMPHY_WRITE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_H3_DRAMPHY_WRITE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_EVENT = {
    .id = 0,
    .name = "allwinner_r40_dramc_detect_cells_disable",
    .sstate = TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_EVENT = {
    .id = 0,
    .name = "allwinner_r40_dramc_detect_cells_enable",
    .sstate = TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_EVENT = {
    .id = 0,
    .name = "allwinner_r40_dramc_map_rows",
    .sstate = TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_ENABLED,
    .dstate = &_TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_DSTATE
};
TraceEvent _TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_EVENT = {
    .id = 0,
    .name = "allwinner_r40_dramc_offset_to_cell",
    .sstate = TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_ENABLED,
    .dstate = &_TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_DSTATE
};
TraceEvent _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_EVENT = {
    .id = 0,
    .name = "allwinner_r40_dramc_detect_cell_write",
    .sstate = TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_EVENT = {
    .id = 0,
    .name = "allwinner_r40_dramc_detect_cell_read",
    .sstate = TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_ENABLED,
    .dstate = &_TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_DSTATE
};
TraceEvent _TRACE_ALLWINNER_R40_DRAMCOM_READ_EVENT = {
    .id = 0,
    .name = "allwinner_r40_dramcom_read",
    .sstate = TRACE_ALLWINNER_R40_DRAMCOM_READ_ENABLED,
    .dstate = &_TRACE_ALLWINNER_R40_DRAMCOM_READ_DSTATE
};
TraceEvent _TRACE_ALLWINNER_R40_DRAMCOM_WRITE_EVENT = {
    .id = 0,
    .name = "allwinner_r40_dramcom_write",
    .sstate = TRACE_ALLWINNER_R40_DRAMCOM_WRITE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_R40_DRAMCOM_WRITE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_R40_DRAMCTL_READ_EVENT = {
    .id = 0,
    .name = "allwinner_r40_dramctl_read",
    .sstate = TRACE_ALLWINNER_R40_DRAMCTL_READ_ENABLED,
    .dstate = &_TRACE_ALLWINNER_R40_DRAMCTL_READ_DSTATE
};
TraceEvent _TRACE_ALLWINNER_R40_DRAMCTL_WRITE_EVENT = {
    .id = 0,
    .name = "allwinner_r40_dramctl_write",
    .sstate = TRACE_ALLWINNER_R40_DRAMCTL_WRITE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_R40_DRAMCTL_WRITE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_R40_DRAMPHY_READ_EVENT = {
    .id = 0,
    .name = "allwinner_r40_dramphy_read",
    .sstate = TRACE_ALLWINNER_R40_DRAMPHY_READ_ENABLED,
    .dstate = &_TRACE_ALLWINNER_R40_DRAMPHY_READ_DSTATE
};
TraceEvent _TRACE_ALLWINNER_R40_DRAMPHY_WRITE_EVENT = {
    .id = 0,
    .name = "allwinner_r40_dramphy_write",
    .sstate = TRACE_ALLWINNER_R40_DRAMPHY_WRITE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_R40_DRAMPHY_WRITE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_SID_READ_EVENT = {
    .id = 0,
    .name = "allwinner_sid_read",
    .sstate = TRACE_ALLWINNER_SID_READ_ENABLED,
    .dstate = &_TRACE_ALLWINNER_SID_READ_DSTATE
};
TraceEvent _TRACE_ALLWINNER_SID_WRITE_EVENT = {
    .id = 0,
    .name = "allwinner_sid_write",
    .sstate = TRACE_ALLWINNER_SID_WRITE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_SID_WRITE_DSTATE
};
TraceEvent _TRACE_ALLWINNER_SRAMC_READ_EVENT = {
    .id = 0,
    .name = "allwinner_sramc_read",
    .sstate = TRACE_ALLWINNER_SRAMC_READ_ENABLED,
    .dstate = &_TRACE_ALLWINNER_SRAMC_READ_DSTATE
};
TraceEvent _TRACE_ALLWINNER_SRAMC_WRITE_EVENT = {
    .id = 0,
    .name = "allwinner_sramc_write",
    .sstate = TRACE_ALLWINNER_SRAMC_WRITE_ENABLED,
    .dstate = &_TRACE_ALLWINNER_SRAMC_WRITE_DSTATE
};
TraceEvent _TRACE_AVR_POWER_READ_EVENT = {
    .id = 0,
    .name = "avr_power_read",
    .sstate = TRACE_AVR_POWER_READ_ENABLED,
    .dstate = &_TRACE_AVR_POWER_READ_DSTATE
};
TraceEvent _TRACE_AVR_POWER_WRITE_EVENT = {
    .id = 0,
    .name = "avr_power_write",
    .sstate = TRACE_AVR_POWER_WRITE_ENABLED,
    .dstate = &_TRACE_AVR_POWER_WRITE_DSTATE
};
TraceEvent _TRACE_AXP2XX_RX_EVENT = {
    .id = 0,
    .name = "axp2xx_rx",
    .sstate = TRACE_AXP2XX_RX_ENABLED,
    .dstate = &_TRACE_AXP2XX_RX_DSTATE
};
TraceEvent _TRACE_AXP2XX_SELECT_EVENT = {
    .id = 0,
    .name = "axp2xx_select",
    .sstate = TRACE_AXP2XX_SELECT_ENABLED,
    .dstate = &_TRACE_AXP2XX_SELECT_DSTATE
};
TraceEvent _TRACE_AXP2XX_TX_EVENT = {
    .id = 0,
    .name = "axp2xx_tx",
    .sstate = TRACE_AXP2XX_TX_ENABLED,
    .dstate = &_TRACE_AXP2XX_TX_DSTATE
};
TraceEvent _TRACE_ECC_MEM_WRITEL_MER_EVENT = {
    .id = 0,
    .name = "ecc_mem_writel_mer",
    .sstate = TRACE_ECC_MEM_WRITEL_MER_ENABLED,
    .dstate = &_TRACE_ECC_MEM_WRITEL_MER_DSTATE
};
TraceEvent _TRACE_ECC_MEM_WRITEL_MDR_EVENT = {
    .id = 0,
    .name = "ecc_mem_writel_mdr",
    .sstate = TRACE_ECC_MEM_WRITEL_MDR_ENABLED,
    .dstate = &_TRACE_ECC_MEM_WRITEL_MDR_DSTATE
};
TraceEvent _TRACE_ECC_MEM_WRITEL_MFSR_EVENT = {
    .id = 0,
    .name = "ecc_mem_writel_mfsr",
    .sstate = TRACE_ECC_MEM_WRITEL_MFSR_ENABLED,
    .dstate = &_TRACE_ECC_MEM_WRITEL_MFSR_DSTATE
};
TraceEvent _TRACE_ECC_MEM_WRITEL_VCR_EVENT = {
    .id = 0,
    .name = "ecc_mem_writel_vcr",
    .sstate = TRACE_ECC_MEM_WRITEL_VCR_ENABLED,
    .dstate = &_TRACE_ECC_MEM_WRITEL_VCR_DSTATE
};
TraceEvent _TRACE_ECC_MEM_WRITEL_DR_EVENT = {
    .id = 0,
    .name = "ecc_mem_writel_dr",
    .sstate = TRACE_ECC_MEM_WRITEL_DR_ENABLED,
    .dstate = &_TRACE_ECC_MEM_WRITEL_DR_DSTATE
};
TraceEvent _TRACE_ECC_MEM_WRITEL_ECR0_EVENT = {
    .id = 0,
    .name = "ecc_mem_writel_ecr0",
    .sstate = TRACE_ECC_MEM_WRITEL_ECR0_ENABLED,
    .dstate = &_TRACE_ECC_MEM_WRITEL_ECR0_DSTATE
};
TraceEvent _TRACE_ECC_MEM_WRITEL_ECR1_EVENT = {
    .id = 0,
    .name = "ecc_mem_writel_ecr1",
    .sstate = TRACE_ECC_MEM_WRITEL_ECR1_ENABLED,
    .dstate = &_TRACE_ECC_MEM_WRITEL_ECR1_DSTATE
};
TraceEvent _TRACE_ECC_MEM_READL_MER_EVENT = {
    .id = 0,
    .name = "ecc_mem_readl_mer",
    .sstate = TRACE_ECC_MEM_READL_MER_ENABLED,
    .dstate = &_TRACE_ECC_MEM_READL_MER_DSTATE
};
TraceEvent _TRACE_ECC_MEM_READL_MDR_EVENT = {
    .id = 0,
    .name = "ecc_mem_readl_mdr",
    .sstate = TRACE_ECC_MEM_READL_MDR_ENABLED,
    .dstate = &_TRACE_ECC_MEM_READL_MDR_DSTATE
};
TraceEvent _TRACE_ECC_MEM_READL_MFSR_EVENT = {
    .id = 0,
    .name = "ecc_mem_readl_mfsr",
    .sstate = TRACE_ECC_MEM_READL_MFSR_ENABLED,
    .dstate = &_TRACE_ECC_MEM_READL_MFSR_DSTATE
};
TraceEvent _TRACE_ECC_MEM_READL_VCR_EVENT = {
    .id = 0,
    .name = "ecc_mem_readl_vcr",
    .sstate = TRACE_ECC_MEM_READL_VCR_ENABLED,
    .dstate = &_TRACE_ECC_MEM_READL_VCR_DSTATE
};
TraceEvent _TRACE_ECC_MEM_READL_MFAR0_EVENT = {
    .id = 0,
    .name = "ecc_mem_readl_mfar0",
    .sstate = TRACE_ECC_MEM_READL_MFAR0_ENABLED,
    .dstate = &_TRACE_ECC_MEM_READL_MFAR0_DSTATE
};
TraceEvent _TRACE_ECC_MEM_READL_MFAR1_EVENT = {
    .id = 0,
    .name = "ecc_mem_readl_mfar1",
    .sstate = TRACE_ECC_MEM_READL_MFAR1_ENABLED,
    .dstate = &_TRACE_ECC_MEM_READL_MFAR1_DSTATE
};
TraceEvent _TRACE_ECC_MEM_READL_DR_EVENT = {
    .id = 0,
    .name = "ecc_mem_readl_dr",
    .sstate = TRACE_ECC_MEM_READL_DR_ENABLED,
    .dstate = &_TRACE_ECC_MEM_READL_DR_DSTATE
};
TraceEvent _TRACE_ECC_MEM_READL_ECR0_EVENT = {
    .id = 0,
    .name = "ecc_mem_readl_ecr0",
    .sstate = TRACE_ECC_MEM_READL_ECR0_ENABLED,
    .dstate = &_TRACE_ECC_MEM_READL_ECR0_DSTATE
};
TraceEvent _TRACE_ECC_MEM_READL_ECR1_EVENT = {
    .id = 0,
    .name = "ecc_mem_readl_ecr1",
    .sstate = TRACE_ECC_MEM_READL_ECR1_ENABLED,
    .dstate = &_TRACE_ECC_MEM_READL_ECR1_DSTATE
};
TraceEvent _TRACE_ECC_DIAG_MEM_WRITEB_EVENT = {
    .id = 0,
    .name = "ecc_diag_mem_writeb",
    .sstate = TRACE_ECC_DIAG_MEM_WRITEB_ENABLED,
    .dstate = &_TRACE_ECC_DIAG_MEM_WRITEB_DSTATE
};
TraceEvent _TRACE_ECC_DIAG_MEM_READB_EVENT = {
    .id = 0,
    .name = "ecc_diag_mem_readb",
    .sstate = TRACE_ECC_DIAG_MEM_READB_ENABLED,
    .dstate = &_TRACE_ECC_DIAG_MEM_READB_DSTATE
};
TraceEvent _TRACE_EMPTY_SLOT_WRITE_EVENT = {
    .id = 0,
    .name = "empty_slot_write",
    .sstate = TRACE_EMPTY_SLOT_WRITE_ENABLED,
    .dstate = &_TRACE_EMPTY_SLOT_WRITE_DSTATE
};
TraceEvent _TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_EVENT = {
    .id = 0,
    .name = "slavio_misc_update_irq_raise",
    .sstate = TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_ENABLED,
    .dstate = &_TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_DSTATE
};
TraceEvent _TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_EVENT = {
    .id = 0,
    .name = "slavio_misc_update_irq_lower",
    .sstate = TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_ENABLED,
    .dstate = &_TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_DSTATE
};
TraceEvent _TRACE_SLAVIO_SET_POWER_FAIL_EVENT = {
    .id = 0,
    .name = "slavio_set_power_fail",
    .sstate = TRACE_SLAVIO_SET_POWER_FAIL_ENABLED,
    .dstate = &_TRACE_SLAVIO_SET_POWER_FAIL_DSTATE
};
TraceEvent _TRACE_SLAVIO_CFG_MEM_WRITEB_EVENT = {
    .id = 0,
    .name = "slavio_cfg_mem_writeb",
    .sstate = TRACE_SLAVIO_CFG_MEM_WRITEB_ENABLED,
    .dstate = &_TRACE_SLAVIO_CFG_MEM_WRITEB_DSTATE
};
TraceEvent _TRACE_SLAVIO_CFG_MEM_READB_EVENT = {
    .id = 0,
    .name = "slavio_cfg_mem_readb",
    .sstate = TRACE_SLAVIO_CFG_MEM_READB_ENABLED,
    .dstate = &_TRACE_SLAVIO_CFG_MEM_READB_DSTATE
};
TraceEvent _TRACE_SLAVIO_DIAG_MEM_WRITEB_EVENT = {
    .id = 0,
    .name = "slavio_diag_mem_writeb",
    .sstate = TRACE_SLAVIO_DIAG_MEM_WRITEB_ENABLED,
    .dstate = &_TRACE_SLAVIO_DIAG_MEM_WRITEB_DSTATE
};
TraceEvent _TRACE_SLAVIO_DIAG_MEM_READB_EVENT = {
    .id = 0,
    .name = "slavio_diag_mem_readb",
    .sstate = TRACE_SLAVIO_DIAG_MEM_READB_ENABLED,
    .dstate = &_TRACE_SLAVIO_DIAG_MEM_READB_DSTATE
};
TraceEvent _TRACE_SLAVIO_MDM_MEM_WRITEB_EVENT = {
    .id = 0,
    .name = "slavio_mdm_mem_writeb",
    .sstate = TRACE_SLAVIO_MDM_MEM_WRITEB_ENABLED,
    .dstate = &_TRACE_SLAVIO_MDM_MEM_WRITEB_DSTATE
};
TraceEvent _TRACE_SLAVIO_MDM_MEM_READB_EVENT = {
    .id = 0,
    .name = "slavio_mdm_mem_readb",
    .sstate = TRACE_SLAVIO_MDM_MEM_READB_ENABLED,
    .dstate = &_TRACE_SLAVIO_MDM_MEM_READB_DSTATE
};
TraceEvent _TRACE_SLAVIO_AUX1_MEM_WRITEB_EVENT = {
    .id = 0,
    .name = "slavio_aux1_mem_writeb",
    .sstate = TRACE_SLAVIO_AUX1_MEM_WRITEB_ENABLED,
    .dstate = &_TRACE_SLAVIO_AUX1_MEM_WRITEB_DSTATE
};
TraceEvent _TRACE_SLAVIO_AUX1_MEM_READB_EVENT = {
    .id = 0,
    .name = "slavio_aux1_mem_readb",
    .sstate = TRACE_SLAVIO_AUX1_MEM_READB_ENABLED,
    .dstate = &_TRACE_SLAVIO_AUX1_MEM_READB_DSTATE
};
TraceEvent _TRACE_SLAVIO_AUX2_MEM_WRITEB_EVENT = {
    .id = 0,
    .name = "slavio_aux2_mem_writeb",
    .sstate = TRACE_SLAVIO_AUX2_MEM_WRITEB_ENABLED,
    .dstate = &_TRACE_SLAVIO_AUX2_MEM_WRITEB_DSTATE
};
TraceEvent _TRACE_SLAVIO_AUX2_MEM_READB_EVENT = {
    .id = 0,
    .name = "slavio_aux2_mem_readb",
    .sstate = TRACE_SLAVIO_AUX2_MEM_READB_ENABLED,
    .dstate = &_TRACE_SLAVIO_AUX2_MEM_READB_DSTATE
};
TraceEvent _TRACE_APC_MEM_WRITEB_EVENT = {
    .id = 0,
    .name = "apc_mem_writeb",
    .sstate = TRACE_APC_MEM_WRITEB_ENABLED,
    .dstate = &_TRACE_APC_MEM_WRITEB_DSTATE
};
TraceEvent _TRACE_APC_MEM_READB_EVENT = {
    .id = 0,
    .name = "apc_mem_readb",
    .sstate = TRACE_APC_MEM_READB_ENABLED,
    .dstate = &_TRACE_APC_MEM_READB_DSTATE
};
TraceEvent _TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_EVENT = {
    .id = 0,
    .name = "slavio_sysctrl_mem_writel",
    .sstate = TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_ENABLED,
    .dstate = &_TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_DSTATE
};
TraceEvent _TRACE_SLAVIO_SYSCTRL_MEM_READL_EVENT = {
    .id = 0,
    .name = "slavio_sysctrl_mem_readl",
    .sstate = TRACE_SLAVIO_SYSCTRL_MEM_READL_ENABLED,
    .dstate = &_TRACE_SLAVIO_SYSCTRL_MEM_READL_DSTATE
};
TraceEvent _TRACE_SLAVIO_LED_MEM_WRITEW_EVENT = {
    .id = 0,
    .name = "slavio_led_mem_writew",
    .sstate = TRACE_SLAVIO_LED_MEM_WRITEW_ENABLED,
    .dstate = &_TRACE_SLAVIO_LED_MEM_WRITEW_DSTATE
};
TraceEvent _TRACE_SLAVIO_LED_MEM_READW_EVENT = {
    .id = 0,
    .name = "slavio_led_mem_readw",
    .sstate = TRACE_SLAVIO_LED_MEM_READW_ENABLED,
    .dstate = &_TRACE_SLAVIO_LED_MEM_READW_DSTATE
};
TraceEvent _TRACE_ASPEED_SBC_IGNORE_CMD_EVENT = {
    .id = 0,
    .name = "aspeed_sbc_ignore_cmd",
    .sstate = TRACE_ASPEED_SBC_IGNORE_CMD_ENABLED,
    .dstate = &_TRACE_ASPEED_SBC_IGNORE_CMD_DSTATE
};
TraceEvent _TRACE_ASPEED_SBC_HANDLE_CMD_EVENT = {
    .id = 0,
    .name = "aspeed_sbc_handle_cmd",
    .sstate = TRACE_ASPEED_SBC_HANDLE_CMD_ENABLED,
    .dstate = &_TRACE_ASPEED_SBC_HANDLE_CMD_DSTATE
};
TraceEvent _TRACE_ASPEED_SBC_OTP_READ_EVENT = {
    .id = 0,
    .name = "aspeed_sbc_otp_read",
    .sstate = TRACE_ASPEED_SBC_OTP_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_SBC_OTP_READ_DSTATE
};
TraceEvent _TRACE_ASPEED_SBC_OTP_PROG_EVENT = {
    .id = 0,
    .name = "aspeed_sbc_otp_prog",
    .sstate = TRACE_ASPEED_SBC_OTP_PROG_ENABLED,
    .dstate = &_TRACE_ASPEED_SBC_OTP_PROG_DSTATE
};
TraceEvent _TRACE_ASPEED_SCU_WRITE_EVENT = {
    .id = 0,
    .name = "aspeed_scu_write",
    .sstate = TRACE_ASPEED_SCU_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_SCU_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_SCU_READ_EVENT = {
    .id = 0,
    .name = "aspeed_scu_read",
    .sstate = TRACE_ASPEED_SCU_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_SCU_READ_DSTATE
};
TraceEvent _TRACE_ASPEED_AST2700_SCU_WRITE_EVENT = {
    .id = 0,
    .name = "aspeed_ast2700_scu_write",
    .sstate = TRACE_ASPEED_AST2700_SCU_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_AST2700_SCU_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_AST2700_SCU_READ_EVENT = {
    .id = 0,
    .name = "aspeed_ast2700_scu_read",
    .sstate = TRACE_ASPEED_AST2700_SCU_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_AST2700_SCU_READ_DSTATE
};
TraceEvent _TRACE_ASPEED_AST2700_SCUIO_WRITE_EVENT = {
    .id = 0,
    .name = "aspeed_ast2700_scuio_write",
    .sstate = TRACE_ASPEED_AST2700_SCUIO_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_AST2700_SCUIO_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_AST2700_SCUIO_READ_EVENT = {
    .id = 0,
    .name = "aspeed_ast2700_scuio_read",
    .sstate = TRACE_ASPEED_AST2700_SCUIO_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_AST2700_SCUIO_READ_DSTATE
};
TraceEvent _TRACE_MPS2_SCC_READ_EVENT = {
    .id = 0,
    .name = "mps2_scc_read",
    .sstate = TRACE_MPS2_SCC_READ_ENABLED,
    .dstate = &_TRACE_MPS2_SCC_READ_DSTATE
};
TraceEvent _TRACE_MPS2_SCC_WRITE_EVENT = {
    .id = 0,
    .name = "mps2_scc_write",
    .sstate = TRACE_MPS2_SCC_WRITE_ENABLED,
    .dstate = &_TRACE_MPS2_SCC_WRITE_DSTATE
};
TraceEvent _TRACE_MPS2_SCC_RESET_EVENT = {
    .id = 0,
    .name = "mps2_scc_reset",
    .sstate = TRACE_MPS2_SCC_RESET_ENABLED,
    .dstate = &_TRACE_MPS2_SCC_RESET_DSTATE
};
TraceEvent _TRACE_MPS2_SCC_CFG_WRITE_EVENT = {
    .id = 0,
    .name = "mps2_scc_cfg_write",
    .sstate = TRACE_MPS2_SCC_CFG_WRITE_ENABLED,
    .dstate = &_TRACE_MPS2_SCC_CFG_WRITE_DSTATE
};
TraceEvent _TRACE_MPS2_SCC_CFG_READ_EVENT = {
    .id = 0,
    .name = "mps2_scc_cfg_read",
    .sstate = TRACE_MPS2_SCC_CFG_READ_ENABLED,
    .dstate = &_TRACE_MPS2_SCC_CFG_READ_DSTATE
};
TraceEvent _TRACE_MPS2_FPGAIO_READ_EVENT = {
    .id = 0,
    .name = "mps2_fpgaio_read",
    .sstate = TRACE_MPS2_FPGAIO_READ_ENABLED,
    .dstate = &_TRACE_MPS2_FPGAIO_READ_DSTATE
};
TraceEvent _TRACE_MPS2_FPGAIO_WRITE_EVENT = {
    .id = 0,
    .name = "mps2_fpgaio_write",
    .sstate = TRACE_MPS2_FPGAIO_WRITE_ENABLED,
    .dstate = &_TRACE_MPS2_FPGAIO_WRITE_DSTATE
};
TraceEvent _TRACE_MPS2_FPGAIO_RESET_EVENT = {
    .id = 0,
    .name = "mps2_fpgaio_reset",
    .sstate = TRACE_MPS2_FPGAIO_RESET_ENABLED,
    .dstate = &_TRACE_MPS2_FPGAIO_RESET_DSTATE
};
TraceEvent _TRACE_MSF2_SYSREG_WRITE_EVENT = {
    .id = 0,
    .name = "msf2_sysreg_write",
    .sstate = TRACE_MSF2_SYSREG_WRITE_ENABLED,
    .dstate = &_TRACE_MSF2_SYSREG_WRITE_DSTATE
};
TraceEvent _TRACE_MSF2_SYSREG_READ_EVENT = {
    .id = 0,
    .name = "msf2_sysreg_read",
    .sstate = TRACE_MSF2_SYSREG_READ_ENABLED,
    .dstate = &_TRACE_MSF2_SYSREG_READ_DSTATE
};
TraceEvent _TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_EVENT = {
    .id = 0,
    .name = "msf2_sysreg_write_pll_status",
    .sstate = TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_ENABLED,
    .dstate = &_TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_DSTATE
};
TraceEvent _TRACE_IMX7_GPR_READ_EVENT = {
    .id = 0,
    .name = "imx7_gpr_read",
    .sstate = TRACE_IMX7_GPR_READ_ENABLED,
    .dstate = &_TRACE_IMX7_GPR_READ_DSTATE
};
TraceEvent _TRACE_IMX7_GPR_WRITE_EVENT = {
    .id = 0,
    .name = "imx7_gpr_write",
    .sstate = TRACE_IMX7_GPR_WRITE_ENABLED,
    .dstate = &_TRACE_IMX7_GPR_WRITE_DSTATE
};
TraceEvent _TRACE_IMX7_SNVS_READ_EVENT = {
    .id = 0,
    .name = "imx7_snvs_read",
    .sstate = TRACE_IMX7_SNVS_READ_ENABLED,
    .dstate = &_TRACE_IMX7_SNVS_READ_DSTATE
};
TraceEvent _TRACE_IMX7_SNVS_WRITE_EVENT = {
    .id = 0,
    .name = "imx7_snvs_write",
    .sstate = TRACE_IMX7_SNVS_WRITE_ENABLED,
    .dstate = &_TRACE_IMX7_SNVS_WRITE_DSTATE
};
TraceEvent _TRACE_MOS6522_SET_COUNTER_EVENT = {
    .id = 0,
    .name = "mos6522_set_counter",
    .sstate = TRACE_MOS6522_SET_COUNTER_ENABLED,
    .dstate = &_TRACE_MOS6522_SET_COUNTER_DSTATE
};
TraceEvent _TRACE_MOS6522_GET_NEXT_IRQ_TIME_EVENT = {
    .id = 0,
    .name = "mos6522_get_next_irq_time",
    .sstate = TRACE_MOS6522_GET_NEXT_IRQ_TIME_ENABLED,
    .dstate = &_TRACE_MOS6522_GET_NEXT_IRQ_TIME_DSTATE
};
TraceEvent _TRACE_MOS6522_SET_SR_INT_EVENT = {
    .id = 0,
    .name = "mos6522_set_sr_int",
    .sstate = TRACE_MOS6522_SET_SR_INT_ENABLED,
    .dstate = &_TRACE_MOS6522_SET_SR_INT_DSTATE
};
TraceEvent _TRACE_MOS6522_WRITE_EVENT = {
    .id = 0,
    .name = "mos6522_write",
    .sstate = TRACE_MOS6522_WRITE_ENABLED,
    .dstate = &_TRACE_MOS6522_WRITE_DSTATE
};
TraceEvent _TRACE_MOS6522_READ_EVENT = {
    .id = 0,
    .name = "mos6522_read",
    .sstate = TRACE_MOS6522_READ_ENABLED,
    .dstate = &_TRACE_MOS6522_READ_DSTATE
};
TraceEvent _TRACE_NPCM_CLK_READ_EVENT = {
    .id = 0,
    .name = "npcm_clk_read",
    .sstate = TRACE_NPCM_CLK_READ_ENABLED,
    .dstate = &_TRACE_NPCM_CLK_READ_DSTATE
};
TraceEvent _TRACE_NPCM_CLK_WRITE_EVENT = {
    .id = 0,
    .name = "npcm_clk_write",
    .sstate = TRACE_NPCM_CLK_WRITE_ENABLED,
    .dstate = &_TRACE_NPCM_CLK_WRITE_DSTATE
};
TraceEvent _TRACE_NPCM_GCR_READ_EVENT = {
    .id = 0,
    .name = "npcm_gcr_read",
    .sstate = TRACE_NPCM_GCR_READ_ENABLED,
    .dstate = &_TRACE_NPCM_GCR_READ_DSTATE
};
TraceEvent _TRACE_NPCM_GCR_WRITE_EVENT = {
    .id = 0,
    .name = "npcm_gcr_write",
    .sstate = TRACE_NPCM_GCR_WRITE_ENABLED,
    .dstate = &_TRACE_NPCM_GCR_WRITE_DSTATE
};
TraceEvent _TRACE_NPCM7XX_MFT_READ_EVENT = {
    .id = 0,
    .name = "npcm7xx_mft_read",
    .sstate = TRACE_NPCM7XX_MFT_READ_ENABLED,
    .dstate = &_TRACE_NPCM7XX_MFT_READ_DSTATE
};
TraceEvent _TRACE_NPCM7XX_MFT_WRITE_EVENT = {
    .id = 0,
    .name = "npcm7xx_mft_write",
    .sstate = TRACE_NPCM7XX_MFT_WRITE_ENABLED,
    .dstate = &_TRACE_NPCM7XX_MFT_WRITE_DSTATE
};
TraceEvent _TRACE_NPCM7XX_MFT_RPM_EVENT = {
    .id = 0,
    .name = "npcm7xx_mft_rpm",
    .sstate = TRACE_NPCM7XX_MFT_RPM_ENABLED,
    .dstate = &_TRACE_NPCM7XX_MFT_RPM_DSTATE
};
TraceEvent _TRACE_NPCM7XX_MFT_CAPTURE_EVENT = {
    .id = 0,
    .name = "npcm7xx_mft_capture",
    .sstate = TRACE_NPCM7XX_MFT_CAPTURE_ENABLED,
    .dstate = &_TRACE_NPCM7XX_MFT_CAPTURE_DSTATE
};
TraceEvent _TRACE_NPCM7XX_MFT_UPDATE_CLOCK_EVENT = {
    .id = 0,
    .name = "npcm7xx_mft_update_clock",
    .sstate = TRACE_NPCM7XX_MFT_UPDATE_CLOCK_ENABLED,
    .dstate = &_TRACE_NPCM7XX_MFT_UPDATE_CLOCK_DSTATE
};
TraceEvent _TRACE_NPCM7XX_MFT_SET_DUTY_EVENT = {
    .id = 0,
    .name = "npcm7xx_mft_set_duty",
    .sstate = TRACE_NPCM7XX_MFT_SET_DUTY_ENABLED,
    .dstate = &_TRACE_NPCM7XX_MFT_SET_DUTY_DSTATE
};
TraceEvent _TRACE_NPCM7XX_RNG_READ_EVENT = {
    .id = 0,
    .name = "npcm7xx_rng_read",
    .sstate = TRACE_NPCM7XX_RNG_READ_ENABLED,
    .dstate = &_TRACE_NPCM7XX_RNG_READ_DSTATE
};
TraceEvent _TRACE_NPCM7XX_RNG_WRITE_EVENT = {
    .id = 0,
    .name = "npcm7xx_rng_write",
    .sstate = TRACE_NPCM7XX_RNG_WRITE_ENABLED,
    .dstate = &_TRACE_NPCM7XX_RNG_WRITE_DSTATE
};
TraceEvent _TRACE_NPCM7XX_PWM_READ_EVENT = {
    .id = 0,
    .name = "npcm7xx_pwm_read",
    .sstate = TRACE_NPCM7XX_PWM_READ_ENABLED,
    .dstate = &_TRACE_NPCM7XX_PWM_READ_DSTATE
};
TraceEvent _TRACE_NPCM7XX_PWM_WRITE_EVENT = {
    .id = 0,
    .name = "npcm7xx_pwm_write",
    .sstate = TRACE_NPCM7XX_PWM_WRITE_ENABLED,
    .dstate = &_TRACE_NPCM7XX_PWM_WRITE_DSTATE
};
TraceEvent _TRACE_NPCM7XX_PWM_UPDATE_FREQ_EVENT = {
    .id = 0,
    .name = "npcm7xx_pwm_update_freq",
    .sstate = TRACE_NPCM7XX_PWM_UPDATE_FREQ_ENABLED,
    .dstate = &_TRACE_NPCM7XX_PWM_UPDATE_FREQ_DSTATE
};
TraceEvent _TRACE_NPCM7XX_PWM_UPDATE_DUTY_EVENT = {
    .id = 0,
    .name = "npcm7xx_pwm_update_duty",
    .sstate = TRACE_NPCM7XX_PWM_UPDATE_DUTY_ENABLED,
    .dstate = &_TRACE_NPCM7XX_PWM_UPDATE_DUTY_DSTATE
};
TraceEvent _TRACE_STM32_RCC_READ_EVENT = {
    .id = 0,
    .name = "stm32_rcc_read",
    .sstate = TRACE_STM32_RCC_READ_ENABLED,
    .dstate = &_TRACE_STM32_RCC_READ_DSTATE
};
TraceEvent _TRACE_STM32_RCC_WRITE_EVENT = {
    .id = 0,
    .name = "stm32_rcc_write",
    .sstate = TRACE_STM32_RCC_WRITE_ENABLED,
    .dstate = &_TRACE_STM32_RCC_WRITE_DSTATE
};
TraceEvent _TRACE_STM32_RCC_PULSE_ENABLE_EVENT = {
    .id = 0,
    .name = "stm32_rcc_pulse_enable",
    .sstate = TRACE_STM32_RCC_PULSE_ENABLE_ENABLED,
    .dstate = &_TRACE_STM32_RCC_PULSE_ENABLE_DSTATE
};
TraceEvent _TRACE_STM32_RCC_PULSE_RESET_EVENT = {
    .id = 0,
    .name = "stm32_rcc_pulse_reset",
    .sstate = TRACE_STM32_RCC_PULSE_RESET_ENABLED,
    .dstate = &_TRACE_STM32_RCC_PULSE_RESET_DSTATE
};
TraceEvent _TRACE_STM32F4XX_SYSCFG_SET_IRQ_EVENT = {
    .id = 0,
    .name = "stm32f4xx_syscfg_set_irq",
    .sstate = TRACE_STM32F4XX_SYSCFG_SET_IRQ_ENABLED,
    .dstate = &_TRACE_STM32F4XX_SYSCFG_SET_IRQ_DSTATE
};
TraceEvent _TRACE_STM32F4XX_PULSE_EXTI_EVENT = {
    .id = 0,
    .name = "stm32f4xx_pulse_exti",
    .sstate = TRACE_STM32F4XX_PULSE_EXTI_ENABLED,
    .dstate = &_TRACE_STM32F4XX_PULSE_EXTI_DSTATE
};
TraceEvent _TRACE_STM32F4XX_SYSCFG_READ_EVENT = {
    .id = 0,
    .name = "stm32f4xx_syscfg_read",
    .sstate = TRACE_STM32F4XX_SYSCFG_READ_ENABLED,
    .dstate = &_TRACE_STM32F4XX_SYSCFG_READ_DSTATE
};
TraceEvent _TRACE_STM32F4XX_SYSCFG_WRITE_EVENT = {
    .id = 0,
    .name = "stm32f4xx_syscfg_write",
    .sstate = TRACE_STM32F4XX_SYSCFG_WRITE_ENABLED,
    .dstate = &_TRACE_STM32F4XX_SYSCFG_WRITE_DSTATE
};
TraceEvent _TRACE_STM32F4XX_EXTI_SET_IRQ_EVENT = {
    .id = 0,
    .name = "stm32f4xx_exti_set_irq",
    .sstate = TRACE_STM32F4XX_EXTI_SET_IRQ_ENABLED,
    .dstate = &_TRACE_STM32F4XX_EXTI_SET_IRQ_DSTATE
};
TraceEvent _TRACE_STM32F4XX_EXTI_READ_EVENT = {
    .id = 0,
    .name = "stm32f4xx_exti_read",
    .sstate = TRACE_STM32F4XX_EXTI_READ_ENABLED,
    .dstate = &_TRACE_STM32F4XX_EXTI_READ_DSTATE
};
TraceEvent _TRACE_STM32F4XX_EXTI_WRITE_EVENT = {
    .id = 0,
    .name = "stm32f4xx_exti_write",
    .sstate = TRACE_STM32F4XX_EXTI_WRITE_ENABLED,
    .dstate = &_TRACE_STM32F4XX_EXTI_WRITE_DSTATE
};
TraceEvent _TRACE_STM32L4X5_SYSCFG_SET_IRQ_EVENT = {
    .id = 0,
    .name = "stm32l4x5_syscfg_set_irq",
    .sstate = TRACE_STM32L4X5_SYSCFG_SET_IRQ_ENABLED,
    .dstate = &_TRACE_STM32L4X5_SYSCFG_SET_IRQ_DSTATE
};
TraceEvent _TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_EVENT = {
    .id = 0,
    .name = "stm32l4x5_syscfg_forward_exti",
    .sstate = TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_ENABLED,
    .dstate = &_TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_DSTATE
};
TraceEvent _TRACE_STM32L4X5_SYSCFG_READ_EVENT = {
    .id = 0,
    .name = "stm32l4x5_syscfg_read",
    .sstate = TRACE_STM32L4X5_SYSCFG_READ_ENABLED,
    .dstate = &_TRACE_STM32L4X5_SYSCFG_READ_DSTATE
};
TraceEvent _TRACE_STM32L4X5_SYSCFG_WRITE_EVENT = {
    .id = 0,
    .name = "stm32l4x5_syscfg_write",
    .sstate = TRACE_STM32L4X5_SYSCFG_WRITE_ENABLED,
    .dstate = &_TRACE_STM32L4X5_SYSCFG_WRITE_DSTATE
};
TraceEvent _TRACE_STM32L4X5_EXTI_SET_IRQ_EVENT = {
    .id = 0,
    .name = "stm32l4x5_exti_set_irq",
    .sstate = TRACE_STM32L4X5_EXTI_SET_IRQ_ENABLED,
    .dstate = &_TRACE_STM32L4X5_EXTI_SET_IRQ_DSTATE
};
TraceEvent _TRACE_STM32L4X5_EXTI_READ_EVENT = {
    .id = 0,
    .name = "stm32l4x5_exti_read",
    .sstate = TRACE_STM32L4X5_EXTI_READ_ENABLED,
    .dstate = &_TRACE_STM32L4X5_EXTI_READ_DSTATE
};
TraceEvent _TRACE_STM32L4X5_EXTI_WRITE_EVENT = {
    .id = 0,
    .name = "stm32l4x5_exti_write",
    .sstate = TRACE_STM32L4X5_EXTI_WRITE_ENABLED,
    .dstate = &_TRACE_STM32L4X5_EXTI_WRITE_DSTATE
};
TraceEvent _TRACE_STM32L4X5_RCC_READ_EVENT = {
    .id = 0,
    .name = "stm32l4x5_rcc_read",
    .sstate = TRACE_STM32L4X5_RCC_READ_ENABLED,
    .dstate = &_TRACE_STM32L4X5_RCC_READ_DSTATE
};
TraceEvent _TRACE_STM32L4X5_RCC_WRITE_EVENT = {
    .id = 0,
    .name = "stm32l4x5_rcc_write",
    .sstate = TRACE_STM32L4X5_RCC_WRITE_ENABLED,
    .dstate = &_TRACE_STM32L4X5_RCC_WRITE_DSTATE
};
TraceEvent _TRACE_STM32L4X5_RCC_MUX_ENABLE_EVENT = {
    .id = 0,
    .name = "stm32l4x5_rcc_mux_enable",
    .sstate = TRACE_STM32L4X5_RCC_MUX_ENABLE_ENABLED,
    .dstate = &_TRACE_STM32L4X5_RCC_MUX_ENABLE_DSTATE
};
TraceEvent _TRACE_STM32L4X5_RCC_MUX_DISABLE_EVENT = {
    .id = 0,
    .name = "stm32l4x5_rcc_mux_disable",
    .sstate = TRACE_STM32L4X5_RCC_MUX_DISABLE_ENABLED,
    .dstate = &_TRACE_STM32L4X5_RCC_MUX_DISABLE_DSTATE
};
TraceEvent _TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_EVENT = {
    .id = 0,
    .name = "stm32l4x5_rcc_mux_set_factor",
    .sstate = TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_ENABLED,
    .dstate = &_TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_DSTATE
};
TraceEvent _TRACE_STM32L4X5_RCC_MUX_SET_SRC_EVENT = {
    .id = 0,
    .name = "stm32l4x5_rcc_mux_set_src",
    .sstate = TRACE_STM32L4X5_RCC_MUX_SET_SRC_ENABLED,
    .dstate = &_TRACE_STM32L4X5_RCC_MUX_SET_SRC_DSTATE
};
TraceEvent _TRACE_STM32L4X5_RCC_MUX_UPDATE_EVENT = {
    .id = 0,
    .name = "stm32l4x5_rcc_mux_update",
    .sstate = TRACE_STM32L4X5_RCC_MUX_UPDATE_ENABLED,
    .dstate = &_TRACE_STM32L4X5_RCC_MUX_UPDATE_DSTATE
};
TraceEvent _TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_EVENT = {
    .id = 0,
    .name = "stm32l4x5_rcc_pll_set_vco_multiplier",
    .sstate = TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_ENABLED,
    .dstate = &_TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_DSTATE
};
TraceEvent _TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_EVENT = {
    .id = 0,
    .name = "stm32l4x5_rcc_pll_channel_enable",
    .sstate = TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_ENABLED,
    .dstate = &_TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_DSTATE
};
TraceEvent _TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_EVENT = {
    .id = 0,
    .name = "stm32l4x5_rcc_pll_channel_disable",
    .sstate = TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_ENABLED,
    .dstate = &_TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_DSTATE
};
TraceEvent _TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_EVENT = {
    .id = 0,
    .name = "stm32l4x5_rcc_pll_set_channel_divider",
    .sstate = TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_ENABLED,
    .dstate = &_TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_DSTATE
};
TraceEvent _TRACE_STM32L4X5_RCC_PLL_UPDATE_EVENT = {
    .id = 0,
    .name = "stm32l4x5_rcc_pll_update",
    .sstate = TRACE_STM32L4X5_RCC_PLL_UPDATE_ENABLED,
    .dstate = &_TRACE_STM32L4X5_RCC_PLL_UPDATE_DSTATE
};
TraceEvent _TRACE_TZ_MPC_REG_READ_EVENT = {
    .id = 0,
    .name = "tz_mpc_reg_read",
    .sstate = TRACE_TZ_MPC_REG_READ_ENABLED,
    .dstate = &_TRACE_TZ_MPC_REG_READ_DSTATE
};
TraceEvent _TRACE_TZ_MPC_REG_WRITE_EVENT = {
    .id = 0,
    .name = "tz_mpc_reg_write",
    .sstate = TRACE_TZ_MPC_REG_WRITE_ENABLED,
    .dstate = &_TRACE_TZ_MPC_REG_WRITE_DSTATE
};
TraceEvent _TRACE_TZ_MPC_MEM_BLOCKED_READ_EVENT = {
    .id = 0,
    .name = "tz_mpc_mem_blocked_read",
    .sstate = TRACE_TZ_MPC_MEM_BLOCKED_READ_ENABLED,
    .dstate = &_TRACE_TZ_MPC_MEM_BLOCKED_READ_DSTATE
};
TraceEvent _TRACE_TZ_MPC_MEM_BLOCKED_WRITE_EVENT = {
    .id = 0,
    .name = "tz_mpc_mem_blocked_write",
    .sstate = TRACE_TZ_MPC_MEM_BLOCKED_WRITE_ENABLED,
    .dstate = &_TRACE_TZ_MPC_MEM_BLOCKED_WRITE_DSTATE
};
TraceEvent _TRACE_TZ_MPC_TRANSLATE_EVENT = {
    .id = 0,
    .name = "tz_mpc_translate",
    .sstate = TRACE_TZ_MPC_TRANSLATE_ENABLED,
    .dstate = &_TRACE_TZ_MPC_TRANSLATE_DSTATE
};
TraceEvent _TRACE_TZ_MPC_IOMMU_NOTIFY_EVENT = {
    .id = 0,
    .name = "tz_mpc_iommu_notify",
    .sstate = TRACE_TZ_MPC_IOMMU_NOTIFY_ENABLED,
    .dstate = &_TRACE_TZ_MPC_IOMMU_NOTIFY_DSTATE
};
TraceEvent _TRACE_TZ_MSC_RESET_EVENT = {
    .id = 0,
    .name = "tz_msc_reset",
    .sstate = TRACE_TZ_MSC_RESET_ENABLED,
    .dstate = &_TRACE_TZ_MSC_RESET_DSTATE
};
TraceEvent _TRACE_TZ_MSC_CFG_NONSEC_EVENT = {
    .id = 0,
    .name = "tz_msc_cfg_nonsec",
    .sstate = TRACE_TZ_MSC_CFG_NONSEC_ENABLED,
    .dstate = &_TRACE_TZ_MSC_CFG_NONSEC_DSTATE
};
TraceEvent _TRACE_TZ_MSC_CFG_SEC_RESP_EVENT = {
    .id = 0,
    .name = "tz_msc_cfg_sec_resp",
    .sstate = TRACE_TZ_MSC_CFG_SEC_RESP_ENABLED,
    .dstate = &_TRACE_TZ_MSC_CFG_SEC_RESP_DSTATE
};
TraceEvent _TRACE_TZ_MSC_IRQ_CLEAR_EVENT = {
    .id = 0,
    .name = "tz_msc_irq_clear",
    .sstate = TRACE_TZ_MSC_IRQ_CLEAR_ENABLED,
    .dstate = &_TRACE_TZ_MSC_IRQ_CLEAR_DSTATE
};
TraceEvent _TRACE_TZ_MSC_UPDATE_IRQ_EVENT = {
    .id = 0,
    .name = "tz_msc_update_irq",
    .sstate = TRACE_TZ_MSC_UPDATE_IRQ_ENABLED,
    .dstate = &_TRACE_TZ_MSC_UPDATE_IRQ_DSTATE
};
TraceEvent _TRACE_TZ_MSC_ACCESS_BLOCKED_EVENT = {
    .id = 0,
    .name = "tz_msc_access_blocked",
    .sstate = TRACE_TZ_MSC_ACCESS_BLOCKED_ENABLED,
    .dstate = &_TRACE_TZ_MSC_ACCESS_BLOCKED_DSTATE
};
TraceEvent _TRACE_TZ_PPC_RESET_EVENT = {
    .id = 0,
    .name = "tz_ppc_reset",
    .sstate = TRACE_TZ_PPC_RESET_ENABLED,
    .dstate = &_TRACE_TZ_PPC_RESET_DSTATE
};
TraceEvent _TRACE_TZ_PPC_CFG_NONSEC_EVENT = {
    .id = 0,
    .name = "tz_ppc_cfg_nonsec",
    .sstate = TRACE_TZ_PPC_CFG_NONSEC_ENABLED,
    .dstate = &_TRACE_TZ_PPC_CFG_NONSEC_DSTATE
};
TraceEvent _TRACE_TZ_PPC_CFG_AP_EVENT = {
    .id = 0,
    .name = "tz_ppc_cfg_ap",
    .sstate = TRACE_TZ_PPC_CFG_AP_ENABLED,
    .dstate = &_TRACE_TZ_PPC_CFG_AP_DSTATE
};
TraceEvent _TRACE_TZ_PPC_CFG_SEC_RESP_EVENT = {
    .id = 0,
    .name = "tz_ppc_cfg_sec_resp",
    .sstate = TRACE_TZ_PPC_CFG_SEC_RESP_ENABLED,
    .dstate = &_TRACE_TZ_PPC_CFG_SEC_RESP_DSTATE
};
TraceEvent _TRACE_TZ_PPC_IRQ_ENABLE_EVENT = {
    .id = 0,
    .name = "tz_ppc_irq_enable",
    .sstate = TRACE_TZ_PPC_IRQ_ENABLE_ENABLED,
    .dstate = &_TRACE_TZ_PPC_IRQ_ENABLE_DSTATE
};
TraceEvent _TRACE_TZ_PPC_IRQ_CLEAR_EVENT = {
    .id = 0,
    .name = "tz_ppc_irq_clear",
    .sstate = TRACE_TZ_PPC_IRQ_CLEAR_ENABLED,
    .dstate = &_TRACE_TZ_PPC_IRQ_CLEAR_DSTATE
};
TraceEvent _TRACE_TZ_PPC_UPDATE_IRQ_EVENT = {
    .id = 0,
    .name = "tz_ppc_update_irq",
    .sstate = TRACE_TZ_PPC_UPDATE_IRQ_ENABLED,
    .dstate = &_TRACE_TZ_PPC_UPDATE_IRQ_DSTATE
};
TraceEvent _TRACE_TZ_PPC_READ_BLOCKED_EVENT = {
    .id = 0,
    .name = "tz_ppc_read_blocked",
    .sstate = TRACE_TZ_PPC_READ_BLOCKED_ENABLED,
    .dstate = &_TRACE_TZ_PPC_READ_BLOCKED_DSTATE
};
TraceEvent _TRACE_TZ_PPC_WRITE_BLOCKED_EVENT = {
    .id = 0,
    .name = "tz_ppc_write_blocked",
    .sstate = TRACE_TZ_PPC_WRITE_BLOCKED_ENABLED,
    .dstate = &_TRACE_TZ_PPC_WRITE_BLOCKED_DSTATE
};
TraceEvent _TRACE_IOTKIT_SECCTL_S_READ_EVENT = {
    .id = 0,
    .name = "iotkit_secctl_s_read",
    .sstate = TRACE_IOTKIT_SECCTL_S_READ_ENABLED,
    .dstate = &_TRACE_IOTKIT_SECCTL_S_READ_DSTATE
};
TraceEvent _TRACE_IOTKIT_SECCTL_S_WRITE_EVENT = {
    .id = 0,
    .name = "iotkit_secctl_s_write",
    .sstate = TRACE_IOTKIT_SECCTL_S_WRITE_ENABLED,
    .dstate = &_TRACE_IOTKIT_SECCTL_S_WRITE_DSTATE
};
TraceEvent _TRACE_IOTKIT_SECCTL_NS_READ_EVENT = {
    .id = 0,
    .name = "iotkit_secctl_ns_read",
    .sstate = TRACE_IOTKIT_SECCTL_NS_READ_ENABLED,
    .dstate = &_TRACE_IOTKIT_SECCTL_NS_READ_DSTATE
};
TraceEvent _TRACE_IOTKIT_SECCTL_NS_WRITE_EVENT = {
    .id = 0,
    .name = "iotkit_secctl_ns_write",
    .sstate = TRACE_IOTKIT_SECCTL_NS_WRITE_ENABLED,
    .dstate = &_TRACE_IOTKIT_SECCTL_NS_WRITE_DSTATE
};
TraceEvent _TRACE_IMX6_ANALOG_GET_PERIPH_CLK_EVENT = {
    .id = 0,
    .name = "imx6_analog_get_periph_clk",
    .sstate = TRACE_IMX6_ANALOG_GET_PERIPH_CLK_ENABLED,
    .dstate = &_TRACE_IMX6_ANALOG_GET_PERIPH_CLK_DSTATE
};
TraceEvent _TRACE_IMX6_ANALOG_GET_PLL2_CLK_EVENT = {
    .id = 0,
    .name = "imx6_analog_get_pll2_clk",
    .sstate = TRACE_IMX6_ANALOG_GET_PLL2_CLK_ENABLED,
    .dstate = &_TRACE_IMX6_ANALOG_GET_PLL2_CLK_DSTATE
};
TraceEvent _TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_EVENT = {
    .id = 0,
    .name = "imx6_analog_get_pll2_pfd0_clk",
    .sstate = TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_ENABLED,
    .dstate = &_TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_DSTATE
};
TraceEvent _TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_EVENT = {
    .id = 0,
    .name = "imx6_analog_get_pll2_pfd2_clk",
    .sstate = TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_ENABLED,
    .dstate = &_TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_DSTATE
};
TraceEvent _TRACE_IMX6_ANALOG_READ_EVENT = {
    .id = 0,
    .name = "imx6_analog_read",
    .sstate = TRACE_IMX6_ANALOG_READ_ENABLED,
    .dstate = &_TRACE_IMX6_ANALOG_READ_DSTATE
};
TraceEvent _TRACE_IMX6_ANALOG_WRITE_EVENT = {
    .id = 0,
    .name = "imx6_analog_write",
    .sstate = TRACE_IMX6_ANALOG_WRITE_ENABLED,
    .dstate = &_TRACE_IMX6_ANALOG_WRITE_DSTATE
};
TraceEvent _TRACE_IMX6_CCM_GET_AHB_CLK_EVENT = {
    .id = 0,
    .name = "imx6_ccm_get_ahb_clk",
    .sstate = TRACE_IMX6_CCM_GET_AHB_CLK_ENABLED,
    .dstate = &_TRACE_IMX6_CCM_GET_AHB_CLK_DSTATE
};
TraceEvent _TRACE_IMX6_CCM_GET_IPG_CLK_EVENT = {
    .id = 0,
    .name = "imx6_ccm_get_ipg_clk",
    .sstate = TRACE_IMX6_CCM_GET_IPG_CLK_ENABLED,
    .dstate = &_TRACE_IMX6_CCM_GET_IPG_CLK_DSTATE
};
TraceEvent _TRACE_IMX6_CCM_GET_PER_CLK_EVENT = {
    .id = 0,
    .name = "imx6_ccm_get_per_clk",
    .sstate = TRACE_IMX6_CCM_GET_PER_CLK_ENABLED,
    .dstate = &_TRACE_IMX6_CCM_GET_PER_CLK_DSTATE
};
TraceEvent _TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_EVENT = {
    .id = 0,
    .name = "imx6_ccm_get_clock_frequency",
    .sstate = TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_ENABLED,
    .dstate = &_TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_DSTATE
};
TraceEvent _TRACE_IMX6_CCM_READ_EVENT = {
    .id = 0,
    .name = "imx6_ccm_read",
    .sstate = TRACE_IMX6_CCM_READ_ENABLED,
    .dstate = &_TRACE_IMX6_CCM_READ_DSTATE
};
TraceEvent _TRACE_IMX6_CCM_RESET_EVENT = {
    .id = 0,
    .name = "imx6_ccm_reset",
    .sstate = TRACE_IMX6_CCM_RESET_ENABLED,
    .dstate = &_TRACE_IMX6_CCM_RESET_DSTATE
};
TraceEvent _TRACE_IMX6_CCM_WRITE_EVENT = {
    .id = 0,
    .name = "imx6_ccm_write",
    .sstate = TRACE_IMX6_CCM_WRITE_ENABLED,
    .dstate = &_TRACE_IMX6_CCM_WRITE_DSTATE
};
TraceEvent _TRACE_CCM_ENTRY_EVENT = {
    .id = 0,
    .name = "ccm_entry",
    .sstate = TRACE_CCM_ENTRY_ENABLED,
    .dstate = &_TRACE_CCM_ENTRY_DSTATE
};
TraceEvent _TRACE_CCM_FREQ_EVENT = {
    .id = 0,
    .name = "ccm_freq",
    .sstate = TRACE_CCM_FREQ_ENABLED,
    .dstate = &_TRACE_CCM_FREQ_DSTATE
};
TraceEvent _TRACE_CCM_CLOCK_FREQ_EVENT = {
    .id = 0,
    .name = "ccm_clock_freq",
    .sstate = TRACE_CCM_CLOCK_FREQ_ENABLED,
    .dstate = &_TRACE_CCM_CLOCK_FREQ_DSTATE
};
TraceEvent _TRACE_CCM_READ_REG_EVENT = {
    .id = 0,
    .name = "ccm_read_reg",
    .sstate = TRACE_CCM_READ_REG_ENABLED,
    .dstate = &_TRACE_CCM_READ_REG_DSTATE
};
TraceEvent _TRACE_CCM_WRITE_REG_EVENT = {
    .id = 0,
    .name = "ccm_write_reg",
    .sstate = TRACE_CCM_WRITE_REG_ENABLED,
    .dstate = &_TRACE_CCM_WRITE_REG_DSTATE
};
TraceEvent _TRACE_IMX6_SRC_READ_EVENT = {
    .id = 0,
    .name = "imx6_src_read",
    .sstate = TRACE_IMX6_SRC_READ_ENABLED,
    .dstate = &_TRACE_IMX6_SRC_READ_DSTATE
};
TraceEvent _TRACE_IMX6_SRC_WRITE_EVENT = {
    .id = 0,
    .name = "imx6_src_write",
    .sstate = TRACE_IMX6_SRC_WRITE_ENABLED,
    .dstate = &_TRACE_IMX6_SRC_WRITE_DSTATE
};
TraceEvent _TRACE_IMX6_CLEAR_RESET_BIT_EVENT = {
    .id = 0,
    .name = "imx6_clear_reset_bit",
    .sstate = TRACE_IMX6_CLEAR_RESET_BIT_ENABLED,
    .dstate = &_TRACE_IMX6_CLEAR_RESET_BIT_DSTATE
};
TraceEvent _TRACE_IMX6_SRC_RESET_EVENT = {
    .id = 0,
    .name = "imx6_src_reset",
    .sstate = TRACE_IMX6_SRC_RESET_ENABLED,
    .dstate = &_TRACE_IMX6_SRC_RESET_DSTATE
};
TraceEvent _TRACE_IMX7_SRC_READ_EVENT = {
    .id = 0,
    .name = "imx7_src_read",
    .sstate = TRACE_IMX7_SRC_READ_ENABLED,
    .dstate = &_TRACE_IMX7_SRC_READ_DSTATE
};
TraceEvent _TRACE_IMX7_SRC_WRITE_EVENT = {
    .id = 0,
    .name = "imx7_src_write",
    .sstate = TRACE_IMX7_SRC_WRITE_ENABLED,
    .dstate = &_TRACE_IMX7_SRC_WRITE_DSTATE
};
TraceEvent _TRACE_IOTKIT_SYSINFO_READ_EVENT = {
    .id = 0,
    .name = "iotkit_sysinfo_read",
    .sstate = TRACE_IOTKIT_SYSINFO_READ_ENABLED,
    .dstate = &_TRACE_IOTKIT_SYSINFO_READ_DSTATE
};
TraceEvent _TRACE_IOTKIT_SYSINFO_WRITE_EVENT = {
    .id = 0,
    .name = "iotkit_sysinfo_write",
    .sstate = TRACE_IOTKIT_SYSINFO_WRITE_ENABLED,
    .dstate = &_TRACE_IOTKIT_SYSINFO_WRITE_DSTATE
};
TraceEvent _TRACE_IOTKIT_SYSCTL_READ_EVENT = {
    .id = 0,
    .name = "iotkit_sysctl_read",
    .sstate = TRACE_IOTKIT_SYSCTL_READ_ENABLED,
    .dstate = &_TRACE_IOTKIT_SYSCTL_READ_DSTATE
};
TraceEvent _TRACE_IOTKIT_SYSCTL_WRITE_EVENT = {
    .id = 0,
    .name = "iotkit_sysctl_write",
    .sstate = TRACE_IOTKIT_SYSCTL_WRITE_ENABLED,
    .dstate = &_TRACE_IOTKIT_SYSCTL_WRITE_DSTATE
};
TraceEvent _TRACE_IOTKIT_SYSCTL_RESET_EVENT = {
    .id = 0,
    .name = "iotkit_sysctl_reset",
    .sstate = TRACE_IOTKIT_SYSCTL_RESET_ENABLED,
    .dstate = &_TRACE_IOTKIT_SYSCTL_RESET_DSTATE
};
TraceEvent _TRACE_ARMSSE_CPU_PWRCTRL_READ_EVENT = {
    .id = 0,
    .name = "armsse_cpu_pwrctrl_read",
    .sstate = TRACE_ARMSSE_CPU_PWRCTRL_READ_ENABLED,
    .dstate = &_TRACE_ARMSSE_CPU_PWRCTRL_READ_DSTATE
};
TraceEvent _TRACE_ARMSSE_CPU_PWRCTRL_WRITE_EVENT = {
    .id = 0,
    .name = "armsse_cpu_pwrctrl_write",
    .sstate = TRACE_ARMSSE_CPU_PWRCTRL_WRITE_ENABLED,
    .dstate = &_TRACE_ARMSSE_CPU_PWRCTRL_WRITE_DSTATE
};
TraceEvent _TRACE_ARMSSE_CPUID_READ_EVENT = {
    .id = 0,
    .name = "armsse_cpuid_read",
    .sstate = TRACE_ARMSSE_CPUID_READ_ENABLED,
    .dstate = &_TRACE_ARMSSE_CPUID_READ_DSTATE
};
TraceEvent _TRACE_ARMSSE_CPUID_WRITE_EVENT = {
    .id = 0,
    .name = "armsse_cpuid_write",
    .sstate = TRACE_ARMSSE_CPUID_WRITE_ENABLED,
    .dstate = &_TRACE_ARMSSE_CPUID_WRITE_DSTATE
};
TraceEvent _TRACE_ARMSSE_MHU_READ_EVENT = {
    .id = 0,
    .name = "armsse_mhu_read",
    .sstate = TRACE_ARMSSE_MHU_READ_ENABLED,
    .dstate = &_TRACE_ARMSSE_MHU_READ_DSTATE
};
TraceEvent _TRACE_ARMSSE_MHU_WRITE_EVENT = {
    .id = 0,
    .name = "armsse_mhu_write",
    .sstate = TRACE_ARMSSE_MHU_WRITE_ENABLED,
    .dstate = &_TRACE_ARMSSE_MHU_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_XDMA_WRITE_EVENT = {
    .id = 0,
    .name = "aspeed_xdma_write",
    .sstate = TRACE_ASPEED_XDMA_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_XDMA_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_I3C_READ_EVENT = {
    .id = 0,
    .name = "aspeed_i3c_read",
    .sstate = TRACE_ASPEED_I3C_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_I3C_READ_DSTATE
};
TraceEvent _TRACE_ASPEED_I3C_WRITE_EVENT = {
    .id = 0,
    .name = "aspeed_i3c_write",
    .sstate = TRACE_ASPEED_I3C_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_I3C_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_I3C_DEVICE_READ_EVENT = {
    .id = 0,
    .name = "aspeed_i3c_device_read",
    .sstate = TRACE_ASPEED_I3C_DEVICE_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_I3C_DEVICE_READ_DSTATE
};
TraceEvent _TRACE_ASPEED_I3C_DEVICE_WRITE_EVENT = {
    .id = 0,
    .name = "aspeed_i3c_device_write",
    .sstate = TRACE_ASPEED_I3C_DEVICE_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_I3C_DEVICE_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_SDMC_WRITE_EVENT = {
    .id = 0,
    .name = "aspeed_sdmc_write",
    .sstate = TRACE_ASPEED_SDMC_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_SDMC_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_SDMC_READ_EVENT = {
    .id = 0,
    .name = "aspeed_sdmc_read",
    .sstate = TRACE_ASPEED_SDMC_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_SDMC_READ_DSTATE
};
TraceEvent _TRACE_ASPEED_PECI_READ_EVENT = {
    .id = 0,
    .name = "aspeed_peci_read",
    .sstate = TRACE_ASPEED_PECI_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_PECI_READ_DSTATE
};
TraceEvent _TRACE_ASPEED_PECI_WRITE_EVENT = {
    .id = 0,
    .name = "aspeed_peci_write",
    .sstate = TRACE_ASPEED_PECI_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_PECI_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_PECI_RAISE_INTERRUPT_EVENT = {
    .id = 0,
    .name = "aspeed_peci_raise_interrupt",
    .sstate = TRACE_ASPEED_PECI_RAISE_INTERRUPT_ENABLED,
    .dstate = &_TRACE_ASPEED_PECI_RAISE_INTERRUPT_DSTATE
};
TraceEvent _TRACE_ASPEED_HACE_READ_EVENT = {
    .id = 0,
    .name = "aspeed_hace_read",
    .sstate = TRACE_ASPEED_HACE_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_HACE_READ_DSTATE
};
TraceEvent _TRACE_ASPEED_HACE_WRITE_EVENT = {
    .id = 0,
    .name = "aspeed_hace_write",
    .sstate = TRACE_ASPEED_HACE_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_HACE_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_HACE_HASH_SG_EVENT = {
    .id = 0,
    .name = "aspeed_hace_hash_sg",
    .sstate = TRACE_ASPEED_HACE_HASH_SG_ENABLED,
    .dstate = &_TRACE_ASPEED_HACE_HASH_SG_DSTATE
};
TraceEvent _TRACE_ASPEED_HACE_HASH_ADDR_EVENT = {
    .id = 0,
    .name = "aspeed_hace_hash_addr",
    .sstate = TRACE_ASPEED_HACE_HASH_ADDR_ENABLED,
    .dstate = &_TRACE_ASPEED_HACE_HASH_ADDR_DSTATE
};
TraceEvent _TRACE_ASPEED_HACE_HASH_EXECUTE_ACC_MODE_EVENT = {
    .id = 0,
    .name = "aspeed_hace_hash_execute_acc_mode",
    .sstate = TRACE_ASPEED_HACE_HASH_EXECUTE_ACC_MODE_ENABLED,
    .dstate = &_TRACE_ASPEED_HACE_HASH_EXECUTE_ACC_MODE_DSTATE
};
TraceEvent _TRACE_ASPEED_HACE_HEXDUMP_EVENT = {
    .id = 0,
    .name = "aspeed_hace_hexdump",
    .sstate = TRACE_ASPEED_HACE_HEXDUMP_ENABLED,
    .dstate = &_TRACE_ASPEED_HACE_HEXDUMP_DSTATE
};
TraceEvent _TRACE_BCM2835_MBOX_PROPERTY_EVENT = {
    .id = 0,
    .name = "bcm2835_mbox_property",
    .sstate = TRACE_BCM2835_MBOX_PROPERTY_ENABLED,
    .dstate = &_TRACE_BCM2835_MBOX_PROPERTY_DSTATE
};
TraceEvent _TRACE_BCM2835_MBOX_WRITE_EVENT = {
    .id = 0,
    .name = "bcm2835_mbox_write",
    .sstate = TRACE_BCM2835_MBOX_WRITE_ENABLED,
    .dstate = &_TRACE_BCM2835_MBOX_WRITE_DSTATE
};
TraceEvent _TRACE_BCM2835_MBOX_READ_EVENT = {
    .id = 0,
    .name = "bcm2835_mbox_read",
    .sstate = TRACE_BCM2835_MBOX_READ_ENABLED,
    .dstate = &_TRACE_BCM2835_MBOX_READ_DSTATE
};
TraceEvent _TRACE_BCM2835_MBOX_IRQ_EVENT = {
    .id = 0,
    .name = "bcm2835_mbox_irq",
    .sstate = TRACE_BCM2835_MBOX_IRQ_ENABLED,
    .dstate = &_TRACE_BCM2835_MBOX_IRQ_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_UPDATE_DATA_OUT_EVENT = {
    .id = 0,
    .name = "via1_rtc_update_data_out",
    .sstate = TRACE_VIA1_RTC_UPDATE_DATA_OUT_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_UPDATE_DATA_OUT_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_UPDATE_DATA_IN_EVENT = {
    .id = 0,
    .name = "via1_rtc_update_data_in",
    .sstate = TRACE_VIA1_RTC_UPDATE_DATA_IN_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_UPDATE_DATA_IN_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_INTERNAL_STATUS_EVENT = {
    .id = 0,
    .name = "via1_rtc_internal_status",
    .sstate = TRACE_VIA1_RTC_INTERNAL_STATUS_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_INTERNAL_STATUS_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_INTERNAL_CMD_EVENT = {
    .id = 0,
    .name = "via1_rtc_internal_cmd",
    .sstate = TRACE_VIA1_RTC_INTERNAL_CMD_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_INTERNAL_CMD_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_CMD_INVALID_EVENT = {
    .id = 0,
    .name = "via1_rtc_cmd_invalid",
    .sstate = TRACE_VIA1_RTC_CMD_INVALID_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_CMD_INVALID_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_INTERNAL_TIME_EVENT = {
    .id = 0,
    .name = "via1_rtc_internal_time",
    .sstate = TRACE_VIA1_RTC_INTERNAL_TIME_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_INTERNAL_TIME_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_INTERNAL_SET_CMD_EVENT = {
    .id = 0,
    .name = "via1_rtc_internal_set_cmd",
    .sstate = TRACE_VIA1_RTC_INTERNAL_SET_CMD_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_INTERNAL_SET_CMD_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_EVENT = {
    .id = 0,
    .name = "via1_rtc_internal_ignore_cmd",
    .sstate = TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_INTERNAL_SET_ALT_EVENT = {
    .id = 0,
    .name = "via1_rtc_internal_set_alt",
    .sstate = TRACE_VIA1_RTC_INTERNAL_SET_ALT_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_INTERNAL_SET_ALT_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_CMD_SECONDS_READ_EVENT = {
    .id = 0,
    .name = "via1_rtc_cmd_seconds_read",
    .sstate = TRACE_VIA1_RTC_CMD_SECONDS_READ_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_CMD_SECONDS_READ_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_CMD_SECONDS_WRITE_EVENT = {
    .id = 0,
    .name = "via1_rtc_cmd_seconds_write",
    .sstate = TRACE_VIA1_RTC_CMD_SECONDS_WRITE_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_CMD_SECONDS_WRITE_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_CMD_TEST_WRITE_EVENT = {
    .id = 0,
    .name = "via1_rtc_cmd_test_write",
    .sstate = TRACE_VIA1_RTC_CMD_TEST_WRITE_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_CMD_TEST_WRITE_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_EVENT = {
    .id = 0,
    .name = "via1_rtc_cmd_wprotect_write",
    .sstate = TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_CMD_PRAM_READ_EVENT = {
    .id = 0,
    .name = "via1_rtc_cmd_pram_read",
    .sstate = TRACE_VIA1_RTC_CMD_PRAM_READ_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_CMD_PRAM_READ_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_CMD_PRAM_WRITE_EVENT = {
    .id = 0,
    .name = "via1_rtc_cmd_pram_write",
    .sstate = TRACE_VIA1_RTC_CMD_PRAM_WRITE_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_CMD_PRAM_WRITE_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_EVENT = {
    .id = 0,
    .name = "via1_rtc_cmd_pram_sect_read",
    .sstate = TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_DSTATE
};
TraceEvent _TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_EVENT = {
    .id = 0,
    .name = "via1_rtc_cmd_pram_sect_write",
    .sstate = TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_ENABLED,
    .dstate = &_TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_DSTATE
};
TraceEvent _TRACE_VIA1_ADB_SEND_EVENT = {
    .id = 0,
    .name = "via1_adb_send",
    .sstate = TRACE_VIA1_ADB_SEND_ENABLED,
    .dstate = &_TRACE_VIA1_ADB_SEND_DSTATE
};
TraceEvent _TRACE_VIA1_ADB_RECEIVE_EVENT = {
    .id = 0,
    .name = "via1_adb_receive",
    .sstate = TRACE_VIA1_ADB_RECEIVE_ENABLED,
    .dstate = &_TRACE_VIA1_ADB_RECEIVE_DSTATE
};
TraceEvent _TRACE_VIA1_ADB_POLL_EVENT = {
    .id = 0,
    .name = "via1_adb_poll",
    .sstate = TRACE_VIA1_ADB_POLL_ENABLED,
    .dstate = &_TRACE_VIA1_ADB_POLL_DSTATE
};
TraceEvent _TRACE_VIA1_ADB_NETBSD_ENUM_HACK_EVENT = {
    .id = 0,
    .name = "via1_adb_netbsd_enum_hack",
    .sstate = TRACE_VIA1_ADB_NETBSD_ENUM_HACK_ENABLED,
    .dstate = &_TRACE_VIA1_ADB_NETBSD_ENUM_HACK_DSTATE
};
TraceEvent _TRACE_VIA1_AUXMODE_EVENT = {
    .id = 0,
    .name = "via1_auxmode",
    .sstate = TRACE_VIA1_AUXMODE_ENABLED,
    .dstate = &_TRACE_VIA1_AUXMODE_DSTATE
};
TraceEvent _TRACE_VIA1_TIMER_HACK_STATE_EVENT = {
    .id = 0,
    .name = "via1_timer_hack_state",
    .sstate = TRACE_VIA1_TIMER_HACK_STATE_ENABLED,
    .dstate = &_TRACE_VIA1_TIMER_HACK_STATE_DSTATE
};
TraceEvent _TRACE_GRLIB_AHB_PNP_READ_EVENT = {
    .id = 0,
    .name = "grlib_ahb_pnp_read",
    .sstate = TRACE_GRLIB_AHB_PNP_READ_ENABLED,
    .dstate = &_TRACE_GRLIB_AHB_PNP_READ_DSTATE
};
TraceEvent _TRACE_GRLIB_APB_PNP_READ_EVENT = {
    .id = 0,
    .name = "grlib_apb_pnp_read",
    .sstate = TRACE_GRLIB_APB_PNP_READ_ENABLED,
    .dstate = &_TRACE_GRLIB_APB_PNP_READ_DSTATE
};
TraceEvent _TRACE_LED_SET_INTENSITY_EVENT = {
    .id = 0,
    .name = "led_set_intensity",
    .sstate = TRACE_LED_SET_INTENSITY_ENABLED,
    .dstate = &_TRACE_LED_SET_INTENSITY_DSTATE
};
TraceEvent _TRACE_LED_CHANGE_INTENSITY_EVENT = {
    .id = 0,
    .name = "led_change_intensity",
    .sstate = TRACE_LED_CHANGE_INTENSITY_ENABLED,
    .dstate = &_TRACE_LED_CHANGE_INTENSITY_DSTATE
};
TraceEvent _TRACE_BCM2835_CPRMAN_READ_EVENT = {
    .id = 0,
    .name = "bcm2835_cprman_read",
    .sstate = TRACE_BCM2835_CPRMAN_READ_ENABLED,
    .dstate = &_TRACE_BCM2835_CPRMAN_READ_DSTATE
};
TraceEvent _TRACE_BCM2835_CPRMAN_WRITE_EVENT = {
    .id = 0,
    .name = "bcm2835_cprman_write",
    .sstate = TRACE_BCM2835_CPRMAN_WRITE_ENABLED,
    .dstate = &_TRACE_BCM2835_CPRMAN_WRITE_DSTATE
};
TraceEvent _TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_EVENT = {
    .id = 0,
    .name = "bcm2835_cprman_write_invalid_magic",
    .sstate = TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_ENABLED,
    .dstate = &_TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_DSTATE
};
TraceEvent _TRACE_VIRT_CTRL_READ_EVENT = {
    .id = 0,
    .name = "virt_ctrl_read",
    .sstate = TRACE_VIRT_CTRL_READ_ENABLED,
    .dstate = &_TRACE_VIRT_CTRL_READ_DSTATE
};
TraceEvent _TRACE_VIRT_CTRL_WRITE_EVENT = {
    .id = 0,
    .name = "virt_ctrl_write",
    .sstate = TRACE_VIRT_CTRL_WRITE_ENABLED,
    .dstate = &_TRACE_VIRT_CTRL_WRITE_DSTATE
};
TraceEvent _TRACE_VIRT_CTRL_RESET_EVENT = {
    .id = 0,
    .name = "virt_ctrl_reset",
    .sstate = TRACE_VIRT_CTRL_RESET_ENABLED,
    .dstate = &_TRACE_VIRT_CTRL_RESET_DSTATE
};
TraceEvent _TRACE_VIRT_CTRL_REALIZE_EVENT = {
    .id = 0,
    .name = "virt_ctrl_realize",
    .sstate = TRACE_VIRT_CTRL_REALIZE_ENABLED,
    .dstate = &_TRACE_VIRT_CTRL_REALIZE_DSTATE
};
TraceEvent _TRACE_VIRT_CTRL_INSTANCE_INIT_EVENT = {
    .id = 0,
    .name = "virt_ctrl_instance_init",
    .sstate = TRACE_VIRT_CTRL_INSTANCE_INIT_ENABLED,
    .dstate = &_TRACE_VIRT_CTRL_INSTANCE_INIT_DSTATE
};
TraceEvent _TRACE_LASI_CHIP_MEM_VALID_EVENT = {
    .id = 0,
    .name = "lasi_chip_mem_valid",
    .sstate = TRACE_LASI_CHIP_MEM_VALID_ENABLED,
    .dstate = &_TRACE_LASI_CHIP_MEM_VALID_DSTATE
};
TraceEvent _TRACE_LASI_CHIP_READ_EVENT = {
    .id = 0,
    .name = "lasi_chip_read",
    .sstate = TRACE_LASI_CHIP_READ_ENABLED,
    .dstate = &_TRACE_LASI_CHIP_READ_DSTATE
};
TraceEvent _TRACE_LASI_CHIP_WRITE_EVENT = {
    .id = 0,
    .name = "lasi_chip_write",
    .sstate = TRACE_LASI_CHIP_WRITE_ENABLED,
    .dstate = &_TRACE_LASI_CHIP_WRITE_DSTATE
};
TraceEvent _TRACE_DJMEMC_READ_EVENT = {
    .id = 0,
    .name = "djmemc_read",
    .sstate = TRACE_DJMEMC_READ_ENABLED,
    .dstate = &_TRACE_DJMEMC_READ_DSTATE
};
TraceEvent _TRACE_DJMEMC_WRITE_EVENT = {
    .id = 0,
    .name = "djmemc_write",
    .sstate = TRACE_DJMEMC_WRITE_ENABLED,
    .dstate = &_TRACE_DJMEMC_WRITE_DSTATE
};
TraceEvent _TRACE_IOSB_READ_EVENT = {
    .id = 0,
    .name = "iosb_read",
    .sstate = TRACE_IOSB_READ_ENABLED,
    .dstate = &_TRACE_IOSB_READ_DSTATE
};
TraceEvent _TRACE_IOSB_WRITE_EVENT = {
    .id = 0,
    .name = "iosb_write",
    .sstate = TRACE_IOSB_WRITE_ENABLED,
    .dstate = &_TRACE_IOSB_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_SLI_WRITE_EVENT = {
    .id = 0,
    .name = "aspeed_sli_write",
    .sstate = TRACE_ASPEED_SLI_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_SLI_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_SLI_READ_EVENT = {
    .id = 0,
    .name = "aspeed_sli_read",
    .sstate = TRACE_ASPEED_SLI_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_SLI_READ_DSTATE
};
TraceEvent _TRACE_ASPEED_SLIIO_WRITE_EVENT = {
    .id = 0,
    .name = "aspeed_sliio_write",
    .sstate = TRACE_ASPEED_SLIIO_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_SLIIO_WRITE_DSTATE
};
TraceEvent _TRACE_ASPEED_SLIIO_READ_EVENT = {
    .id = 0,
    .name = "aspeed_sliio_read",
    .sstate = TRACE_ASPEED_SLIIO_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_SLIIO_READ_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_IRQ_HANDLER_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_irq_handler",
    .sstate = TRACE_IVSHMEM_FLAT_IRQ_HANDLER_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_IRQ_HANDLER_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_NEW_PEER_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_new_peer",
    .sstate = TRACE_IVSHMEM_FLAT_NEW_PEER_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_NEW_PEER_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_ADD_VECTOR_FAILURE_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_add_vector_failure",
    .sstate = TRACE_IVSHMEM_FLAT_ADD_VECTOR_FAILURE_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_ADD_VECTOR_FAILURE_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_ADD_VECTOR_SUCCESS_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_add_vector_success",
    .sstate = TRACE_IVSHMEM_FLAT_ADD_VECTOR_SUCCESS_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_ADD_VECTOR_SUCCESS_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_IRQ_RESOLVED_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_irq_resolved",
    .sstate = TRACE_IVSHMEM_FLAT_IRQ_RESOLVED_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_IRQ_RESOLVED_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_PROTO_VER_OWN_ID_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_proto_ver_own_id",
    .sstate = TRACE_IVSHMEM_FLAT_PROTO_VER_OWN_ID_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_PROTO_VER_OWN_ID_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_SHMEM_SIZE_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_shmem_size",
    .sstate = TRACE_IVSHMEM_FLAT_SHMEM_SIZE_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_SHMEM_SIZE_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_SHMEM_MAP_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_shmem_map",
    .sstate = TRACE_IVSHMEM_FLAT_SHMEM_MAP_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_SHMEM_MAP_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_MMIO_MAP_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_mmio_map",
    .sstate = TRACE_IVSHMEM_FLAT_MMIO_MAP_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_MMIO_MAP_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_READ_MMR_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_read_mmr",
    .sstate = TRACE_IVSHMEM_FLAT_READ_MMR_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_READ_MMR_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_READ_MMR_DOORBELL_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_read_mmr_doorbell",
    .sstate = TRACE_IVSHMEM_FLAT_READ_MMR_DOORBELL_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_READ_MMR_DOORBELL_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_READ_WRITE_MMR_INVALID_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_read_write_mmr_invalid",
    .sstate = TRACE_IVSHMEM_FLAT_READ_WRITE_MMR_INVALID_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_READ_WRITE_MMR_INVALID_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_INTERRUPT_INVALID_PEER_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_interrupt_invalid_peer",
    .sstate = TRACE_IVSHMEM_FLAT_INTERRUPT_INVALID_PEER_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_INTERRUPT_INVALID_PEER_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_WRITE_MMR_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_write_mmr",
    .sstate = TRACE_IVSHMEM_FLAT_WRITE_MMR_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_WRITE_MMR_DSTATE
};
TraceEvent _TRACE_IVSHMEM_FLAT_INTERRUPT_PEER_EVENT = {
    .id = 0,
    .name = "ivshmem_flat_interrupt_peer",
    .sstate = TRACE_IVSHMEM_FLAT_INTERRUPT_PEER_ENABLED,
    .dstate = &_TRACE_IVSHMEM_FLAT_INTERRUPT_PEER_DSTATE
};
TraceEvent _TRACE_I2C_ECHO_EVENT_EVENT = {
    .id = 0,
    .name = "i2c_echo_event",
    .sstate = TRACE_I2C_ECHO_EVENT_ENABLED,
    .dstate = &_TRACE_I2C_ECHO_EVENT_DSTATE
};
TraceEvent _TRACE_I2C_ECHO_RECV_EVENT = {
    .id = 0,
    .name = "i2c_echo_recv",
    .sstate = TRACE_I2C_ECHO_RECV_ENABLED,
    .dstate = &_TRACE_I2C_ECHO_RECV_DSTATE
};
TraceEvent _TRACE_I2C_ECHO_SEND_EVENT = {
    .id = 0,
    .name = "i2c_echo_send",
    .sstate = TRACE_I2C_ECHO_SEND_ENABLED,
    .dstate = &_TRACE_I2C_ECHO_SEND_DSTATE
};
TraceEvent *hw_misc_trace_events[] = {
    &_TRACE_ALLWINNER_CPUCFG_CPU_RESET_EVENT,
    &_TRACE_ALLWINNER_CPUCFG_READ_EVENT,
    &_TRACE_ALLWINNER_CPUCFG_WRITE_EVENT,
    &_TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_EVENT,
    &_TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_EVENT,
    &_TRACE_ALLWINNER_H3_DRAMCOM_READ_EVENT,
    &_TRACE_ALLWINNER_H3_DRAMCOM_WRITE_EVENT,
    &_TRACE_ALLWINNER_H3_DRAMCTL_READ_EVENT,
    &_TRACE_ALLWINNER_H3_DRAMCTL_WRITE_EVENT,
    &_TRACE_ALLWINNER_H3_DRAMPHY_READ_EVENT,
    &_TRACE_ALLWINNER_H3_DRAMPHY_WRITE_EVENT,
    &_TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_EVENT,
    &_TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_EVENT,
    &_TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_EVENT,
    &_TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_EVENT,
    &_TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_EVENT,
    &_TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_EVENT,
    &_TRACE_ALLWINNER_R40_DRAMCOM_READ_EVENT,
    &_TRACE_ALLWINNER_R40_DRAMCOM_WRITE_EVENT,
    &_TRACE_ALLWINNER_R40_DRAMCTL_READ_EVENT,
    &_TRACE_ALLWINNER_R40_DRAMCTL_WRITE_EVENT,
    &_TRACE_ALLWINNER_R40_DRAMPHY_READ_EVENT,
    &_TRACE_ALLWINNER_R40_DRAMPHY_WRITE_EVENT,
    &_TRACE_ALLWINNER_SID_READ_EVENT,
    &_TRACE_ALLWINNER_SID_WRITE_EVENT,
    &_TRACE_ALLWINNER_SRAMC_READ_EVENT,
    &_TRACE_ALLWINNER_SRAMC_WRITE_EVENT,
    &_TRACE_AVR_POWER_READ_EVENT,
    &_TRACE_AVR_POWER_WRITE_EVENT,
    &_TRACE_AXP2XX_RX_EVENT,
    &_TRACE_AXP2XX_SELECT_EVENT,
    &_TRACE_AXP2XX_TX_EVENT,
    &_TRACE_ECC_MEM_WRITEL_MER_EVENT,
    &_TRACE_ECC_MEM_WRITEL_MDR_EVENT,
    &_TRACE_ECC_MEM_WRITEL_MFSR_EVENT,
    &_TRACE_ECC_MEM_WRITEL_VCR_EVENT,
    &_TRACE_ECC_MEM_WRITEL_DR_EVENT,
    &_TRACE_ECC_MEM_WRITEL_ECR0_EVENT,
    &_TRACE_ECC_MEM_WRITEL_ECR1_EVENT,
    &_TRACE_ECC_MEM_READL_MER_EVENT,
    &_TRACE_ECC_MEM_READL_MDR_EVENT,
    &_TRACE_ECC_MEM_READL_MFSR_EVENT,
    &_TRACE_ECC_MEM_READL_VCR_EVENT,
    &_TRACE_ECC_MEM_READL_MFAR0_EVENT,
    &_TRACE_ECC_MEM_READL_MFAR1_EVENT,
    &_TRACE_ECC_MEM_READL_DR_EVENT,
    &_TRACE_ECC_MEM_READL_ECR0_EVENT,
    &_TRACE_ECC_MEM_READL_ECR1_EVENT,
    &_TRACE_ECC_DIAG_MEM_WRITEB_EVENT,
    &_TRACE_ECC_DIAG_MEM_READB_EVENT,
    &_TRACE_EMPTY_SLOT_WRITE_EVENT,
    &_TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_EVENT,
    &_TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_EVENT,
    &_TRACE_SLAVIO_SET_POWER_FAIL_EVENT,
    &_TRACE_SLAVIO_CFG_MEM_WRITEB_EVENT,
    &_TRACE_SLAVIO_CFG_MEM_READB_EVENT,
    &_TRACE_SLAVIO_DIAG_MEM_WRITEB_EVENT,
    &_TRACE_SLAVIO_DIAG_MEM_READB_EVENT,
    &_TRACE_SLAVIO_MDM_MEM_WRITEB_EVENT,
    &_TRACE_SLAVIO_MDM_MEM_READB_EVENT,
    &_TRACE_SLAVIO_AUX1_MEM_WRITEB_EVENT,
    &_TRACE_SLAVIO_AUX1_MEM_READB_EVENT,
    &_TRACE_SLAVIO_AUX2_MEM_WRITEB_EVENT,
    &_TRACE_SLAVIO_AUX2_MEM_READB_EVENT,
    &_TRACE_APC_MEM_WRITEB_EVENT,
    &_TRACE_APC_MEM_READB_EVENT,
    &_TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_EVENT,
    &_TRACE_SLAVIO_SYSCTRL_MEM_READL_EVENT,
    &_TRACE_SLAVIO_LED_MEM_WRITEW_EVENT,
    &_TRACE_SLAVIO_LED_MEM_READW_EVENT,
    &_TRACE_ASPEED_SBC_IGNORE_CMD_EVENT,
    &_TRACE_ASPEED_SBC_HANDLE_CMD_EVENT,
    &_TRACE_ASPEED_SBC_OTP_READ_EVENT,
    &_TRACE_ASPEED_SBC_OTP_PROG_EVENT,
    &_TRACE_ASPEED_SCU_WRITE_EVENT,
    &_TRACE_ASPEED_SCU_READ_EVENT,
    &_TRACE_ASPEED_AST2700_SCU_WRITE_EVENT,
    &_TRACE_ASPEED_AST2700_SCU_READ_EVENT,
    &_TRACE_ASPEED_AST2700_SCUIO_WRITE_EVENT,
    &_TRACE_ASPEED_AST2700_SCUIO_READ_EVENT,
    &_TRACE_MPS2_SCC_READ_EVENT,
    &_TRACE_MPS2_SCC_WRITE_EVENT,
    &_TRACE_MPS2_SCC_RESET_EVENT,
    &_TRACE_MPS2_SCC_CFG_WRITE_EVENT,
    &_TRACE_MPS2_SCC_CFG_READ_EVENT,
    &_TRACE_MPS2_FPGAIO_READ_EVENT,
    &_TRACE_MPS2_FPGAIO_WRITE_EVENT,
    &_TRACE_MPS2_FPGAIO_RESET_EVENT,
    &_TRACE_MSF2_SYSREG_WRITE_EVENT,
    &_TRACE_MSF2_SYSREG_READ_EVENT,
    &_TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_EVENT,
    &_TRACE_IMX7_GPR_READ_EVENT,
    &_TRACE_IMX7_GPR_WRITE_EVENT,
    &_TRACE_IMX7_SNVS_READ_EVENT,
    &_TRACE_IMX7_SNVS_WRITE_EVENT,
    &_TRACE_MOS6522_SET_COUNTER_EVENT,
    &_TRACE_MOS6522_GET_NEXT_IRQ_TIME_EVENT,
    &_TRACE_MOS6522_SET_SR_INT_EVENT,
    &_TRACE_MOS6522_WRITE_EVENT,
    &_TRACE_MOS6522_READ_EVENT,
    &_TRACE_NPCM_CLK_READ_EVENT,
    &_TRACE_NPCM_CLK_WRITE_EVENT,
    &_TRACE_NPCM_GCR_READ_EVENT,
    &_TRACE_NPCM_GCR_WRITE_EVENT,
    &_TRACE_NPCM7XX_MFT_READ_EVENT,
    &_TRACE_NPCM7XX_MFT_WRITE_EVENT,
    &_TRACE_NPCM7XX_MFT_RPM_EVENT,
    &_TRACE_NPCM7XX_MFT_CAPTURE_EVENT,
    &_TRACE_NPCM7XX_MFT_UPDATE_CLOCK_EVENT,
    &_TRACE_NPCM7XX_MFT_SET_DUTY_EVENT,
    &_TRACE_NPCM7XX_RNG_READ_EVENT,
    &_TRACE_NPCM7XX_RNG_WRITE_EVENT,
    &_TRACE_NPCM7XX_PWM_READ_EVENT,
    &_TRACE_NPCM7XX_PWM_WRITE_EVENT,
    &_TRACE_NPCM7XX_PWM_UPDATE_FREQ_EVENT,
    &_TRACE_NPCM7XX_PWM_UPDATE_DUTY_EVENT,
    &_TRACE_STM32_RCC_READ_EVENT,
    &_TRACE_STM32_RCC_WRITE_EVENT,
    &_TRACE_STM32_RCC_PULSE_ENABLE_EVENT,
    &_TRACE_STM32_RCC_PULSE_RESET_EVENT,
    &_TRACE_STM32F4XX_SYSCFG_SET_IRQ_EVENT,
    &_TRACE_STM32F4XX_PULSE_EXTI_EVENT,
    &_TRACE_STM32F4XX_SYSCFG_READ_EVENT,
    &_TRACE_STM32F4XX_SYSCFG_WRITE_EVENT,
    &_TRACE_STM32F4XX_EXTI_SET_IRQ_EVENT,
    &_TRACE_STM32F4XX_EXTI_READ_EVENT,
    &_TRACE_STM32F4XX_EXTI_WRITE_EVENT,
    &_TRACE_STM32L4X5_SYSCFG_SET_IRQ_EVENT,
    &_TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_EVENT,
    &_TRACE_STM32L4X5_SYSCFG_READ_EVENT,
    &_TRACE_STM32L4X5_SYSCFG_WRITE_EVENT,
    &_TRACE_STM32L4X5_EXTI_SET_IRQ_EVENT,
    &_TRACE_STM32L4X5_EXTI_READ_EVENT,
    &_TRACE_STM32L4X5_EXTI_WRITE_EVENT,
    &_TRACE_STM32L4X5_RCC_READ_EVENT,
    &_TRACE_STM32L4X5_RCC_WRITE_EVENT,
    &_TRACE_STM32L4X5_RCC_MUX_ENABLE_EVENT,
    &_TRACE_STM32L4X5_RCC_MUX_DISABLE_EVENT,
    &_TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_EVENT,
    &_TRACE_STM32L4X5_RCC_MUX_SET_SRC_EVENT,
    &_TRACE_STM32L4X5_RCC_MUX_UPDATE_EVENT,
    &_TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_EVENT,
    &_TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_EVENT,
    &_TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_EVENT,
    &_TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_EVENT,
    &_TRACE_STM32L4X5_RCC_PLL_UPDATE_EVENT,
    &_TRACE_TZ_MPC_REG_READ_EVENT,
    &_TRACE_TZ_MPC_REG_WRITE_EVENT,
    &_TRACE_TZ_MPC_MEM_BLOCKED_READ_EVENT,
    &_TRACE_TZ_MPC_MEM_BLOCKED_WRITE_EVENT,
    &_TRACE_TZ_MPC_TRANSLATE_EVENT,
    &_TRACE_TZ_MPC_IOMMU_NOTIFY_EVENT,
    &_TRACE_TZ_MSC_RESET_EVENT,
    &_TRACE_TZ_MSC_CFG_NONSEC_EVENT,
    &_TRACE_TZ_MSC_CFG_SEC_RESP_EVENT,
    &_TRACE_TZ_MSC_IRQ_CLEAR_EVENT,
    &_TRACE_TZ_MSC_UPDATE_IRQ_EVENT,
    &_TRACE_TZ_MSC_ACCESS_BLOCKED_EVENT,
    &_TRACE_TZ_PPC_RESET_EVENT,
    &_TRACE_TZ_PPC_CFG_NONSEC_EVENT,
    &_TRACE_TZ_PPC_CFG_AP_EVENT,
    &_TRACE_TZ_PPC_CFG_SEC_RESP_EVENT,
    &_TRACE_TZ_PPC_IRQ_ENABLE_EVENT,
    &_TRACE_TZ_PPC_IRQ_CLEAR_EVENT,
    &_TRACE_TZ_PPC_UPDATE_IRQ_EVENT,
    &_TRACE_TZ_PPC_READ_BLOCKED_EVENT,
    &_TRACE_TZ_PPC_WRITE_BLOCKED_EVENT,
    &_TRACE_IOTKIT_SECCTL_S_READ_EVENT,
    &_TRACE_IOTKIT_SECCTL_S_WRITE_EVENT,
    &_TRACE_IOTKIT_SECCTL_NS_READ_EVENT,
    &_TRACE_IOTKIT_SECCTL_NS_WRITE_EVENT,
    &_TRACE_IMX6_ANALOG_GET_PERIPH_CLK_EVENT,
    &_TRACE_IMX6_ANALOG_GET_PLL2_CLK_EVENT,
    &_TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_EVENT,
    &_TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_EVENT,
    &_TRACE_IMX6_ANALOG_READ_EVENT,
    &_TRACE_IMX6_ANALOG_WRITE_EVENT,
    &_TRACE_IMX6_CCM_GET_AHB_CLK_EVENT,
    &_TRACE_IMX6_CCM_GET_IPG_CLK_EVENT,
    &_TRACE_IMX6_CCM_GET_PER_CLK_EVENT,
    &_TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_EVENT,
    &_TRACE_IMX6_CCM_READ_EVENT,
    &_TRACE_IMX6_CCM_RESET_EVENT,
    &_TRACE_IMX6_CCM_WRITE_EVENT,
    &_TRACE_CCM_ENTRY_EVENT,
    &_TRACE_CCM_FREQ_EVENT,
    &_TRACE_CCM_CLOCK_FREQ_EVENT,
    &_TRACE_CCM_READ_REG_EVENT,
    &_TRACE_CCM_WRITE_REG_EVENT,
    &_TRACE_IMX6_SRC_READ_EVENT,
    &_TRACE_IMX6_SRC_WRITE_EVENT,
    &_TRACE_IMX6_CLEAR_RESET_BIT_EVENT,
    &_TRACE_IMX6_SRC_RESET_EVENT,
    &_TRACE_IMX7_SRC_READ_EVENT,
    &_TRACE_IMX7_SRC_WRITE_EVENT,
    &_TRACE_IOTKIT_SYSINFO_READ_EVENT,
    &_TRACE_IOTKIT_SYSINFO_WRITE_EVENT,
    &_TRACE_IOTKIT_SYSCTL_READ_EVENT,
    &_TRACE_IOTKIT_SYSCTL_WRITE_EVENT,
    &_TRACE_IOTKIT_SYSCTL_RESET_EVENT,
    &_TRACE_ARMSSE_CPU_PWRCTRL_READ_EVENT,
    &_TRACE_ARMSSE_CPU_PWRCTRL_WRITE_EVENT,
    &_TRACE_ARMSSE_CPUID_READ_EVENT,
    &_TRACE_ARMSSE_CPUID_WRITE_EVENT,
    &_TRACE_ARMSSE_MHU_READ_EVENT,
    &_TRACE_ARMSSE_MHU_WRITE_EVENT,
    &_TRACE_ASPEED_XDMA_WRITE_EVENT,
    &_TRACE_ASPEED_I3C_READ_EVENT,
    &_TRACE_ASPEED_I3C_WRITE_EVENT,
    &_TRACE_ASPEED_I3C_DEVICE_READ_EVENT,
    &_TRACE_ASPEED_I3C_DEVICE_WRITE_EVENT,
    &_TRACE_ASPEED_SDMC_WRITE_EVENT,
    &_TRACE_ASPEED_SDMC_READ_EVENT,
    &_TRACE_ASPEED_PECI_READ_EVENT,
    &_TRACE_ASPEED_PECI_WRITE_EVENT,
    &_TRACE_ASPEED_PECI_RAISE_INTERRUPT_EVENT,
    &_TRACE_ASPEED_HACE_READ_EVENT,
    &_TRACE_ASPEED_HACE_WRITE_EVENT,
    &_TRACE_ASPEED_HACE_HASH_SG_EVENT,
    &_TRACE_ASPEED_HACE_HASH_ADDR_EVENT,
    &_TRACE_ASPEED_HACE_HASH_EXECUTE_ACC_MODE_EVENT,
    &_TRACE_ASPEED_HACE_HEXDUMP_EVENT,
    &_TRACE_BCM2835_MBOX_PROPERTY_EVENT,
    &_TRACE_BCM2835_MBOX_WRITE_EVENT,
    &_TRACE_BCM2835_MBOX_READ_EVENT,
    &_TRACE_BCM2835_MBOX_IRQ_EVENT,
    &_TRACE_VIA1_RTC_UPDATE_DATA_OUT_EVENT,
    &_TRACE_VIA1_RTC_UPDATE_DATA_IN_EVENT,
    &_TRACE_VIA1_RTC_INTERNAL_STATUS_EVENT,
    &_TRACE_VIA1_RTC_INTERNAL_CMD_EVENT,
    &_TRACE_VIA1_RTC_CMD_INVALID_EVENT,
    &_TRACE_VIA1_RTC_INTERNAL_TIME_EVENT,
    &_TRACE_VIA1_RTC_INTERNAL_SET_CMD_EVENT,
    &_TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_EVENT,
    &_TRACE_VIA1_RTC_INTERNAL_SET_ALT_EVENT,
    &_TRACE_VIA1_RTC_CMD_SECONDS_READ_EVENT,
    &_TRACE_VIA1_RTC_CMD_SECONDS_WRITE_EVENT,
    &_TRACE_VIA1_RTC_CMD_TEST_WRITE_EVENT,
    &_TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_EVENT,
    &_TRACE_VIA1_RTC_CMD_PRAM_READ_EVENT,
    &_TRACE_VIA1_RTC_CMD_PRAM_WRITE_EVENT,
    &_TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_EVENT,
    &_TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_EVENT,
    &_TRACE_VIA1_ADB_SEND_EVENT,
    &_TRACE_VIA1_ADB_RECEIVE_EVENT,
    &_TRACE_VIA1_ADB_POLL_EVENT,
    &_TRACE_VIA1_ADB_NETBSD_ENUM_HACK_EVENT,
    &_TRACE_VIA1_AUXMODE_EVENT,
    &_TRACE_VIA1_TIMER_HACK_STATE_EVENT,
    &_TRACE_GRLIB_AHB_PNP_READ_EVENT,
    &_TRACE_GRLIB_APB_PNP_READ_EVENT,
    &_TRACE_LED_SET_INTENSITY_EVENT,
    &_TRACE_LED_CHANGE_INTENSITY_EVENT,
    &_TRACE_BCM2835_CPRMAN_READ_EVENT,
    &_TRACE_BCM2835_CPRMAN_WRITE_EVENT,
    &_TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_EVENT,
    &_TRACE_VIRT_CTRL_READ_EVENT,
    &_TRACE_VIRT_CTRL_WRITE_EVENT,
    &_TRACE_VIRT_CTRL_RESET_EVENT,
    &_TRACE_VIRT_CTRL_REALIZE_EVENT,
    &_TRACE_VIRT_CTRL_INSTANCE_INIT_EVENT,
    &_TRACE_LASI_CHIP_MEM_VALID_EVENT,
    &_TRACE_LASI_CHIP_READ_EVENT,
    &_TRACE_LASI_CHIP_WRITE_EVENT,
    &_TRACE_DJMEMC_READ_EVENT,
    &_TRACE_DJMEMC_WRITE_EVENT,
    &_TRACE_IOSB_READ_EVENT,
    &_TRACE_IOSB_WRITE_EVENT,
    &_TRACE_ASPEED_SLI_WRITE_EVENT,
    &_TRACE_ASPEED_SLI_READ_EVENT,
    &_TRACE_ASPEED_SLIIO_WRITE_EVENT,
    &_TRACE_ASPEED_SLIIO_READ_EVENT,
    &_TRACE_IVSHMEM_FLAT_IRQ_HANDLER_EVENT,
    &_TRACE_IVSHMEM_FLAT_NEW_PEER_EVENT,
    &_TRACE_IVSHMEM_FLAT_ADD_VECTOR_FAILURE_EVENT,
    &_TRACE_IVSHMEM_FLAT_ADD_VECTOR_SUCCESS_EVENT,
    &_TRACE_IVSHMEM_FLAT_IRQ_RESOLVED_EVENT,
    &_TRACE_IVSHMEM_FLAT_PROTO_VER_OWN_ID_EVENT,
    &_TRACE_IVSHMEM_FLAT_SHMEM_SIZE_EVENT,
    &_TRACE_IVSHMEM_FLAT_SHMEM_MAP_EVENT,
    &_TRACE_IVSHMEM_FLAT_MMIO_MAP_EVENT,
    &_TRACE_IVSHMEM_FLAT_READ_MMR_EVENT,
    &_TRACE_IVSHMEM_FLAT_READ_MMR_DOORBELL_EVENT,
    &_TRACE_IVSHMEM_FLAT_READ_WRITE_MMR_INVALID_EVENT,
    &_TRACE_IVSHMEM_FLAT_INTERRUPT_INVALID_PEER_EVENT,
    &_TRACE_IVSHMEM_FLAT_WRITE_MMR_EVENT,
    &_TRACE_IVSHMEM_FLAT_INTERRUPT_PEER_EVENT,
    &_TRACE_I2C_ECHO_EVENT_EVENT,
    &_TRACE_I2C_ECHO_RECV_EVENT,
    &_TRACE_I2C_ECHO_SEND_EVENT,
  NULL,
};

static void trace_hw_misc_register_events(void)
{
    trace_event_register_group(hw_misc_trace_events);
}
trace_init(trace_hw_misc_register_events)
