/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_timer.h"

uint16_t _TRACE_SLAVIO_TIMER_GET_OUT_DSTATE;
uint16_t _TRACE_SLAVIO_TIMER_IRQ_DSTATE;
uint16_t _TRACE_SLAVIO_TIMER_MEM_READL_INVALID_DSTATE;
uint16_t _TRACE_SLAVIO_TIMER_MEM_READL_DSTATE;
uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_DSTATE;
uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_DSTATE;
uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_DSTATE;
uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_DSTATE;
uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_DSTATE;
uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_DSTATE;
uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_DSTATE;
uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_DSTATE;
uint16_t _TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_DSTATE;
uint16_t _TRACE_GRLIB_GPTIMER_ENABLE_DSTATE;
uint16_t _TRACE_GRLIB_GPTIMER_DISABLED_DSTATE;
uint16_t _TRACE_GRLIB_GPTIMER_RESTART_DSTATE;
uint16_t _TRACE_GRLIB_GPTIMER_SET_SCALER_DSTATE;
uint16_t _TRACE_GRLIB_GPTIMER_HIT_DSTATE;
uint16_t _TRACE_GRLIB_GPTIMER_READL_DSTATE;
uint16_t _TRACE_GRLIB_GPTIMER_WRITEL_DSTATE;
uint16_t _TRACE_ASPEED_TIMER_CTRL_ENABLE_DSTATE;
uint16_t _TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_DSTATE;
uint16_t _TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_DSTATE;
uint16_t _TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_DSTATE;
uint16_t _TRACE_ASPEED_TIMER_SET_CTRL2_DSTATE;
uint16_t _TRACE_ASPEED_TIMER_SET_VALUE_DSTATE;
uint16_t _TRACE_ASPEED_TIMER_READ_DSTATE;
uint16_t _TRACE_SYSTICK_RELOAD_DSTATE;
uint16_t _TRACE_SYSTICK_TIMER_TICK_DSTATE;
uint16_t _TRACE_SYSTICK_READ_DSTATE;
uint16_t _TRACE_SYSTICK_WRITE_DSTATE;
uint16_t _TRACE_CMSDK_APB_TIMER_READ_DSTATE;
uint16_t _TRACE_CMSDK_APB_TIMER_WRITE_DSTATE;
uint16_t _TRACE_CMSDK_APB_TIMER_RESET_DSTATE;
uint16_t _TRACE_CMSDK_APB_DUALTIMER_READ_DSTATE;
uint16_t _TRACE_CMSDK_APB_DUALTIMER_WRITE_DSTATE;
uint16_t _TRACE_CMSDK_APB_DUALTIMER_RESET_DSTATE;
uint16_t _TRACE_PIT_IOPORT_READ_DSTATE;
uint16_t _TRACE_PIT_IOPORT_WRITE_DSTATE;
uint16_t _TRACE_IMX_GPT_SET_FREQ_DSTATE;
uint16_t _TRACE_IMX_GPT_READ_DSTATE;
uint16_t _TRACE_IMX_GPT_WRITE_DSTATE;
uint16_t _TRACE_IMX_GPT_TIMEOUT_DSTATE;
uint16_t _TRACE_NPCM7XX_TIMER_READ_DSTATE;
uint16_t _TRACE_NPCM7XX_TIMER_WRITE_DSTATE;
uint16_t _TRACE_NPCM7XX_TIMER_IRQ_DSTATE;
uint16_t _TRACE_NRF51_TIMER_READ_DSTATE;
uint16_t _TRACE_NRF51_TIMER_WRITE_DSTATE;
uint16_t _TRACE_NRF51_TIMER_SET_COUNT_DSTATE;
uint16_t _TRACE_BCM2835_SYSTMR_TIMER_EXPIRED_DSTATE;
uint16_t _TRACE_BCM2835_SYSTMR_IRQ_ACK_DSTATE;
uint16_t _TRACE_BCM2835_SYSTMR_READ_DSTATE;
uint16_t _TRACE_BCM2835_SYSTMR_WRITE_DSTATE;
uint16_t _TRACE_BCM2835_SYSTMR_RUN_DSTATE;
uint16_t _TRACE_AVR_TIMER16_READ_DSTATE;
uint16_t _TRACE_AVR_TIMER16_READ_IFR_DSTATE;
uint16_t _TRACE_AVR_TIMER16_READ_IMSK_DSTATE;
uint16_t _TRACE_AVR_TIMER16_WRITE_DSTATE;
uint16_t _TRACE_AVR_TIMER16_WRITE_IMSK_DSTATE;
uint16_t _TRACE_AVR_TIMER16_INTERRUPT_COUNT_DSTATE;
uint16_t _TRACE_AVR_TIMER16_INTERRUPT_OVERFLOW_DSTATE;
uint16_t _TRACE_AVR_TIMER16_NEXT_ALARM_DSTATE;
uint16_t _TRACE_AVR_TIMER16_CLKSRC_UPDATE_DSTATE;
uint16_t _TRACE_SSE_COUNTER_CONTROL_READ_DSTATE;
uint16_t _TRACE_SSE_COUNTER_CONTROL_WRITE_DSTATE;
uint16_t _TRACE_SSE_COUNTER_STATUS_READ_DSTATE;
uint16_t _TRACE_SSE_COUNTER_STATUS_WRITE_DSTATE;
uint16_t _TRACE_SSE_COUNTER_RESET_DSTATE;
uint16_t _TRACE_SSE_TIMER_READ_DSTATE;
uint16_t _TRACE_SSE_TIMER_WRITE_DSTATE;
uint16_t _TRACE_SSE_TIMER_RESET_DSTATE;
uint16_t _TRACE_SIFIVE_PWM_SET_ALARM_DSTATE;
uint16_t _TRACE_SIFIVE_PWM_INTERRUPT_DSTATE;
uint16_t _TRACE_SIFIVE_PWM_READ_DSTATE;
uint16_t _TRACE_SIFIVE_PWM_WRITE_DSTATE;
uint16_t _TRACE_SH_TIMER_START_STOP_DSTATE;
uint16_t _TRACE_SH_TIMER_READ_DSTATE;
uint16_t _TRACE_SH_TIMER_WRITE_DSTATE;
uint16_t _TRACE_HPET_TIMER_ID_OUT_OF_RANGE_DSTATE;
uint16_t _TRACE_HPET_INVALID_HPET_CFG_DSTATE;
uint16_t _TRACE_HPET_RAM_READ_DSTATE;
uint16_t _TRACE_HPET_RAM_READ_READING_COUNTER_DSTATE;
uint16_t _TRACE_HPET_RAM_READ_INVALID_DSTATE;
uint16_t _TRACE_HPET_RAM_WRITE_DSTATE;
uint16_t _TRACE_HPET_RAM_WRITE_TIMER_ID_DSTATE;
uint16_t _TRACE_HPET_RAM_WRITE_TN_CFG_DSTATE;
uint16_t _TRACE_HPET_RAM_WRITE_TN_CMP_DSTATE;
uint16_t _TRACE_HPET_RAM_WRITE_INVALID_TN_CMP_DSTATE;
uint16_t _TRACE_HPET_RAM_WRITE_INVALID_DSTATE;
uint16_t _TRACE_HPET_RAM_WRITE_COUNTER_WRITE_WHILE_ENABLED_DSTATE;
uint16_t _TRACE_HPET_RAM_WRITE_COUNTER_WRITTEN_DSTATE;
TraceEvent _TRACE_SLAVIO_TIMER_GET_OUT_EVENT = {
    .id = 0,
    .name = "slavio_timer_get_out",
    .sstate = TRACE_SLAVIO_TIMER_GET_OUT_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_GET_OUT_DSTATE
};
TraceEvent _TRACE_SLAVIO_TIMER_IRQ_EVENT = {
    .id = 0,
    .name = "slavio_timer_irq",
    .sstate = TRACE_SLAVIO_TIMER_IRQ_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_IRQ_DSTATE
};
TraceEvent _TRACE_SLAVIO_TIMER_MEM_READL_INVALID_EVENT = {
    .id = 0,
    .name = "slavio_timer_mem_readl_invalid",
    .sstate = TRACE_SLAVIO_TIMER_MEM_READL_INVALID_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_MEM_READL_INVALID_DSTATE
};
TraceEvent _TRACE_SLAVIO_TIMER_MEM_READL_EVENT = {
    .id = 0,
    .name = "slavio_timer_mem_readl",
    .sstate = TRACE_SLAVIO_TIMER_MEM_READL_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_MEM_READL_DSTATE
};
TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_EVENT = {
    .id = 0,
    .name = "slavio_timer_mem_writel",
    .sstate = TRACE_SLAVIO_TIMER_MEM_WRITEL_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_MEM_WRITEL_DSTATE
};
TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_EVENT = {
    .id = 0,
    .name = "slavio_timer_mem_writel_limit",
    .sstate = TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_DSTATE
};
TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_EVENT = {
    .id = 0,
    .name = "slavio_timer_mem_writel_counter_invalid",
    .sstate = TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_DSTATE
};
TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_EVENT = {
    .id = 0,
    .name = "slavio_timer_mem_writel_status_start",
    .sstate = TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_DSTATE
};
TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_EVENT = {
    .id = 0,
    .name = "slavio_timer_mem_writel_status_stop",
    .sstate = TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_DSTATE
};
TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_EVENT = {
    .id = 0,
    .name = "slavio_timer_mem_writel_mode_user",
    .sstate = TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_DSTATE
};
TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_EVENT = {
    .id = 0,
    .name = "slavio_timer_mem_writel_mode_counter",
    .sstate = TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_DSTATE
};
TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_EVENT = {
    .id = 0,
    .name = "slavio_timer_mem_writel_mode_invalid",
    .sstate = TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_DSTATE
};
TraceEvent _TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_EVENT = {
    .id = 0,
    .name = "slavio_timer_mem_writel_invalid",
    .sstate = TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_ENABLED,
    .dstate = &_TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_DSTATE
};
TraceEvent _TRACE_GRLIB_GPTIMER_ENABLE_EVENT = {
    .id = 0,
    .name = "grlib_gptimer_enable",
    .sstate = TRACE_GRLIB_GPTIMER_ENABLE_ENABLED,
    .dstate = &_TRACE_GRLIB_GPTIMER_ENABLE_DSTATE
};
TraceEvent _TRACE_GRLIB_GPTIMER_DISABLED_EVENT = {
    .id = 0,
    .name = "grlib_gptimer_disabled",
    .sstate = TRACE_GRLIB_GPTIMER_DISABLED_ENABLED,
    .dstate = &_TRACE_GRLIB_GPTIMER_DISABLED_DSTATE
};
TraceEvent _TRACE_GRLIB_GPTIMER_RESTART_EVENT = {
    .id = 0,
    .name = "grlib_gptimer_restart",
    .sstate = TRACE_GRLIB_GPTIMER_RESTART_ENABLED,
    .dstate = &_TRACE_GRLIB_GPTIMER_RESTART_DSTATE
};
TraceEvent _TRACE_GRLIB_GPTIMER_SET_SCALER_EVENT = {
    .id = 0,
    .name = "grlib_gptimer_set_scaler",
    .sstate = TRACE_GRLIB_GPTIMER_SET_SCALER_ENABLED,
    .dstate = &_TRACE_GRLIB_GPTIMER_SET_SCALER_DSTATE
};
TraceEvent _TRACE_GRLIB_GPTIMER_HIT_EVENT = {
    .id = 0,
    .name = "grlib_gptimer_hit",
    .sstate = TRACE_GRLIB_GPTIMER_HIT_ENABLED,
    .dstate = &_TRACE_GRLIB_GPTIMER_HIT_DSTATE
};
TraceEvent _TRACE_GRLIB_GPTIMER_READL_EVENT = {
    .id = 0,
    .name = "grlib_gptimer_readl",
    .sstate = TRACE_GRLIB_GPTIMER_READL_ENABLED,
    .dstate = &_TRACE_GRLIB_GPTIMER_READL_DSTATE
};
TraceEvent _TRACE_GRLIB_GPTIMER_WRITEL_EVENT = {
    .id = 0,
    .name = "grlib_gptimer_writel",
    .sstate = TRACE_GRLIB_GPTIMER_WRITEL_ENABLED,
    .dstate = &_TRACE_GRLIB_GPTIMER_WRITEL_DSTATE
};
TraceEvent _TRACE_ASPEED_TIMER_CTRL_ENABLE_EVENT = {
    .id = 0,
    .name = "aspeed_timer_ctrl_enable",
    .sstate = TRACE_ASPEED_TIMER_CTRL_ENABLE_ENABLED,
    .dstate = &_TRACE_ASPEED_TIMER_CTRL_ENABLE_DSTATE
};
TraceEvent _TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_EVENT = {
    .id = 0,
    .name = "aspeed_timer_ctrl_external_clock",
    .sstate = TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_ENABLED,
    .dstate = &_TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_DSTATE
};
TraceEvent _TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_EVENT = {
    .id = 0,
    .name = "aspeed_timer_ctrl_overflow_interrupt",
    .sstate = TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_ENABLED,
    .dstate = &_TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_DSTATE
};
TraceEvent _TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_EVENT = {
    .id = 0,
    .name = "aspeed_timer_ctrl_pulse_enable",
    .sstate = TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_ENABLED,
    .dstate = &_TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_DSTATE
};
TraceEvent _TRACE_ASPEED_TIMER_SET_CTRL2_EVENT = {
    .id = 0,
    .name = "aspeed_timer_set_ctrl2",
    .sstate = TRACE_ASPEED_TIMER_SET_CTRL2_ENABLED,
    .dstate = &_TRACE_ASPEED_TIMER_SET_CTRL2_DSTATE
};
TraceEvent _TRACE_ASPEED_TIMER_SET_VALUE_EVENT = {
    .id = 0,
    .name = "aspeed_timer_set_value",
    .sstate = TRACE_ASPEED_TIMER_SET_VALUE_ENABLED,
    .dstate = &_TRACE_ASPEED_TIMER_SET_VALUE_DSTATE
};
TraceEvent _TRACE_ASPEED_TIMER_READ_EVENT = {
    .id = 0,
    .name = "aspeed_timer_read",
    .sstate = TRACE_ASPEED_TIMER_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_TIMER_READ_DSTATE
};
TraceEvent _TRACE_SYSTICK_RELOAD_EVENT = {
    .id = 0,
    .name = "systick_reload",
    .sstate = TRACE_SYSTICK_RELOAD_ENABLED,
    .dstate = &_TRACE_SYSTICK_RELOAD_DSTATE
};
TraceEvent _TRACE_SYSTICK_TIMER_TICK_EVENT = {
    .id = 0,
    .name = "systick_timer_tick",
    .sstate = TRACE_SYSTICK_TIMER_TICK_ENABLED,
    .dstate = &_TRACE_SYSTICK_TIMER_TICK_DSTATE
};
TraceEvent _TRACE_SYSTICK_READ_EVENT = {
    .id = 0,
    .name = "systick_read",
    .sstate = TRACE_SYSTICK_READ_ENABLED,
    .dstate = &_TRACE_SYSTICK_READ_DSTATE
};
TraceEvent _TRACE_SYSTICK_WRITE_EVENT = {
    .id = 0,
    .name = "systick_write",
    .sstate = TRACE_SYSTICK_WRITE_ENABLED,
    .dstate = &_TRACE_SYSTICK_WRITE_DSTATE
};
TraceEvent _TRACE_CMSDK_APB_TIMER_READ_EVENT = {
    .id = 0,
    .name = "cmsdk_apb_timer_read",
    .sstate = TRACE_CMSDK_APB_TIMER_READ_ENABLED,
    .dstate = &_TRACE_CMSDK_APB_TIMER_READ_DSTATE
};
TraceEvent _TRACE_CMSDK_APB_TIMER_WRITE_EVENT = {
    .id = 0,
    .name = "cmsdk_apb_timer_write",
    .sstate = TRACE_CMSDK_APB_TIMER_WRITE_ENABLED,
    .dstate = &_TRACE_CMSDK_APB_TIMER_WRITE_DSTATE
};
TraceEvent _TRACE_CMSDK_APB_TIMER_RESET_EVENT = {
    .id = 0,
    .name = "cmsdk_apb_timer_reset",
    .sstate = TRACE_CMSDK_APB_TIMER_RESET_ENABLED,
    .dstate = &_TRACE_CMSDK_APB_TIMER_RESET_DSTATE
};
TraceEvent _TRACE_CMSDK_APB_DUALTIMER_READ_EVENT = {
    .id = 0,
    .name = "cmsdk_apb_dualtimer_read",
    .sstate = TRACE_CMSDK_APB_DUALTIMER_READ_ENABLED,
    .dstate = &_TRACE_CMSDK_APB_DUALTIMER_READ_DSTATE
};
TraceEvent _TRACE_CMSDK_APB_DUALTIMER_WRITE_EVENT = {
    .id = 0,
    .name = "cmsdk_apb_dualtimer_write",
    .sstate = TRACE_CMSDK_APB_DUALTIMER_WRITE_ENABLED,
    .dstate = &_TRACE_CMSDK_APB_DUALTIMER_WRITE_DSTATE
};
TraceEvent _TRACE_CMSDK_APB_DUALTIMER_RESET_EVENT = {
    .id = 0,
    .name = "cmsdk_apb_dualtimer_reset",
    .sstate = TRACE_CMSDK_APB_DUALTIMER_RESET_ENABLED,
    .dstate = &_TRACE_CMSDK_APB_DUALTIMER_RESET_DSTATE
};
TraceEvent _TRACE_PIT_IOPORT_READ_EVENT = {
    .id = 0,
    .name = "pit_ioport_read",
    .sstate = TRACE_PIT_IOPORT_READ_ENABLED,
    .dstate = &_TRACE_PIT_IOPORT_READ_DSTATE
};
TraceEvent _TRACE_PIT_IOPORT_WRITE_EVENT = {
    .id = 0,
    .name = "pit_ioport_write",
    .sstate = TRACE_PIT_IOPORT_WRITE_ENABLED,
    .dstate = &_TRACE_PIT_IOPORT_WRITE_DSTATE
};
TraceEvent _TRACE_IMX_GPT_SET_FREQ_EVENT = {
    .id = 0,
    .name = "imx_gpt_set_freq",
    .sstate = TRACE_IMX_GPT_SET_FREQ_ENABLED,
    .dstate = &_TRACE_IMX_GPT_SET_FREQ_DSTATE
};
TraceEvent _TRACE_IMX_GPT_READ_EVENT = {
    .id = 0,
    .name = "imx_gpt_read",
    .sstate = TRACE_IMX_GPT_READ_ENABLED,
    .dstate = &_TRACE_IMX_GPT_READ_DSTATE
};
TraceEvent _TRACE_IMX_GPT_WRITE_EVENT = {
    .id = 0,
    .name = "imx_gpt_write",
    .sstate = TRACE_IMX_GPT_WRITE_ENABLED,
    .dstate = &_TRACE_IMX_GPT_WRITE_DSTATE
};
TraceEvent _TRACE_IMX_GPT_TIMEOUT_EVENT = {
    .id = 0,
    .name = "imx_gpt_timeout",
    .sstate = TRACE_IMX_GPT_TIMEOUT_ENABLED,
    .dstate = &_TRACE_IMX_GPT_TIMEOUT_DSTATE
};
TraceEvent _TRACE_NPCM7XX_TIMER_READ_EVENT = {
    .id = 0,
    .name = "npcm7xx_timer_read",
    .sstate = TRACE_NPCM7XX_TIMER_READ_ENABLED,
    .dstate = &_TRACE_NPCM7XX_TIMER_READ_DSTATE
};
TraceEvent _TRACE_NPCM7XX_TIMER_WRITE_EVENT = {
    .id = 0,
    .name = "npcm7xx_timer_write",
    .sstate = TRACE_NPCM7XX_TIMER_WRITE_ENABLED,
    .dstate = &_TRACE_NPCM7XX_TIMER_WRITE_DSTATE
};
TraceEvent _TRACE_NPCM7XX_TIMER_IRQ_EVENT = {
    .id = 0,
    .name = "npcm7xx_timer_irq",
    .sstate = TRACE_NPCM7XX_TIMER_IRQ_ENABLED,
    .dstate = &_TRACE_NPCM7XX_TIMER_IRQ_DSTATE
};
TraceEvent _TRACE_NRF51_TIMER_READ_EVENT = {
    .id = 0,
    .name = "nrf51_timer_read",
    .sstate = TRACE_NRF51_TIMER_READ_ENABLED,
    .dstate = &_TRACE_NRF51_TIMER_READ_DSTATE
};
TraceEvent _TRACE_NRF51_TIMER_WRITE_EVENT = {
    .id = 0,
    .name = "nrf51_timer_write",
    .sstate = TRACE_NRF51_TIMER_WRITE_ENABLED,
    .dstate = &_TRACE_NRF51_TIMER_WRITE_DSTATE
};
TraceEvent _TRACE_NRF51_TIMER_SET_COUNT_EVENT = {
    .id = 0,
    .name = "nrf51_timer_set_count",
    .sstate = TRACE_NRF51_TIMER_SET_COUNT_ENABLED,
    .dstate = &_TRACE_NRF51_TIMER_SET_COUNT_DSTATE
};
TraceEvent _TRACE_BCM2835_SYSTMR_TIMER_EXPIRED_EVENT = {
    .id = 0,
    .name = "bcm2835_systmr_timer_expired",
    .sstate = TRACE_BCM2835_SYSTMR_TIMER_EXPIRED_ENABLED,
    .dstate = &_TRACE_BCM2835_SYSTMR_TIMER_EXPIRED_DSTATE
};
TraceEvent _TRACE_BCM2835_SYSTMR_IRQ_ACK_EVENT = {
    .id = 0,
    .name = "bcm2835_systmr_irq_ack",
    .sstate = TRACE_BCM2835_SYSTMR_IRQ_ACK_ENABLED,
    .dstate = &_TRACE_BCM2835_SYSTMR_IRQ_ACK_DSTATE
};
TraceEvent _TRACE_BCM2835_SYSTMR_READ_EVENT = {
    .id = 0,
    .name = "bcm2835_systmr_read",
    .sstate = TRACE_BCM2835_SYSTMR_READ_ENABLED,
    .dstate = &_TRACE_BCM2835_SYSTMR_READ_DSTATE
};
TraceEvent _TRACE_BCM2835_SYSTMR_WRITE_EVENT = {
    .id = 0,
    .name = "bcm2835_systmr_write",
    .sstate = TRACE_BCM2835_SYSTMR_WRITE_ENABLED,
    .dstate = &_TRACE_BCM2835_SYSTMR_WRITE_DSTATE
};
TraceEvent _TRACE_BCM2835_SYSTMR_RUN_EVENT = {
    .id = 0,
    .name = "bcm2835_systmr_run",
    .sstate = TRACE_BCM2835_SYSTMR_RUN_ENABLED,
    .dstate = &_TRACE_BCM2835_SYSTMR_RUN_DSTATE
};
TraceEvent _TRACE_AVR_TIMER16_READ_EVENT = {
    .id = 0,
    .name = "avr_timer16_read",
    .sstate = TRACE_AVR_TIMER16_READ_ENABLED,
    .dstate = &_TRACE_AVR_TIMER16_READ_DSTATE
};
TraceEvent _TRACE_AVR_TIMER16_READ_IFR_EVENT = {
    .id = 0,
    .name = "avr_timer16_read_ifr",
    .sstate = TRACE_AVR_TIMER16_READ_IFR_ENABLED,
    .dstate = &_TRACE_AVR_TIMER16_READ_IFR_DSTATE
};
TraceEvent _TRACE_AVR_TIMER16_READ_IMSK_EVENT = {
    .id = 0,
    .name = "avr_timer16_read_imsk",
    .sstate = TRACE_AVR_TIMER16_READ_IMSK_ENABLED,
    .dstate = &_TRACE_AVR_TIMER16_READ_IMSK_DSTATE
};
TraceEvent _TRACE_AVR_TIMER16_WRITE_EVENT = {
    .id = 0,
    .name = "avr_timer16_write",
    .sstate = TRACE_AVR_TIMER16_WRITE_ENABLED,
    .dstate = &_TRACE_AVR_TIMER16_WRITE_DSTATE
};
TraceEvent _TRACE_AVR_TIMER16_WRITE_IMSK_EVENT = {
    .id = 0,
    .name = "avr_timer16_write_imsk",
    .sstate = TRACE_AVR_TIMER16_WRITE_IMSK_ENABLED,
    .dstate = &_TRACE_AVR_TIMER16_WRITE_IMSK_DSTATE
};
TraceEvent _TRACE_AVR_TIMER16_INTERRUPT_COUNT_EVENT = {
    .id = 0,
    .name = "avr_timer16_interrupt_count",
    .sstate = TRACE_AVR_TIMER16_INTERRUPT_COUNT_ENABLED,
    .dstate = &_TRACE_AVR_TIMER16_INTERRUPT_COUNT_DSTATE
};
TraceEvent _TRACE_AVR_TIMER16_INTERRUPT_OVERFLOW_EVENT = {
    .id = 0,
    .name = "avr_timer16_interrupt_overflow",
    .sstate = TRACE_AVR_TIMER16_INTERRUPT_OVERFLOW_ENABLED,
    .dstate = &_TRACE_AVR_TIMER16_INTERRUPT_OVERFLOW_DSTATE
};
TraceEvent _TRACE_AVR_TIMER16_NEXT_ALARM_EVENT = {
    .id = 0,
    .name = "avr_timer16_next_alarm",
    .sstate = TRACE_AVR_TIMER16_NEXT_ALARM_ENABLED,
    .dstate = &_TRACE_AVR_TIMER16_NEXT_ALARM_DSTATE
};
TraceEvent _TRACE_AVR_TIMER16_CLKSRC_UPDATE_EVENT = {
    .id = 0,
    .name = "avr_timer16_clksrc_update",
    .sstate = TRACE_AVR_TIMER16_CLKSRC_UPDATE_ENABLED,
    .dstate = &_TRACE_AVR_TIMER16_CLKSRC_UPDATE_DSTATE
};
TraceEvent _TRACE_SSE_COUNTER_CONTROL_READ_EVENT = {
    .id = 0,
    .name = "sse_counter_control_read",
    .sstate = TRACE_SSE_COUNTER_CONTROL_READ_ENABLED,
    .dstate = &_TRACE_SSE_COUNTER_CONTROL_READ_DSTATE
};
TraceEvent _TRACE_SSE_COUNTER_CONTROL_WRITE_EVENT = {
    .id = 0,
    .name = "sse_counter_control_write",
    .sstate = TRACE_SSE_COUNTER_CONTROL_WRITE_ENABLED,
    .dstate = &_TRACE_SSE_COUNTER_CONTROL_WRITE_DSTATE
};
TraceEvent _TRACE_SSE_COUNTER_STATUS_READ_EVENT = {
    .id = 0,
    .name = "sse_counter_status_read",
    .sstate = TRACE_SSE_COUNTER_STATUS_READ_ENABLED,
    .dstate = &_TRACE_SSE_COUNTER_STATUS_READ_DSTATE
};
TraceEvent _TRACE_SSE_COUNTER_STATUS_WRITE_EVENT = {
    .id = 0,
    .name = "sse_counter_status_write",
    .sstate = TRACE_SSE_COUNTER_STATUS_WRITE_ENABLED,
    .dstate = &_TRACE_SSE_COUNTER_STATUS_WRITE_DSTATE
};
TraceEvent _TRACE_SSE_COUNTER_RESET_EVENT = {
    .id = 0,
    .name = "sse_counter_reset",
    .sstate = TRACE_SSE_COUNTER_RESET_ENABLED,
    .dstate = &_TRACE_SSE_COUNTER_RESET_DSTATE
};
TraceEvent _TRACE_SSE_TIMER_READ_EVENT = {
    .id = 0,
    .name = "sse_timer_read",
    .sstate = TRACE_SSE_TIMER_READ_ENABLED,
    .dstate = &_TRACE_SSE_TIMER_READ_DSTATE
};
TraceEvent _TRACE_SSE_TIMER_WRITE_EVENT = {
    .id = 0,
    .name = "sse_timer_write",
    .sstate = TRACE_SSE_TIMER_WRITE_ENABLED,
    .dstate = &_TRACE_SSE_TIMER_WRITE_DSTATE
};
TraceEvent _TRACE_SSE_TIMER_RESET_EVENT = {
    .id = 0,
    .name = "sse_timer_reset",
    .sstate = TRACE_SSE_TIMER_RESET_ENABLED,
    .dstate = &_TRACE_SSE_TIMER_RESET_DSTATE
};
TraceEvent _TRACE_SIFIVE_PWM_SET_ALARM_EVENT = {
    .id = 0,
    .name = "sifive_pwm_set_alarm",
    .sstate = TRACE_SIFIVE_PWM_SET_ALARM_ENABLED,
    .dstate = &_TRACE_SIFIVE_PWM_SET_ALARM_DSTATE
};
TraceEvent _TRACE_SIFIVE_PWM_INTERRUPT_EVENT = {
    .id = 0,
    .name = "sifive_pwm_interrupt",
    .sstate = TRACE_SIFIVE_PWM_INTERRUPT_ENABLED,
    .dstate = &_TRACE_SIFIVE_PWM_INTERRUPT_DSTATE
};
TraceEvent _TRACE_SIFIVE_PWM_READ_EVENT = {
    .id = 0,
    .name = "sifive_pwm_read",
    .sstate = TRACE_SIFIVE_PWM_READ_ENABLED,
    .dstate = &_TRACE_SIFIVE_PWM_READ_DSTATE
};
TraceEvent _TRACE_SIFIVE_PWM_WRITE_EVENT = {
    .id = 0,
    .name = "sifive_pwm_write",
    .sstate = TRACE_SIFIVE_PWM_WRITE_ENABLED,
    .dstate = &_TRACE_SIFIVE_PWM_WRITE_DSTATE
};
TraceEvent _TRACE_SH_TIMER_START_STOP_EVENT = {
    .id = 0,
    .name = "sh_timer_start_stop",
    .sstate = TRACE_SH_TIMER_START_STOP_ENABLED,
    .dstate = &_TRACE_SH_TIMER_START_STOP_DSTATE
};
TraceEvent _TRACE_SH_TIMER_READ_EVENT = {
    .id = 0,
    .name = "sh_timer_read",
    .sstate = TRACE_SH_TIMER_READ_ENABLED,
    .dstate = &_TRACE_SH_TIMER_READ_DSTATE
};
TraceEvent _TRACE_SH_TIMER_WRITE_EVENT = {
    .id = 0,
    .name = "sh_timer_write",
    .sstate = TRACE_SH_TIMER_WRITE_ENABLED,
    .dstate = &_TRACE_SH_TIMER_WRITE_DSTATE
};
TraceEvent _TRACE_HPET_TIMER_ID_OUT_OF_RANGE_EVENT = {
    .id = 0,
    .name = "hpet_timer_id_out_of_range",
    .sstate = TRACE_HPET_TIMER_ID_OUT_OF_RANGE_ENABLED,
    .dstate = &_TRACE_HPET_TIMER_ID_OUT_OF_RANGE_DSTATE
};
TraceEvent _TRACE_HPET_INVALID_HPET_CFG_EVENT = {
    .id = 0,
    .name = "hpet_invalid_hpet_cfg",
    .sstate = TRACE_HPET_INVALID_HPET_CFG_ENABLED,
    .dstate = &_TRACE_HPET_INVALID_HPET_CFG_DSTATE
};
TraceEvent _TRACE_HPET_RAM_READ_EVENT = {
    .id = 0,
    .name = "hpet_ram_read",
    .sstate = TRACE_HPET_RAM_READ_ENABLED,
    .dstate = &_TRACE_HPET_RAM_READ_DSTATE
};
TraceEvent _TRACE_HPET_RAM_READ_READING_COUNTER_EVENT = {
    .id = 0,
    .name = "hpet_ram_read_reading_counter",
    .sstate = TRACE_HPET_RAM_READ_READING_COUNTER_ENABLED,
    .dstate = &_TRACE_HPET_RAM_READ_READING_COUNTER_DSTATE
};
TraceEvent _TRACE_HPET_RAM_READ_INVALID_EVENT = {
    .id = 0,
    .name = "hpet_ram_read_invalid",
    .sstate = TRACE_HPET_RAM_READ_INVALID_ENABLED,
    .dstate = &_TRACE_HPET_RAM_READ_INVALID_DSTATE
};
TraceEvent _TRACE_HPET_RAM_WRITE_EVENT = {
    .id = 0,
    .name = "hpet_ram_write",
    .sstate = TRACE_HPET_RAM_WRITE_ENABLED,
    .dstate = &_TRACE_HPET_RAM_WRITE_DSTATE
};
TraceEvent _TRACE_HPET_RAM_WRITE_TIMER_ID_EVENT = {
    .id = 0,
    .name = "hpet_ram_write_timer_id",
    .sstate = TRACE_HPET_RAM_WRITE_TIMER_ID_ENABLED,
    .dstate = &_TRACE_HPET_RAM_WRITE_TIMER_ID_DSTATE
};
TraceEvent _TRACE_HPET_RAM_WRITE_TN_CFG_EVENT = {
    .id = 0,
    .name = "hpet_ram_write_tn_cfg",
    .sstate = TRACE_HPET_RAM_WRITE_TN_CFG_ENABLED,
    .dstate = &_TRACE_HPET_RAM_WRITE_TN_CFG_DSTATE
};
TraceEvent _TRACE_HPET_RAM_WRITE_TN_CMP_EVENT = {
    .id = 0,
    .name = "hpet_ram_write_tn_cmp",
    .sstate = TRACE_HPET_RAM_WRITE_TN_CMP_ENABLED,
    .dstate = &_TRACE_HPET_RAM_WRITE_TN_CMP_DSTATE
};
TraceEvent _TRACE_HPET_RAM_WRITE_INVALID_TN_CMP_EVENT = {
    .id = 0,
    .name = "hpet_ram_write_invalid_tn_cmp",
    .sstate = TRACE_HPET_RAM_WRITE_INVALID_TN_CMP_ENABLED,
    .dstate = &_TRACE_HPET_RAM_WRITE_INVALID_TN_CMP_DSTATE
};
TraceEvent _TRACE_HPET_RAM_WRITE_INVALID_EVENT = {
    .id = 0,
    .name = "hpet_ram_write_invalid",
    .sstate = TRACE_HPET_RAM_WRITE_INVALID_ENABLED,
    .dstate = &_TRACE_HPET_RAM_WRITE_INVALID_DSTATE
};
TraceEvent _TRACE_HPET_RAM_WRITE_COUNTER_WRITE_WHILE_ENABLED_EVENT = {
    .id = 0,
    .name = "hpet_ram_write_counter_write_while_enabled",
    .sstate = TRACE_HPET_RAM_WRITE_COUNTER_WRITE_WHILE_ENABLED_ENABLED,
    .dstate = &_TRACE_HPET_RAM_WRITE_COUNTER_WRITE_WHILE_ENABLED_DSTATE
};
TraceEvent _TRACE_HPET_RAM_WRITE_COUNTER_WRITTEN_EVENT = {
    .id = 0,
    .name = "hpet_ram_write_counter_written",
    .sstate = TRACE_HPET_RAM_WRITE_COUNTER_WRITTEN_ENABLED,
    .dstate = &_TRACE_HPET_RAM_WRITE_COUNTER_WRITTEN_DSTATE
};
TraceEvent *hw_timer_trace_events[] = {
    &_TRACE_SLAVIO_TIMER_GET_OUT_EVENT,
    &_TRACE_SLAVIO_TIMER_IRQ_EVENT,
    &_TRACE_SLAVIO_TIMER_MEM_READL_INVALID_EVENT,
    &_TRACE_SLAVIO_TIMER_MEM_READL_EVENT,
    &_TRACE_SLAVIO_TIMER_MEM_WRITEL_EVENT,
    &_TRACE_SLAVIO_TIMER_MEM_WRITEL_LIMIT_EVENT,
    &_TRACE_SLAVIO_TIMER_MEM_WRITEL_COUNTER_INVALID_EVENT,
    &_TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_START_EVENT,
    &_TRACE_SLAVIO_TIMER_MEM_WRITEL_STATUS_STOP_EVENT,
    &_TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_USER_EVENT,
    &_TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_COUNTER_EVENT,
    &_TRACE_SLAVIO_TIMER_MEM_WRITEL_MODE_INVALID_EVENT,
    &_TRACE_SLAVIO_TIMER_MEM_WRITEL_INVALID_EVENT,
    &_TRACE_GRLIB_GPTIMER_ENABLE_EVENT,
    &_TRACE_GRLIB_GPTIMER_DISABLED_EVENT,
    &_TRACE_GRLIB_GPTIMER_RESTART_EVENT,
    &_TRACE_GRLIB_GPTIMER_SET_SCALER_EVENT,
    &_TRACE_GRLIB_GPTIMER_HIT_EVENT,
    &_TRACE_GRLIB_GPTIMER_READL_EVENT,
    &_TRACE_GRLIB_GPTIMER_WRITEL_EVENT,
    &_TRACE_ASPEED_TIMER_CTRL_ENABLE_EVENT,
    &_TRACE_ASPEED_TIMER_CTRL_EXTERNAL_CLOCK_EVENT,
    &_TRACE_ASPEED_TIMER_CTRL_OVERFLOW_INTERRUPT_EVENT,
    &_TRACE_ASPEED_TIMER_CTRL_PULSE_ENABLE_EVENT,
    &_TRACE_ASPEED_TIMER_SET_CTRL2_EVENT,
    &_TRACE_ASPEED_TIMER_SET_VALUE_EVENT,
    &_TRACE_ASPEED_TIMER_READ_EVENT,
    &_TRACE_SYSTICK_RELOAD_EVENT,
    &_TRACE_SYSTICK_TIMER_TICK_EVENT,
    &_TRACE_SYSTICK_READ_EVENT,
    &_TRACE_SYSTICK_WRITE_EVENT,
    &_TRACE_CMSDK_APB_TIMER_READ_EVENT,
    &_TRACE_CMSDK_APB_TIMER_WRITE_EVENT,
    &_TRACE_CMSDK_APB_TIMER_RESET_EVENT,
    &_TRACE_CMSDK_APB_DUALTIMER_READ_EVENT,
    &_TRACE_CMSDK_APB_DUALTIMER_WRITE_EVENT,
    &_TRACE_CMSDK_APB_DUALTIMER_RESET_EVENT,
    &_TRACE_PIT_IOPORT_READ_EVENT,
    &_TRACE_PIT_IOPORT_WRITE_EVENT,
    &_TRACE_IMX_GPT_SET_FREQ_EVENT,
    &_TRACE_IMX_GPT_READ_EVENT,
    &_TRACE_IMX_GPT_WRITE_EVENT,
    &_TRACE_IMX_GPT_TIMEOUT_EVENT,
    &_TRACE_NPCM7XX_TIMER_READ_EVENT,
    &_TRACE_NPCM7XX_TIMER_WRITE_EVENT,
    &_TRACE_NPCM7XX_TIMER_IRQ_EVENT,
    &_TRACE_NRF51_TIMER_READ_EVENT,
    &_TRACE_NRF51_TIMER_WRITE_EVENT,
    &_TRACE_NRF51_TIMER_SET_COUNT_EVENT,
    &_TRACE_BCM2835_SYSTMR_TIMER_EXPIRED_EVENT,
    &_TRACE_BCM2835_SYSTMR_IRQ_ACK_EVENT,
    &_TRACE_BCM2835_SYSTMR_READ_EVENT,
    &_TRACE_BCM2835_SYSTMR_WRITE_EVENT,
    &_TRACE_BCM2835_SYSTMR_RUN_EVENT,
    &_TRACE_AVR_TIMER16_READ_EVENT,
    &_TRACE_AVR_TIMER16_READ_IFR_EVENT,
    &_TRACE_AVR_TIMER16_READ_IMSK_EVENT,
    &_TRACE_AVR_TIMER16_WRITE_EVENT,
    &_TRACE_AVR_TIMER16_WRITE_IMSK_EVENT,
    &_TRACE_AVR_TIMER16_INTERRUPT_COUNT_EVENT,
    &_TRACE_AVR_TIMER16_INTERRUPT_OVERFLOW_EVENT,
    &_TRACE_AVR_TIMER16_NEXT_ALARM_EVENT,
    &_TRACE_AVR_TIMER16_CLKSRC_UPDATE_EVENT,
    &_TRACE_SSE_COUNTER_CONTROL_READ_EVENT,
    &_TRACE_SSE_COUNTER_CONTROL_WRITE_EVENT,
    &_TRACE_SSE_COUNTER_STATUS_READ_EVENT,
    &_TRACE_SSE_COUNTER_STATUS_WRITE_EVENT,
    &_TRACE_SSE_COUNTER_RESET_EVENT,
    &_TRACE_SSE_TIMER_READ_EVENT,
    &_TRACE_SSE_TIMER_WRITE_EVENT,
    &_TRACE_SSE_TIMER_RESET_EVENT,
    &_TRACE_SIFIVE_PWM_SET_ALARM_EVENT,
    &_TRACE_SIFIVE_PWM_INTERRUPT_EVENT,
    &_TRACE_SIFIVE_PWM_READ_EVENT,
    &_TRACE_SIFIVE_PWM_WRITE_EVENT,
    &_TRACE_SH_TIMER_START_STOP_EVENT,
    &_TRACE_SH_TIMER_READ_EVENT,
    &_TRACE_SH_TIMER_WRITE_EVENT,
    &_TRACE_HPET_TIMER_ID_OUT_OF_RANGE_EVENT,
    &_TRACE_HPET_INVALID_HPET_CFG_EVENT,
    &_TRACE_HPET_RAM_READ_EVENT,
    &_TRACE_HPET_RAM_READ_READING_COUNTER_EVENT,
    &_TRACE_HPET_RAM_READ_INVALID_EVENT,
    &_TRACE_HPET_RAM_WRITE_EVENT,
    &_TRACE_HPET_RAM_WRITE_TIMER_ID_EVENT,
    &_TRACE_HPET_RAM_WRITE_TN_CFG_EVENT,
    &_TRACE_HPET_RAM_WRITE_TN_CMP_EVENT,
    &_TRACE_HPET_RAM_WRITE_INVALID_TN_CMP_EVENT,
    &_TRACE_HPET_RAM_WRITE_INVALID_EVENT,
    &_TRACE_HPET_RAM_WRITE_COUNTER_WRITE_WHILE_ENABLED_EVENT,
    &_TRACE_HPET_RAM_WRITE_COUNTER_WRITTEN_EVENT,
  NULL,
};

static void trace_hw_timer_register_events(void)
{
    trace_event_register_group(hw_timer_trace_events);
}
trace_init(trace_hw_timer_register_events)
