/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_i386.h"

uint16_t _TRACE_X86_IOMMU_IEC_NOTIFY_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_CC_DOMAIN_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_CC_GLOBAL_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_CC_DEVICE_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_CC_DEVICES_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_IOTLB_GLOBAL_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_IOTLB_DOMAIN_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_IOTLB_PAGES_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_IOTLB_PASID_PAGES_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_IOTLB_PASID_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_WAIT_SW_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_WAIT_IRQ_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_WAIT_WRITE_FAIL_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_IEC_DSTATE;
uint16_t _TRACE_VTD_INV_QI_ENABLE_DSTATE;
uint16_t _TRACE_VTD_INV_QI_SETUP_DSTATE;
uint16_t _TRACE_VTD_INV_QI_HEAD_DSTATE;
uint16_t _TRACE_VTD_INV_QI_TAIL_DSTATE;
uint16_t _TRACE_VTD_INV_QI_FETCH_DSTATE;
uint16_t _TRACE_VTD_CONTEXT_CACHE_RESET_DSTATE;
uint16_t _TRACE_VTD_PASID_CACHE_RESET_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_PASID_CACHE_GSI_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_PASID_CACHE_DSI_DSTATE;
uint16_t _TRACE_VTD_INV_DESC_PASID_CACHE_PSI_DSTATE;
uint16_t _TRACE_VTD_RE_NOT_PRESENT_DSTATE;
uint16_t _TRACE_VTD_CE_NOT_PRESENT_DSTATE;
uint16_t _TRACE_VTD_IOTLB_PAGE_HIT_DSTATE;
uint16_t _TRACE_VTD_IOTLB_PAGE_UPDATE_DSTATE;
uint16_t _TRACE_VTD_IOTLB_CC_HIT_DSTATE;
uint16_t _TRACE_VTD_IOTLB_CC_UPDATE_DSTATE;
uint16_t _TRACE_VTD_IOTLB_RESET_DSTATE;
uint16_t _TRACE_VTD_FAULT_DISABLED_DSTATE;
uint16_t _TRACE_VTD_REPLAY_CE_VALID_DSTATE;
uint16_t _TRACE_VTD_REPLAY_CE_INVALID_DSTATE;
uint16_t _TRACE_VTD_PAGE_WALK_LEVEL_DSTATE;
uint16_t _TRACE_VTD_PAGE_WALK_ONE_DSTATE;
uint16_t _TRACE_VTD_PAGE_WALK_ONE_SKIP_MAP_DSTATE;
uint16_t _TRACE_VTD_PAGE_WALK_ONE_SKIP_UNMAP_DSTATE;
uint16_t _TRACE_VTD_PAGE_WALK_SKIP_READ_DSTATE;
uint16_t _TRACE_VTD_PAGE_WALK_SKIP_RESERVE_DSTATE;
uint16_t _TRACE_VTD_SWITCH_ADDRESS_SPACE_DSTATE;
uint16_t _TRACE_VTD_AS_UNMAP_WHOLE_DSTATE;
uint16_t _TRACE_VTD_TRANSLATE_PT_DSTATE;
uint16_t _TRACE_VTD_PT_ENABLE_FAST_PATH_DSTATE;
uint16_t _TRACE_VTD_IRQ_GENERATE_DSTATE;
uint16_t _TRACE_VTD_REG_READ_DSTATE;
uint16_t _TRACE_VTD_REG_WRITE_DSTATE;
uint16_t _TRACE_VTD_REG_DMAR_ROOT_DSTATE;
uint16_t _TRACE_VTD_REG_IR_ROOT_DSTATE;
uint16_t _TRACE_VTD_REG_WRITE_GCMD_DSTATE;
uint16_t _TRACE_VTD_REG_WRITE_FECTL_DSTATE;
uint16_t _TRACE_VTD_REG_WRITE_IECTL_DSTATE;
uint16_t _TRACE_VTD_REG_ICS_CLEAR_IP_DSTATE;
uint16_t _TRACE_VTD_DMAR_TRANSLATE_DSTATE;
uint16_t _TRACE_VTD_DMAR_ENABLE_DSTATE;
uint16_t _TRACE_VTD_DMAR_FAULT_DSTATE;
uint16_t _TRACE_VTD_IR_ENABLE_DSTATE;
uint16_t _TRACE_VTD_IR_IRTE_GET_DSTATE;
uint16_t _TRACE_VTD_IR_REMAP_DSTATE;
uint16_t _TRACE_VTD_IR_REMAP_TYPE_DSTATE;
uint16_t _TRACE_VTD_IR_REMAP_MSI_DSTATE;
uint16_t _TRACE_VTD_IR_REMAP_MSI_REQ_DSTATE;
uint16_t _TRACE_VTD_FSTS_PPF_DSTATE;
uint16_t _TRACE_VTD_FSTS_CLEAR_IP_DSTATE;
uint16_t _TRACE_VTD_FRR_NEW_DSTATE;
uint16_t _TRACE_VTD_WARN_INVALID_QI_TAIL_DSTATE;
uint16_t _TRACE_VTD_WARN_IR_VECTOR_DSTATE;
uint16_t _TRACE_VTD_WARN_IR_TRIGGER_DSTATE;
uint16_t _TRACE_VTD_RESET_EXIT_DSTATE;
uint16_t _TRACE_AMDVI_EVNTLOG_FAIL_DSTATE;
uint16_t _TRACE_AMDVI_CACHE_UPDATE_DSTATE;
uint16_t _TRACE_AMDVI_COMPLETION_WAIT_FAIL_DSTATE;
uint16_t _TRACE_AMDVI_MMIO_WRITE_DSTATE;
uint16_t _TRACE_AMDVI_MMIO_READ_DSTATE;
uint16_t _TRACE_AMDVI_MMIO_READ_INVALID_DSTATE;
uint16_t _TRACE_AMDVI_COMMAND_ERROR_DSTATE;
uint16_t _TRACE_AMDVI_COMMAND_READ_FAIL_DSTATE;
uint16_t _TRACE_AMDVI_COMMAND_EXEC_DSTATE;
uint16_t _TRACE_AMDVI_UNHANDLED_COMMAND_DSTATE;
uint16_t _TRACE_AMDVI_INTR_INVAL_DSTATE;
uint16_t _TRACE_AMDVI_IOTLB_INVAL_DSTATE;
uint16_t _TRACE_AMDVI_PREFETCH_PAGES_DSTATE;
uint16_t _TRACE_AMDVI_PAGES_INVAL_DSTATE;
uint16_t _TRACE_AMDVI_ALL_INVAL_DSTATE;
uint16_t _TRACE_AMDVI_PPR_EXEC_DSTATE;
uint16_t _TRACE_AMDVI_DEVTAB_INVAL_DSTATE;
uint16_t _TRACE_AMDVI_COMPLETION_WAIT_DSTATE;
uint16_t _TRACE_AMDVI_CONTROL_STATUS_DSTATE;
uint16_t _TRACE_AMDVI_IOTLB_RESET_DSTATE;
uint16_t _TRACE_AMDVI_DTE_GET_FAIL_DSTATE;
uint16_t _TRACE_AMDVI_INVALID_DTE_DSTATE;
uint16_t _TRACE_AMDVI_GET_PTE_HWERROR_DSTATE;
uint16_t _TRACE_AMDVI_MODE_INVALID_DSTATE;
uint16_t _TRACE_AMDVI_PAGE_FAULT_DSTATE;
uint16_t _TRACE_AMDVI_IOTLB_HIT_DSTATE;
uint16_t _TRACE_AMDVI_TRANSLATION_RESULT_DSTATE;
uint16_t _TRACE_AMDVI_MEM_IR_WRITE_REQ_DSTATE;
uint16_t _TRACE_AMDVI_MEM_IR_WRITE_DSTATE;
uint16_t _TRACE_AMDVI_IR_REMAP_MSI_REQ_DSTATE;
uint16_t _TRACE_AMDVI_IR_REMAP_MSI_DSTATE;
uint16_t _TRACE_AMDVI_ERR_DSTATE;
uint16_t _TRACE_AMDVI_IR_IRTE_DSTATE;
uint16_t _TRACE_AMDVI_IR_IRTE_VAL_DSTATE;
uint16_t _TRACE_AMDVI_IR_ERR_DSTATE;
uint16_t _TRACE_AMDVI_IR_INTCTL_DSTATE;
uint16_t _TRACE_AMDVI_IR_TARGET_ABORT_DSTATE;
uint16_t _TRACE_AMDVI_IR_DELIVERY_MODE_DSTATE;
uint16_t _TRACE_AMDVI_IR_IRTE_GA_VAL_DSTATE;
uint16_t _TRACE_VMPORT_REGISTER_DSTATE;
uint16_t _TRACE_VMPORT_COMMAND_DSTATE;
uint16_t _TRACE_X86_GSI_INTERRUPT_DSTATE;
uint16_t _TRACE_X86_PIC_INTERRUPT_DSTATE;
uint16_t _TRACE_PORT92_READ_DSTATE;
uint16_t _TRACE_PORT92_WRITE_DSTATE;
uint16_t _TRACE_VMMOUSE_GET_STATUS_DSTATE;
uint16_t _TRACE_VMMOUSE_MOUSE_EVENT_DSTATE;
uint16_t _TRACE_VMMOUSE_INIT_DSTATE;
uint16_t _TRACE_VMMOUSE_READ_ID_DSTATE;
uint16_t _TRACE_VMMOUSE_REQUEST_RELATIVE_DSTATE;
uint16_t _TRACE_VMMOUSE_REQUEST_ABSOLUTE_DSTATE;
uint16_t _TRACE_VMMOUSE_DISABLE_DSTATE;
uint16_t _TRACE_VMMOUSE_DATA_DSTATE;
TraceEvent _TRACE_X86_IOMMU_IEC_NOTIFY_EVENT = {
    .id = 0,
    .name = "x86_iommu_iec_notify",
    .sstate = TRACE_X86_IOMMU_IEC_NOTIFY_ENABLED,
    .dstate = &_TRACE_X86_IOMMU_IEC_NOTIFY_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc",
    .sstate = TRACE_VTD_INV_DESC_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_CC_DOMAIN_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_cc_domain",
    .sstate = TRACE_VTD_INV_DESC_CC_DOMAIN_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_CC_DOMAIN_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_CC_GLOBAL_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_cc_global",
    .sstate = TRACE_VTD_INV_DESC_CC_GLOBAL_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_CC_GLOBAL_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_CC_DEVICE_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_cc_device",
    .sstate = TRACE_VTD_INV_DESC_CC_DEVICE_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_CC_DEVICE_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_CC_DEVICES_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_cc_devices",
    .sstate = TRACE_VTD_INV_DESC_CC_DEVICES_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_CC_DEVICES_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_IOTLB_GLOBAL_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_iotlb_global",
    .sstate = TRACE_VTD_INV_DESC_IOTLB_GLOBAL_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_IOTLB_GLOBAL_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_IOTLB_DOMAIN_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_iotlb_domain",
    .sstate = TRACE_VTD_INV_DESC_IOTLB_DOMAIN_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_IOTLB_DOMAIN_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_IOTLB_PAGES_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_iotlb_pages",
    .sstate = TRACE_VTD_INV_DESC_IOTLB_PAGES_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_IOTLB_PAGES_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_IOTLB_PASID_PAGES_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_iotlb_pasid_pages",
    .sstate = TRACE_VTD_INV_DESC_IOTLB_PASID_PAGES_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_IOTLB_PASID_PAGES_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_IOTLB_PASID_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_iotlb_pasid",
    .sstate = TRACE_VTD_INV_DESC_IOTLB_PASID_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_IOTLB_PASID_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_WAIT_SW_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_wait_sw",
    .sstate = TRACE_VTD_INV_DESC_WAIT_SW_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_WAIT_SW_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_WAIT_IRQ_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_wait_irq",
    .sstate = TRACE_VTD_INV_DESC_WAIT_IRQ_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_WAIT_IRQ_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_WAIT_WRITE_FAIL_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_wait_write_fail",
    .sstate = TRACE_VTD_INV_DESC_WAIT_WRITE_FAIL_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_WAIT_WRITE_FAIL_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_IEC_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_iec",
    .sstate = TRACE_VTD_INV_DESC_IEC_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_IEC_DSTATE
};
TraceEvent _TRACE_VTD_INV_QI_ENABLE_EVENT = {
    .id = 0,
    .name = "vtd_inv_qi_enable",
    .sstate = TRACE_VTD_INV_QI_ENABLE_ENABLED,
    .dstate = &_TRACE_VTD_INV_QI_ENABLE_DSTATE
};
TraceEvent _TRACE_VTD_INV_QI_SETUP_EVENT = {
    .id = 0,
    .name = "vtd_inv_qi_setup",
    .sstate = TRACE_VTD_INV_QI_SETUP_ENABLED,
    .dstate = &_TRACE_VTD_INV_QI_SETUP_DSTATE
};
TraceEvent _TRACE_VTD_INV_QI_HEAD_EVENT = {
    .id = 0,
    .name = "vtd_inv_qi_head",
    .sstate = TRACE_VTD_INV_QI_HEAD_ENABLED,
    .dstate = &_TRACE_VTD_INV_QI_HEAD_DSTATE
};
TraceEvent _TRACE_VTD_INV_QI_TAIL_EVENT = {
    .id = 0,
    .name = "vtd_inv_qi_tail",
    .sstate = TRACE_VTD_INV_QI_TAIL_ENABLED,
    .dstate = &_TRACE_VTD_INV_QI_TAIL_DSTATE
};
TraceEvent _TRACE_VTD_INV_QI_FETCH_EVENT = {
    .id = 0,
    .name = "vtd_inv_qi_fetch",
    .sstate = TRACE_VTD_INV_QI_FETCH_ENABLED,
    .dstate = &_TRACE_VTD_INV_QI_FETCH_DSTATE
};
TraceEvent _TRACE_VTD_CONTEXT_CACHE_RESET_EVENT = {
    .id = 0,
    .name = "vtd_context_cache_reset",
    .sstate = TRACE_VTD_CONTEXT_CACHE_RESET_ENABLED,
    .dstate = &_TRACE_VTD_CONTEXT_CACHE_RESET_DSTATE
};
TraceEvent _TRACE_VTD_PASID_CACHE_RESET_EVENT = {
    .id = 0,
    .name = "vtd_pasid_cache_reset",
    .sstate = TRACE_VTD_PASID_CACHE_RESET_ENABLED,
    .dstate = &_TRACE_VTD_PASID_CACHE_RESET_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_PASID_CACHE_GSI_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_pasid_cache_gsi",
    .sstate = TRACE_VTD_INV_DESC_PASID_CACHE_GSI_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_PASID_CACHE_GSI_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_PASID_CACHE_DSI_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_pasid_cache_dsi",
    .sstate = TRACE_VTD_INV_DESC_PASID_CACHE_DSI_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_PASID_CACHE_DSI_DSTATE
};
TraceEvent _TRACE_VTD_INV_DESC_PASID_CACHE_PSI_EVENT = {
    .id = 0,
    .name = "vtd_inv_desc_pasid_cache_psi",
    .sstate = TRACE_VTD_INV_DESC_PASID_CACHE_PSI_ENABLED,
    .dstate = &_TRACE_VTD_INV_DESC_PASID_CACHE_PSI_DSTATE
};
TraceEvent _TRACE_VTD_RE_NOT_PRESENT_EVENT = {
    .id = 0,
    .name = "vtd_re_not_present",
    .sstate = TRACE_VTD_RE_NOT_PRESENT_ENABLED,
    .dstate = &_TRACE_VTD_RE_NOT_PRESENT_DSTATE
};
TraceEvent _TRACE_VTD_CE_NOT_PRESENT_EVENT = {
    .id = 0,
    .name = "vtd_ce_not_present",
    .sstate = TRACE_VTD_CE_NOT_PRESENT_ENABLED,
    .dstate = &_TRACE_VTD_CE_NOT_PRESENT_DSTATE
};
TraceEvent _TRACE_VTD_IOTLB_PAGE_HIT_EVENT = {
    .id = 0,
    .name = "vtd_iotlb_page_hit",
    .sstate = TRACE_VTD_IOTLB_PAGE_HIT_ENABLED,
    .dstate = &_TRACE_VTD_IOTLB_PAGE_HIT_DSTATE
};
TraceEvent _TRACE_VTD_IOTLB_PAGE_UPDATE_EVENT = {
    .id = 0,
    .name = "vtd_iotlb_page_update",
    .sstate = TRACE_VTD_IOTLB_PAGE_UPDATE_ENABLED,
    .dstate = &_TRACE_VTD_IOTLB_PAGE_UPDATE_DSTATE
};
TraceEvent _TRACE_VTD_IOTLB_CC_HIT_EVENT = {
    .id = 0,
    .name = "vtd_iotlb_cc_hit",
    .sstate = TRACE_VTD_IOTLB_CC_HIT_ENABLED,
    .dstate = &_TRACE_VTD_IOTLB_CC_HIT_DSTATE
};
TraceEvent _TRACE_VTD_IOTLB_CC_UPDATE_EVENT = {
    .id = 0,
    .name = "vtd_iotlb_cc_update",
    .sstate = TRACE_VTD_IOTLB_CC_UPDATE_ENABLED,
    .dstate = &_TRACE_VTD_IOTLB_CC_UPDATE_DSTATE
};
TraceEvent _TRACE_VTD_IOTLB_RESET_EVENT = {
    .id = 0,
    .name = "vtd_iotlb_reset",
    .sstate = TRACE_VTD_IOTLB_RESET_ENABLED,
    .dstate = &_TRACE_VTD_IOTLB_RESET_DSTATE
};
TraceEvent _TRACE_VTD_FAULT_DISABLED_EVENT = {
    .id = 0,
    .name = "vtd_fault_disabled",
    .sstate = TRACE_VTD_FAULT_DISABLED_ENABLED,
    .dstate = &_TRACE_VTD_FAULT_DISABLED_DSTATE
};
TraceEvent _TRACE_VTD_REPLAY_CE_VALID_EVENT = {
    .id = 0,
    .name = "vtd_replay_ce_valid",
    .sstate = TRACE_VTD_REPLAY_CE_VALID_ENABLED,
    .dstate = &_TRACE_VTD_REPLAY_CE_VALID_DSTATE
};
TraceEvent _TRACE_VTD_REPLAY_CE_INVALID_EVENT = {
    .id = 0,
    .name = "vtd_replay_ce_invalid",
    .sstate = TRACE_VTD_REPLAY_CE_INVALID_ENABLED,
    .dstate = &_TRACE_VTD_REPLAY_CE_INVALID_DSTATE
};
TraceEvent _TRACE_VTD_PAGE_WALK_LEVEL_EVENT = {
    .id = 0,
    .name = "vtd_page_walk_level",
    .sstate = TRACE_VTD_PAGE_WALK_LEVEL_ENABLED,
    .dstate = &_TRACE_VTD_PAGE_WALK_LEVEL_DSTATE
};
TraceEvent _TRACE_VTD_PAGE_WALK_ONE_EVENT = {
    .id = 0,
    .name = "vtd_page_walk_one",
    .sstate = TRACE_VTD_PAGE_WALK_ONE_ENABLED,
    .dstate = &_TRACE_VTD_PAGE_WALK_ONE_DSTATE
};
TraceEvent _TRACE_VTD_PAGE_WALK_ONE_SKIP_MAP_EVENT = {
    .id = 0,
    .name = "vtd_page_walk_one_skip_map",
    .sstate = TRACE_VTD_PAGE_WALK_ONE_SKIP_MAP_ENABLED,
    .dstate = &_TRACE_VTD_PAGE_WALK_ONE_SKIP_MAP_DSTATE
};
TraceEvent _TRACE_VTD_PAGE_WALK_ONE_SKIP_UNMAP_EVENT = {
    .id = 0,
    .name = "vtd_page_walk_one_skip_unmap",
    .sstate = TRACE_VTD_PAGE_WALK_ONE_SKIP_UNMAP_ENABLED,
    .dstate = &_TRACE_VTD_PAGE_WALK_ONE_SKIP_UNMAP_DSTATE
};
TraceEvent _TRACE_VTD_PAGE_WALK_SKIP_READ_EVENT = {
    .id = 0,
    .name = "vtd_page_walk_skip_read",
    .sstate = TRACE_VTD_PAGE_WALK_SKIP_READ_ENABLED,
    .dstate = &_TRACE_VTD_PAGE_WALK_SKIP_READ_DSTATE
};
TraceEvent _TRACE_VTD_PAGE_WALK_SKIP_RESERVE_EVENT = {
    .id = 0,
    .name = "vtd_page_walk_skip_reserve",
    .sstate = TRACE_VTD_PAGE_WALK_SKIP_RESERVE_ENABLED,
    .dstate = &_TRACE_VTD_PAGE_WALK_SKIP_RESERVE_DSTATE
};
TraceEvent _TRACE_VTD_SWITCH_ADDRESS_SPACE_EVENT = {
    .id = 0,
    .name = "vtd_switch_address_space",
    .sstate = TRACE_VTD_SWITCH_ADDRESS_SPACE_ENABLED,
    .dstate = &_TRACE_VTD_SWITCH_ADDRESS_SPACE_DSTATE
};
TraceEvent _TRACE_VTD_AS_UNMAP_WHOLE_EVENT = {
    .id = 0,
    .name = "vtd_as_unmap_whole",
    .sstate = TRACE_VTD_AS_UNMAP_WHOLE_ENABLED,
    .dstate = &_TRACE_VTD_AS_UNMAP_WHOLE_DSTATE
};
TraceEvent _TRACE_VTD_TRANSLATE_PT_EVENT = {
    .id = 0,
    .name = "vtd_translate_pt",
    .sstate = TRACE_VTD_TRANSLATE_PT_ENABLED,
    .dstate = &_TRACE_VTD_TRANSLATE_PT_DSTATE
};
TraceEvent _TRACE_VTD_PT_ENABLE_FAST_PATH_EVENT = {
    .id = 0,
    .name = "vtd_pt_enable_fast_path",
    .sstate = TRACE_VTD_PT_ENABLE_FAST_PATH_ENABLED,
    .dstate = &_TRACE_VTD_PT_ENABLE_FAST_PATH_DSTATE
};
TraceEvent _TRACE_VTD_IRQ_GENERATE_EVENT = {
    .id = 0,
    .name = "vtd_irq_generate",
    .sstate = TRACE_VTD_IRQ_GENERATE_ENABLED,
    .dstate = &_TRACE_VTD_IRQ_GENERATE_DSTATE
};
TraceEvent _TRACE_VTD_REG_READ_EVENT = {
    .id = 0,
    .name = "vtd_reg_read",
    .sstate = TRACE_VTD_REG_READ_ENABLED,
    .dstate = &_TRACE_VTD_REG_READ_DSTATE
};
TraceEvent _TRACE_VTD_REG_WRITE_EVENT = {
    .id = 0,
    .name = "vtd_reg_write",
    .sstate = TRACE_VTD_REG_WRITE_ENABLED,
    .dstate = &_TRACE_VTD_REG_WRITE_DSTATE
};
TraceEvent _TRACE_VTD_REG_DMAR_ROOT_EVENT = {
    .id = 0,
    .name = "vtd_reg_dmar_root",
    .sstate = TRACE_VTD_REG_DMAR_ROOT_ENABLED,
    .dstate = &_TRACE_VTD_REG_DMAR_ROOT_DSTATE
};
TraceEvent _TRACE_VTD_REG_IR_ROOT_EVENT = {
    .id = 0,
    .name = "vtd_reg_ir_root",
    .sstate = TRACE_VTD_REG_IR_ROOT_ENABLED,
    .dstate = &_TRACE_VTD_REG_IR_ROOT_DSTATE
};
TraceEvent _TRACE_VTD_REG_WRITE_GCMD_EVENT = {
    .id = 0,
    .name = "vtd_reg_write_gcmd",
    .sstate = TRACE_VTD_REG_WRITE_GCMD_ENABLED,
    .dstate = &_TRACE_VTD_REG_WRITE_GCMD_DSTATE
};
TraceEvent _TRACE_VTD_REG_WRITE_FECTL_EVENT = {
    .id = 0,
    .name = "vtd_reg_write_fectl",
    .sstate = TRACE_VTD_REG_WRITE_FECTL_ENABLED,
    .dstate = &_TRACE_VTD_REG_WRITE_FECTL_DSTATE
};
TraceEvent _TRACE_VTD_REG_WRITE_IECTL_EVENT = {
    .id = 0,
    .name = "vtd_reg_write_iectl",
    .sstate = TRACE_VTD_REG_WRITE_IECTL_ENABLED,
    .dstate = &_TRACE_VTD_REG_WRITE_IECTL_DSTATE
};
TraceEvent _TRACE_VTD_REG_ICS_CLEAR_IP_EVENT = {
    .id = 0,
    .name = "vtd_reg_ics_clear_ip",
    .sstate = TRACE_VTD_REG_ICS_CLEAR_IP_ENABLED,
    .dstate = &_TRACE_VTD_REG_ICS_CLEAR_IP_DSTATE
};
TraceEvent _TRACE_VTD_DMAR_TRANSLATE_EVENT = {
    .id = 0,
    .name = "vtd_dmar_translate",
    .sstate = TRACE_VTD_DMAR_TRANSLATE_ENABLED,
    .dstate = &_TRACE_VTD_DMAR_TRANSLATE_DSTATE
};
TraceEvent _TRACE_VTD_DMAR_ENABLE_EVENT = {
    .id = 0,
    .name = "vtd_dmar_enable",
    .sstate = TRACE_VTD_DMAR_ENABLE_ENABLED,
    .dstate = &_TRACE_VTD_DMAR_ENABLE_DSTATE
};
TraceEvent _TRACE_VTD_DMAR_FAULT_EVENT = {
    .id = 0,
    .name = "vtd_dmar_fault",
    .sstate = TRACE_VTD_DMAR_FAULT_ENABLED,
    .dstate = &_TRACE_VTD_DMAR_FAULT_DSTATE
};
TraceEvent _TRACE_VTD_IR_ENABLE_EVENT = {
    .id = 0,
    .name = "vtd_ir_enable",
    .sstate = TRACE_VTD_IR_ENABLE_ENABLED,
    .dstate = &_TRACE_VTD_IR_ENABLE_DSTATE
};
TraceEvent _TRACE_VTD_IR_IRTE_GET_EVENT = {
    .id = 0,
    .name = "vtd_ir_irte_get",
    .sstate = TRACE_VTD_IR_IRTE_GET_ENABLED,
    .dstate = &_TRACE_VTD_IR_IRTE_GET_DSTATE
};
TraceEvent _TRACE_VTD_IR_REMAP_EVENT = {
    .id = 0,
    .name = "vtd_ir_remap",
    .sstate = TRACE_VTD_IR_REMAP_ENABLED,
    .dstate = &_TRACE_VTD_IR_REMAP_DSTATE
};
TraceEvent _TRACE_VTD_IR_REMAP_TYPE_EVENT = {
    .id = 0,
    .name = "vtd_ir_remap_type",
    .sstate = TRACE_VTD_IR_REMAP_TYPE_ENABLED,
    .dstate = &_TRACE_VTD_IR_REMAP_TYPE_DSTATE
};
TraceEvent _TRACE_VTD_IR_REMAP_MSI_EVENT = {
    .id = 0,
    .name = "vtd_ir_remap_msi",
    .sstate = TRACE_VTD_IR_REMAP_MSI_ENABLED,
    .dstate = &_TRACE_VTD_IR_REMAP_MSI_DSTATE
};
TraceEvent _TRACE_VTD_IR_REMAP_MSI_REQ_EVENT = {
    .id = 0,
    .name = "vtd_ir_remap_msi_req",
    .sstate = TRACE_VTD_IR_REMAP_MSI_REQ_ENABLED,
    .dstate = &_TRACE_VTD_IR_REMAP_MSI_REQ_DSTATE
};
TraceEvent _TRACE_VTD_FSTS_PPF_EVENT = {
    .id = 0,
    .name = "vtd_fsts_ppf",
    .sstate = TRACE_VTD_FSTS_PPF_ENABLED,
    .dstate = &_TRACE_VTD_FSTS_PPF_DSTATE
};
TraceEvent _TRACE_VTD_FSTS_CLEAR_IP_EVENT = {
    .id = 0,
    .name = "vtd_fsts_clear_ip",
    .sstate = TRACE_VTD_FSTS_CLEAR_IP_ENABLED,
    .dstate = &_TRACE_VTD_FSTS_CLEAR_IP_DSTATE
};
TraceEvent _TRACE_VTD_FRR_NEW_EVENT = {
    .id = 0,
    .name = "vtd_frr_new",
    .sstate = TRACE_VTD_FRR_NEW_ENABLED,
    .dstate = &_TRACE_VTD_FRR_NEW_DSTATE
};
TraceEvent _TRACE_VTD_WARN_INVALID_QI_TAIL_EVENT = {
    .id = 0,
    .name = "vtd_warn_invalid_qi_tail",
    .sstate = TRACE_VTD_WARN_INVALID_QI_TAIL_ENABLED,
    .dstate = &_TRACE_VTD_WARN_INVALID_QI_TAIL_DSTATE
};
TraceEvent _TRACE_VTD_WARN_IR_VECTOR_EVENT = {
    .id = 0,
    .name = "vtd_warn_ir_vector",
    .sstate = TRACE_VTD_WARN_IR_VECTOR_ENABLED,
    .dstate = &_TRACE_VTD_WARN_IR_VECTOR_DSTATE
};
TraceEvent _TRACE_VTD_WARN_IR_TRIGGER_EVENT = {
    .id = 0,
    .name = "vtd_warn_ir_trigger",
    .sstate = TRACE_VTD_WARN_IR_TRIGGER_ENABLED,
    .dstate = &_TRACE_VTD_WARN_IR_TRIGGER_DSTATE
};
TraceEvent _TRACE_VTD_RESET_EXIT_EVENT = {
    .id = 0,
    .name = "vtd_reset_exit",
    .sstate = TRACE_VTD_RESET_EXIT_ENABLED,
    .dstate = &_TRACE_VTD_RESET_EXIT_DSTATE
};
TraceEvent _TRACE_AMDVI_EVNTLOG_FAIL_EVENT = {
    .id = 0,
    .name = "amdvi_evntlog_fail",
    .sstate = TRACE_AMDVI_EVNTLOG_FAIL_ENABLED,
    .dstate = &_TRACE_AMDVI_EVNTLOG_FAIL_DSTATE
};
TraceEvent _TRACE_AMDVI_CACHE_UPDATE_EVENT = {
    .id = 0,
    .name = "amdvi_cache_update",
    .sstate = TRACE_AMDVI_CACHE_UPDATE_ENABLED,
    .dstate = &_TRACE_AMDVI_CACHE_UPDATE_DSTATE
};
TraceEvent _TRACE_AMDVI_COMPLETION_WAIT_FAIL_EVENT = {
    .id = 0,
    .name = "amdvi_completion_wait_fail",
    .sstate = TRACE_AMDVI_COMPLETION_WAIT_FAIL_ENABLED,
    .dstate = &_TRACE_AMDVI_COMPLETION_WAIT_FAIL_DSTATE
};
TraceEvent _TRACE_AMDVI_MMIO_WRITE_EVENT = {
    .id = 0,
    .name = "amdvi_mmio_write",
    .sstate = TRACE_AMDVI_MMIO_WRITE_ENABLED,
    .dstate = &_TRACE_AMDVI_MMIO_WRITE_DSTATE
};
TraceEvent _TRACE_AMDVI_MMIO_READ_EVENT = {
    .id = 0,
    .name = "amdvi_mmio_read",
    .sstate = TRACE_AMDVI_MMIO_READ_ENABLED,
    .dstate = &_TRACE_AMDVI_MMIO_READ_DSTATE
};
TraceEvent _TRACE_AMDVI_MMIO_READ_INVALID_EVENT = {
    .id = 0,
    .name = "amdvi_mmio_read_invalid",
    .sstate = TRACE_AMDVI_MMIO_READ_INVALID_ENABLED,
    .dstate = &_TRACE_AMDVI_MMIO_READ_INVALID_DSTATE
};
TraceEvent _TRACE_AMDVI_COMMAND_ERROR_EVENT = {
    .id = 0,
    .name = "amdvi_command_error",
    .sstate = TRACE_AMDVI_COMMAND_ERROR_ENABLED,
    .dstate = &_TRACE_AMDVI_COMMAND_ERROR_DSTATE
};
TraceEvent _TRACE_AMDVI_COMMAND_READ_FAIL_EVENT = {
    .id = 0,
    .name = "amdvi_command_read_fail",
    .sstate = TRACE_AMDVI_COMMAND_READ_FAIL_ENABLED,
    .dstate = &_TRACE_AMDVI_COMMAND_READ_FAIL_DSTATE
};
TraceEvent _TRACE_AMDVI_COMMAND_EXEC_EVENT = {
    .id = 0,
    .name = "amdvi_command_exec",
    .sstate = TRACE_AMDVI_COMMAND_EXEC_ENABLED,
    .dstate = &_TRACE_AMDVI_COMMAND_EXEC_DSTATE
};
TraceEvent _TRACE_AMDVI_UNHANDLED_COMMAND_EVENT = {
    .id = 0,
    .name = "amdvi_unhandled_command",
    .sstate = TRACE_AMDVI_UNHANDLED_COMMAND_ENABLED,
    .dstate = &_TRACE_AMDVI_UNHANDLED_COMMAND_DSTATE
};
TraceEvent _TRACE_AMDVI_INTR_INVAL_EVENT = {
    .id = 0,
    .name = "amdvi_intr_inval",
    .sstate = TRACE_AMDVI_INTR_INVAL_ENABLED,
    .dstate = &_TRACE_AMDVI_INTR_INVAL_DSTATE
};
TraceEvent _TRACE_AMDVI_IOTLB_INVAL_EVENT = {
    .id = 0,
    .name = "amdvi_iotlb_inval",
    .sstate = TRACE_AMDVI_IOTLB_INVAL_ENABLED,
    .dstate = &_TRACE_AMDVI_IOTLB_INVAL_DSTATE
};
TraceEvent _TRACE_AMDVI_PREFETCH_PAGES_EVENT = {
    .id = 0,
    .name = "amdvi_prefetch_pages",
    .sstate = TRACE_AMDVI_PREFETCH_PAGES_ENABLED,
    .dstate = &_TRACE_AMDVI_PREFETCH_PAGES_DSTATE
};
TraceEvent _TRACE_AMDVI_PAGES_INVAL_EVENT = {
    .id = 0,
    .name = "amdvi_pages_inval",
    .sstate = TRACE_AMDVI_PAGES_INVAL_ENABLED,
    .dstate = &_TRACE_AMDVI_PAGES_INVAL_DSTATE
};
TraceEvent _TRACE_AMDVI_ALL_INVAL_EVENT = {
    .id = 0,
    .name = "amdvi_all_inval",
    .sstate = TRACE_AMDVI_ALL_INVAL_ENABLED,
    .dstate = &_TRACE_AMDVI_ALL_INVAL_DSTATE
};
TraceEvent _TRACE_AMDVI_PPR_EXEC_EVENT = {
    .id = 0,
    .name = "amdvi_ppr_exec",
    .sstate = TRACE_AMDVI_PPR_EXEC_ENABLED,
    .dstate = &_TRACE_AMDVI_PPR_EXEC_DSTATE
};
TraceEvent _TRACE_AMDVI_DEVTAB_INVAL_EVENT = {
    .id = 0,
    .name = "amdvi_devtab_inval",
    .sstate = TRACE_AMDVI_DEVTAB_INVAL_ENABLED,
    .dstate = &_TRACE_AMDVI_DEVTAB_INVAL_DSTATE
};
TraceEvent _TRACE_AMDVI_COMPLETION_WAIT_EVENT = {
    .id = 0,
    .name = "amdvi_completion_wait",
    .sstate = TRACE_AMDVI_COMPLETION_WAIT_ENABLED,
    .dstate = &_TRACE_AMDVI_COMPLETION_WAIT_DSTATE
};
TraceEvent _TRACE_AMDVI_CONTROL_STATUS_EVENT = {
    .id = 0,
    .name = "amdvi_control_status",
    .sstate = TRACE_AMDVI_CONTROL_STATUS_ENABLED,
    .dstate = &_TRACE_AMDVI_CONTROL_STATUS_DSTATE
};
TraceEvent _TRACE_AMDVI_IOTLB_RESET_EVENT = {
    .id = 0,
    .name = "amdvi_iotlb_reset",
    .sstate = TRACE_AMDVI_IOTLB_RESET_ENABLED,
    .dstate = &_TRACE_AMDVI_IOTLB_RESET_DSTATE
};
TraceEvent _TRACE_AMDVI_DTE_GET_FAIL_EVENT = {
    .id = 0,
    .name = "amdvi_dte_get_fail",
    .sstate = TRACE_AMDVI_DTE_GET_FAIL_ENABLED,
    .dstate = &_TRACE_AMDVI_DTE_GET_FAIL_DSTATE
};
TraceEvent _TRACE_AMDVI_INVALID_DTE_EVENT = {
    .id = 0,
    .name = "amdvi_invalid_dte",
    .sstate = TRACE_AMDVI_INVALID_DTE_ENABLED,
    .dstate = &_TRACE_AMDVI_INVALID_DTE_DSTATE
};
TraceEvent _TRACE_AMDVI_GET_PTE_HWERROR_EVENT = {
    .id = 0,
    .name = "amdvi_get_pte_hwerror",
    .sstate = TRACE_AMDVI_GET_PTE_HWERROR_ENABLED,
    .dstate = &_TRACE_AMDVI_GET_PTE_HWERROR_DSTATE
};
TraceEvent _TRACE_AMDVI_MODE_INVALID_EVENT = {
    .id = 0,
    .name = "amdvi_mode_invalid",
    .sstate = TRACE_AMDVI_MODE_INVALID_ENABLED,
    .dstate = &_TRACE_AMDVI_MODE_INVALID_DSTATE
};
TraceEvent _TRACE_AMDVI_PAGE_FAULT_EVENT = {
    .id = 0,
    .name = "amdvi_page_fault",
    .sstate = TRACE_AMDVI_PAGE_FAULT_ENABLED,
    .dstate = &_TRACE_AMDVI_PAGE_FAULT_DSTATE
};
TraceEvent _TRACE_AMDVI_IOTLB_HIT_EVENT = {
    .id = 0,
    .name = "amdvi_iotlb_hit",
    .sstate = TRACE_AMDVI_IOTLB_HIT_ENABLED,
    .dstate = &_TRACE_AMDVI_IOTLB_HIT_DSTATE
};
TraceEvent _TRACE_AMDVI_TRANSLATION_RESULT_EVENT = {
    .id = 0,
    .name = "amdvi_translation_result",
    .sstate = TRACE_AMDVI_TRANSLATION_RESULT_ENABLED,
    .dstate = &_TRACE_AMDVI_TRANSLATION_RESULT_DSTATE
};
TraceEvent _TRACE_AMDVI_MEM_IR_WRITE_REQ_EVENT = {
    .id = 0,
    .name = "amdvi_mem_ir_write_req",
    .sstate = TRACE_AMDVI_MEM_IR_WRITE_REQ_ENABLED,
    .dstate = &_TRACE_AMDVI_MEM_IR_WRITE_REQ_DSTATE
};
TraceEvent _TRACE_AMDVI_MEM_IR_WRITE_EVENT = {
    .id = 0,
    .name = "amdvi_mem_ir_write",
    .sstate = TRACE_AMDVI_MEM_IR_WRITE_ENABLED,
    .dstate = &_TRACE_AMDVI_MEM_IR_WRITE_DSTATE
};
TraceEvent _TRACE_AMDVI_IR_REMAP_MSI_REQ_EVENT = {
    .id = 0,
    .name = "amdvi_ir_remap_msi_req",
    .sstate = TRACE_AMDVI_IR_REMAP_MSI_REQ_ENABLED,
    .dstate = &_TRACE_AMDVI_IR_REMAP_MSI_REQ_DSTATE
};
TraceEvent _TRACE_AMDVI_IR_REMAP_MSI_EVENT = {
    .id = 0,
    .name = "amdvi_ir_remap_msi",
    .sstate = TRACE_AMDVI_IR_REMAP_MSI_ENABLED,
    .dstate = &_TRACE_AMDVI_IR_REMAP_MSI_DSTATE
};
TraceEvent _TRACE_AMDVI_ERR_EVENT = {
    .id = 0,
    .name = "amdvi_err",
    .sstate = TRACE_AMDVI_ERR_ENABLED,
    .dstate = &_TRACE_AMDVI_ERR_DSTATE
};
TraceEvent _TRACE_AMDVI_IR_IRTE_EVENT = {
    .id = 0,
    .name = "amdvi_ir_irte",
    .sstate = TRACE_AMDVI_IR_IRTE_ENABLED,
    .dstate = &_TRACE_AMDVI_IR_IRTE_DSTATE
};
TraceEvent _TRACE_AMDVI_IR_IRTE_VAL_EVENT = {
    .id = 0,
    .name = "amdvi_ir_irte_val",
    .sstate = TRACE_AMDVI_IR_IRTE_VAL_ENABLED,
    .dstate = &_TRACE_AMDVI_IR_IRTE_VAL_DSTATE
};
TraceEvent _TRACE_AMDVI_IR_ERR_EVENT = {
    .id = 0,
    .name = "amdvi_ir_err",
    .sstate = TRACE_AMDVI_IR_ERR_ENABLED,
    .dstate = &_TRACE_AMDVI_IR_ERR_DSTATE
};
TraceEvent _TRACE_AMDVI_IR_INTCTL_EVENT = {
    .id = 0,
    .name = "amdvi_ir_intctl",
    .sstate = TRACE_AMDVI_IR_INTCTL_ENABLED,
    .dstate = &_TRACE_AMDVI_IR_INTCTL_DSTATE
};
TraceEvent _TRACE_AMDVI_IR_TARGET_ABORT_EVENT = {
    .id = 0,
    .name = "amdvi_ir_target_abort",
    .sstate = TRACE_AMDVI_IR_TARGET_ABORT_ENABLED,
    .dstate = &_TRACE_AMDVI_IR_TARGET_ABORT_DSTATE
};
TraceEvent _TRACE_AMDVI_IR_DELIVERY_MODE_EVENT = {
    .id = 0,
    .name = "amdvi_ir_delivery_mode",
    .sstate = TRACE_AMDVI_IR_DELIVERY_MODE_ENABLED,
    .dstate = &_TRACE_AMDVI_IR_DELIVERY_MODE_DSTATE
};
TraceEvent _TRACE_AMDVI_IR_IRTE_GA_VAL_EVENT = {
    .id = 0,
    .name = "amdvi_ir_irte_ga_val",
    .sstate = TRACE_AMDVI_IR_IRTE_GA_VAL_ENABLED,
    .dstate = &_TRACE_AMDVI_IR_IRTE_GA_VAL_DSTATE
};
TraceEvent _TRACE_VMPORT_REGISTER_EVENT = {
    .id = 0,
    .name = "vmport_register",
    .sstate = TRACE_VMPORT_REGISTER_ENABLED,
    .dstate = &_TRACE_VMPORT_REGISTER_DSTATE
};
TraceEvent _TRACE_VMPORT_COMMAND_EVENT = {
    .id = 0,
    .name = "vmport_command",
    .sstate = TRACE_VMPORT_COMMAND_ENABLED,
    .dstate = &_TRACE_VMPORT_COMMAND_DSTATE
};
TraceEvent _TRACE_X86_GSI_INTERRUPT_EVENT = {
    .id = 0,
    .name = "x86_gsi_interrupt",
    .sstate = TRACE_X86_GSI_INTERRUPT_ENABLED,
    .dstate = &_TRACE_X86_GSI_INTERRUPT_DSTATE
};
TraceEvent _TRACE_X86_PIC_INTERRUPT_EVENT = {
    .id = 0,
    .name = "x86_pic_interrupt",
    .sstate = TRACE_X86_PIC_INTERRUPT_ENABLED,
    .dstate = &_TRACE_X86_PIC_INTERRUPT_DSTATE
};
TraceEvent _TRACE_PORT92_READ_EVENT = {
    .id = 0,
    .name = "port92_read",
    .sstate = TRACE_PORT92_READ_ENABLED,
    .dstate = &_TRACE_PORT92_READ_DSTATE
};
TraceEvent _TRACE_PORT92_WRITE_EVENT = {
    .id = 0,
    .name = "port92_write",
    .sstate = TRACE_PORT92_WRITE_ENABLED,
    .dstate = &_TRACE_PORT92_WRITE_DSTATE
};
TraceEvent _TRACE_VMMOUSE_GET_STATUS_EVENT = {
    .id = 0,
    .name = "vmmouse_get_status",
    .sstate = TRACE_VMMOUSE_GET_STATUS_ENABLED,
    .dstate = &_TRACE_VMMOUSE_GET_STATUS_DSTATE
};
TraceEvent _TRACE_VMMOUSE_MOUSE_EVENT_EVENT = {
    .id = 0,
    .name = "vmmouse_mouse_event",
    .sstate = TRACE_VMMOUSE_MOUSE_EVENT_ENABLED,
    .dstate = &_TRACE_VMMOUSE_MOUSE_EVENT_DSTATE
};
TraceEvent _TRACE_VMMOUSE_INIT_EVENT = {
    .id = 0,
    .name = "vmmouse_init",
    .sstate = TRACE_VMMOUSE_INIT_ENABLED,
    .dstate = &_TRACE_VMMOUSE_INIT_DSTATE
};
TraceEvent _TRACE_VMMOUSE_READ_ID_EVENT = {
    .id = 0,
    .name = "vmmouse_read_id",
    .sstate = TRACE_VMMOUSE_READ_ID_ENABLED,
    .dstate = &_TRACE_VMMOUSE_READ_ID_DSTATE
};
TraceEvent _TRACE_VMMOUSE_REQUEST_RELATIVE_EVENT = {
    .id = 0,
    .name = "vmmouse_request_relative",
    .sstate = TRACE_VMMOUSE_REQUEST_RELATIVE_ENABLED,
    .dstate = &_TRACE_VMMOUSE_REQUEST_RELATIVE_DSTATE
};
TraceEvent _TRACE_VMMOUSE_REQUEST_ABSOLUTE_EVENT = {
    .id = 0,
    .name = "vmmouse_request_absolute",
    .sstate = TRACE_VMMOUSE_REQUEST_ABSOLUTE_ENABLED,
    .dstate = &_TRACE_VMMOUSE_REQUEST_ABSOLUTE_DSTATE
};
TraceEvent _TRACE_VMMOUSE_DISABLE_EVENT = {
    .id = 0,
    .name = "vmmouse_disable",
    .sstate = TRACE_VMMOUSE_DISABLE_ENABLED,
    .dstate = &_TRACE_VMMOUSE_DISABLE_DSTATE
};
TraceEvent _TRACE_VMMOUSE_DATA_EVENT = {
    .id = 0,
    .name = "vmmouse_data",
    .sstate = TRACE_VMMOUSE_DATA_ENABLED,
    .dstate = &_TRACE_VMMOUSE_DATA_DSTATE
};
TraceEvent *hw_i386_trace_events[] = {
    &_TRACE_X86_IOMMU_IEC_NOTIFY_EVENT,
    &_TRACE_VTD_INV_DESC_EVENT,
    &_TRACE_VTD_INV_DESC_CC_DOMAIN_EVENT,
    &_TRACE_VTD_INV_DESC_CC_GLOBAL_EVENT,
    &_TRACE_VTD_INV_DESC_CC_DEVICE_EVENT,
    &_TRACE_VTD_INV_DESC_CC_DEVICES_EVENT,
    &_TRACE_VTD_INV_DESC_IOTLB_GLOBAL_EVENT,
    &_TRACE_VTD_INV_DESC_IOTLB_DOMAIN_EVENT,
    &_TRACE_VTD_INV_DESC_IOTLB_PAGES_EVENT,
    &_TRACE_VTD_INV_DESC_IOTLB_PASID_PAGES_EVENT,
    &_TRACE_VTD_INV_DESC_IOTLB_PASID_EVENT,
    &_TRACE_VTD_INV_DESC_WAIT_SW_EVENT,
    &_TRACE_VTD_INV_DESC_WAIT_IRQ_EVENT,
    &_TRACE_VTD_INV_DESC_WAIT_WRITE_FAIL_EVENT,
    &_TRACE_VTD_INV_DESC_IEC_EVENT,
    &_TRACE_VTD_INV_QI_ENABLE_EVENT,
    &_TRACE_VTD_INV_QI_SETUP_EVENT,
    &_TRACE_VTD_INV_QI_HEAD_EVENT,
    &_TRACE_VTD_INV_QI_TAIL_EVENT,
    &_TRACE_VTD_INV_QI_FETCH_EVENT,
    &_TRACE_VTD_CONTEXT_CACHE_RESET_EVENT,
    &_TRACE_VTD_PASID_CACHE_RESET_EVENT,
    &_TRACE_VTD_INV_DESC_PASID_CACHE_GSI_EVENT,
    &_TRACE_VTD_INV_DESC_PASID_CACHE_DSI_EVENT,
    &_TRACE_VTD_INV_DESC_PASID_CACHE_PSI_EVENT,
    &_TRACE_VTD_RE_NOT_PRESENT_EVENT,
    &_TRACE_VTD_CE_NOT_PRESENT_EVENT,
    &_TRACE_VTD_IOTLB_PAGE_HIT_EVENT,
    &_TRACE_VTD_IOTLB_PAGE_UPDATE_EVENT,
    &_TRACE_VTD_IOTLB_CC_HIT_EVENT,
    &_TRACE_VTD_IOTLB_CC_UPDATE_EVENT,
    &_TRACE_VTD_IOTLB_RESET_EVENT,
    &_TRACE_VTD_FAULT_DISABLED_EVENT,
    &_TRACE_VTD_REPLAY_CE_VALID_EVENT,
    &_TRACE_VTD_REPLAY_CE_INVALID_EVENT,
    &_TRACE_VTD_PAGE_WALK_LEVEL_EVENT,
    &_TRACE_VTD_PAGE_WALK_ONE_EVENT,
    &_TRACE_VTD_PAGE_WALK_ONE_SKIP_MAP_EVENT,
    &_TRACE_VTD_PAGE_WALK_ONE_SKIP_UNMAP_EVENT,
    &_TRACE_VTD_PAGE_WALK_SKIP_READ_EVENT,
    &_TRACE_VTD_PAGE_WALK_SKIP_RESERVE_EVENT,
    &_TRACE_VTD_SWITCH_ADDRESS_SPACE_EVENT,
    &_TRACE_VTD_AS_UNMAP_WHOLE_EVENT,
    &_TRACE_VTD_TRANSLATE_PT_EVENT,
    &_TRACE_VTD_PT_ENABLE_FAST_PATH_EVENT,
    &_TRACE_VTD_IRQ_GENERATE_EVENT,
    &_TRACE_VTD_REG_READ_EVENT,
    &_TRACE_VTD_REG_WRITE_EVENT,
    &_TRACE_VTD_REG_DMAR_ROOT_EVENT,
    &_TRACE_VTD_REG_IR_ROOT_EVENT,
    &_TRACE_VTD_REG_WRITE_GCMD_EVENT,
    &_TRACE_VTD_REG_WRITE_FECTL_EVENT,
    &_TRACE_VTD_REG_WRITE_IECTL_EVENT,
    &_TRACE_VTD_REG_ICS_CLEAR_IP_EVENT,
    &_TRACE_VTD_DMAR_TRANSLATE_EVENT,
    &_TRACE_VTD_DMAR_ENABLE_EVENT,
    &_TRACE_VTD_DMAR_FAULT_EVENT,
    &_TRACE_VTD_IR_ENABLE_EVENT,
    &_TRACE_VTD_IR_IRTE_GET_EVENT,
    &_TRACE_VTD_IR_REMAP_EVENT,
    &_TRACE_VTD_IR_REMAP_TYPE_EVENT,
    &_TRACE_VTD_IR_REMAP_MSI_EVENT,
    &_TRACE_VTD_IR_REMAP_MSI_REQ_EVENT,
    &_TRACE_VTD_FSTS_PPF_EVENT,
    &_TRACE_VTD_FSTS_CLEAR_IP_EVENT,
    &_TRACE_VTD_FRR_NEW_EVENT,
    &_TRACE_VTD_WARN_INVALID_QI_TAIL_EVENT,
    &_TRACE_VTD_WARN_IR_VECTOR_EVENT,
    &_TRACE_VTD_WARN_IR_TRIGGER_EVENT,
    &_TRACE_VTD_RESET_EXIT_EVENT,
    &_TRACE_AMDVI_EVNTLOG_FAIL_EVENT,
    &_TRACE_AMDVI_CACHE_UPDATE_EVENT,
    &_TRACE_AMDVI_COMPLETION_WAIT_FAIL_EVENT,
    &_TRACE_AMDVI_MMIO_WRITE_EVENT,
    &_TRACE_AMDVI_MMIO_READ_EVENT,
    &_TRACE_AMDVI_MMIO_READ_INVALID_EVENT,
    &_TRACE_AMDVI_COMMAND_ERROR_EVENT,
    &_TRACE_AMDVI_COMMAND_READ_FAIL_EVENT,
    &_TRACE_AMDVI_COMMAND_EXEC_EVENT,
    &_TRACE_AMDVI_UNHANDLED_COMMAND_EVENT,
    &_TRACE_AMDVI_INTR_INVAL_EVENT,
    &_TRACE_AMDVI_IOTLB_INVAL_EVENT,
    &_TRACE_AMDVI_PREFETCH_PAGES_EVENT,
    &_TRACE_AMDVI_PAGES_INVAL_EVENT,
    &_TRACE_AMDVI_ALL_INVAL_EVENT,
    &_TRACE_AMDVI_PPR_EXEC_EVENT,
    &_TRACE_AMDVI_DEVTAB_INVAL_EVENT,
    &_TRACE_AMDVI_COMPLETION_WAIT_EVENT,
    &_TRACE_AMDVI_CONTROL_STATUS_EVENT,
    &_TRACE_AMDVI_IOTLB_RESET_EVENT,
    &_TRACE_AMDVI_DTE_GET_FAIL_EVENT,
    &_TRACE_AMDVI_INVALID_DTE_EVENT,
    &_TRACE_AMDVI_GET_PTE_HWERROR_EVENT,
    &_TRACE_AMDVI_MODE_INVALID_EVENT,
    &_TRACE_AMDVI_PAGE_FAULT_EVENT,
    &_TRACE_AMDVI_IOTLB_HIT_EVENT,
    &_TRACE_AMDVI_TRANSLATION_RESULT_EVENT,
    &_TRACE_AMDVI_MEM_IR_WRITE_REQ_EVENT,
    &_TRACE_AMDVI_MEM_IR_WRITE_EVENT,
    &_TRACE_AMDVI_IR_REMAP_MSI_REQ_EVENT,
    &_TRACE_AMDVI_IR_REMAP_MSI_EVENT,
    &_TRACE_AMDVI_ERR_EVENT,
    &_TRACE_AMDVI_IR_IRTE_EVENT,
    &_TRACE_AMDVI_IR_IRTE_VAL_EVENT,
    &_TRACE_AMDVI_IR_ERR_EVENT,
    &_TRACE_AMDVI_IR_INTCTL_EVENT,
    &_TRACE_AMDVI_IR_TARGET_ABORT_EVENT,
    &_TRACE_AMDVI_IR_DELIVERY_MODE_EVENT,
    &_TRACE_AMDVI_IR_IRTE_GA_VAL_EVENT,
    &_TRACE_VMPORT_REGISTER_EVENT,
    &_TRACE_VMPORT_COMMAND_EVENT,
    &_TRACE_X86_GSI_INTERRUPT_EVENT,
    &_TRACE_X86_PIC_INTERRUPT_EVENT,
    &_TRACE_PORT92_READ_EVENT,
    &_TRACE_PORT92_WRITE_EVENT,
    &_TRACE_VMMOUSE_GET_STATUS_EVENT,
    &_TRACE_VMMOUSE_MOUSE_EVENT_EVENT,
    &_TRACE_VMMOUSE_INIT_EVENT,
    &_TRACE_VMMOUSE_READ_ID_EVENT,
    &_TRACE_VMMOUSE_REQUEST_RELATIVE_EVENT,
    &_TRACE_VMMOUSE_REQUEST_ABSOLUTE_EVENT,
    &_TRACE_VMMOUSE_DISABLE_EVENT,
    &_TRACE_VMMOUSE_DATA_EVENT,
  NULL,
};

static void trace_hw_i386_register_events(void)
{
    trace_event_register_group(hw_i386_trace_events);
}
trace_init(trace_hw_i386_register_events)
